FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10K ® Embedded Programmable Logic Family October 1998, ver. 3.13 Data Sheet Features... ■ The industryÕs first embedded programmable logic device (PLD) family, providing system integration in a single device Ð Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions Ð Logic array for general logic functions ■ High density Ð 10,000 to 250,000 typical gates (see Tables 1 and 2) Ð Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity ■ System-level features Ð MultiVoltª I/O interface support Ð 5.0-V tolerant input pins in FLEX¨ 10KA devices Ð Low power consumption (typical specification less than 0.5 mA in standby mode for most devices) Ð FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest GroupÕs (PCI-SIG) PCI Local Bus Specification, Revision 2.1 Ð FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance Ð Select FLEX 10KA devices support 5.0-V PCI buses with eight or fewer loads Ð Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming any device logic Table 1. FLEX 10K Device Features Feature EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K10A EPF10K30A EPF10K50V Typical gates (logic and RAM), 10,000 20,000 30,000 40,000 50,000 Note (1) Usable gates 7,000 to 15,000 to 22,000 to 29,000 to 36,000 to 31,000 63,000 69,000 93,000 116,000 Logic elements (LEs) 576 1,152 1,728 2,304 2,880 Logic array blocks (LABs) 72 144 216 288 360 Embedded array blocks (EABs) 366810 Total RAM bits 6,144 12,288 12,288 16,384 20,480 Maximum user I/O pins 134 189 246 189 310 Altera Corporation 1 A-DS-F10K-03.13 FLEX 10K Embedded Programmable Logic Family Data Sheet Table 2.
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