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Research, Development and Testing of a Fault-Tolerant Fpga-Based Sequencer for Cubesat Launching Applications

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Research, Development and Testing of a Fault-Tolerant Fpga-Based Sequencer for Cubesat Launching Applications Calhoun: The NPS Institutional Archive Theses and Dissertations Thesis Collection 2013-03 RESEARCH, DEVELOPMENT AND TESTING OF A FAULT-TOLERANT FPGA-BASED SEQUENCER FOR CUBESAT LAUNCHING APPLICATIONS Parobek, Lucas S. Monterey, California. Naval Postgraduate School http://hdl.handle.net/10945/32882 NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS RESEARCH, DEVELOPMENT AND TESTING OF A FAULT-TOLERANT FPGA-BASED SEQUENCER FOR CUBESAT LAUNCHING APPLICATIONS by Lucas S. Parobek March 2013 Thesis Co-Advisors: Herschel H. Loomis, Jr. James H. Newman Approved for public release; distribution is unlimited THIS PAGE INTENTIONALLY LEFT BLANK REPORT DOCUMENTATION PAGE Form Approved OMB No. 0704–0188 Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instruction, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202–4302, and to the Office of Management and Budget, Paperwork Reduction Project (0704–0188) Washington DC 20503. 1. AGENCY USE ONLY (Leave blank) 2. REPORT DATE 3. REPORT TYPE AND DATES COVERED March 2013 Master’s Thesis 4. TITLE AND SUBTITLE RESEARCH, DEVELOPMENT AND TESTING OF 5. FUNDING NUMBERS A FAULT-TOLERANT FPGA-BASED SEQUENCER FOR CUBESAT LAUNCHING APPLICATIONS 6. AUTHOR(S) Lucas S. Parobek 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION Naval Postgraduate School REPORT NUMBER Monterey, CA 93943–5000 9. SPONSORING /MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSORING/MONITORING N/A AGENCY REPORT NUMBER 11. SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. IRB Protocol number ______N/A______. 12a. DISTRIBUTION / AVAILABILITY STATEMENT 12b. DISTRIBUTION CODE Approved for public release; distribution is unlimited A 13. ABSTRACT (maximum 200 words) This thesis concerns various means of implementing fault tolerance in logic for use in a general payload processor design. The first specific application of this research is a sequencer developed for deploying CubeSats. The sequencer shall be capable of the timing and accurate deployment of multiple CubeSats from a host spacecraft and shall have the capability for quick reconfiguration prior to launch. This research considers a variety of hardware for suitability toward sequencer construction; field programmable gate arrays (FPGAs) are chosen as the primary device. The design further evolves to selection of the Actel ProASIC3 series of FPGAs. Initial logic test configurations are implemented on a development kit with analysis of results provided. Fault-tolerant techniques are compared with a set of experiments to determine optimum resource utilization and timing schemes. Triple modular redundancy (TMR) is selected as the technique for fault-tolerant logic implementation in the sequencer. Preliminary test boards are built via schematic design and printed circuit board layout. The manufacturing, integration and testing of the ‘ProASIC3 Test Board’ is fully discussed. A follow-on flight prototype board is designed with more extensive hardware allowing for implementation of fault-tolerant techniques and future growth capability. Recommendations for future work are discussed. 14. SUBJECT TERMS Single-Event Effect (SEE), Single-Event Upset (SEU), Multiple-Bit Upset 15. NUMBER OF (MBU), Field Programmable Gate Array (FPGA), Fault Tolerance, Triple Modular Redundancy PAGES (TMR), Quadruple Force Decide Redundancy (QFDR), Quadded Logic, CubeSat, Satellite, Altium, 224 Actel, Microsemi, ProASIC3, Xilinx, Virtex 16. PRICE CODE 17. SECURITY 18. SECURITY 19. SECURITY 20. LIMITATION OF CLASSIFICATION OF CLASSIFICATION OF THIS CLASSIFICATION OF ABSTRACT REPORT PAGE ABSTRACT Unclassified Unclassified Unclassified UU NSN 7540–01–280–5500 Standard Form 298 (Rev. 2–89) Prescribed by ANSI Std. 239–18 i THIS PAGE INTENTIONALLY LEFT BLANK ii Approved for public release; distribution is unlimited RESEARCH, DEVELOPMENT AND TESTING OF A FAULT-TOLERANT FPGA-BASED SEQUENCER FOR CUBESAT LAUNCHING APPLICATIONS Lucas S. Parobek Lieutenant, United States Navy B.S., The Citadel, 2006 Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL March 2013 Author: Lucas S. Parobek Approved by: Herschel H. Loomis, Jr. Thesis Co-Advisor James H. Newman Thesis Co-Advisor Clark Robertson Chair, Department of Electrical and Computer Engineering iii THIS PAGE INTENTIONALLY LEFT BLANK iv ABSTRACT This thesis concerns various means of implementing fault tolerance in logic for use in a general payload processor design. The first specific application of this research is a sequencer developed for deploying CubeSats. The sequencer shall be capable of the timing and accurate deployment of multiple CubeSats from a host spacecraft and shall have the capability for quick reconfiguration prior to launch. This research considers a variety of hardware for suitability toward sequencer construction; field programmable gate arrays (FPGAs) are chosen as the primary device. The design further evolves to selection of the Actel ProASIC3 series of FPGAs. Initial logic test configurations are implemented on a development kit with analysis of results provided. Fault-tolerant techniques are compared with a set of experiments to determine optimum resource utilization and timing schemes. Triple modular redundancy (TMR) is selected as the technique for fault-tolerant logic implementation in the sequencer. Preliminary test boards are built via schematic design and printed circuit board layout. The manufacturing, integration and testing of the ‘ProASIC3 Test Board’ is fully discussed. A follow-on flight prototype board is designed with more extensive hardware allowing for implementation of fault-tolerant techniques and future growth capability. Recommendations for future work are discussed. v THIS PAGE INTENTIONALLY LEFT BLANK vi TABLE OF CONTENTS I. INTRODUCTION........................................................................................................1 A. PURPOSE .........................................................................................................1 B. NAVAL POSTGRADUATE SCHOOL CUBESAT LAUNCHER (NPSCUL) BACKGROUND...........................................................................3 1. NPSCuL Objective and History .........................................................3 2. NPSCuL Physical Design Characteristics .........................................3 3. History of Sequencer Requirement ....................................................5 4. Concept of Sequencer Development ...................................................6 5. Sequencer Requirements and Specifications .....................................7 C. RELATED WORK AND DOCUMENTATION ..........................................9 D. CONCEPT OF DEVELOPMENT STRATEGY ........................................10 E. THESIS ORGANIZATION ..........................................................................11 II. SEQUENCERS, RADIATION HARDENING, AND FAULT-TOLERANCE ...13 A. SEQUENCER DESIGN METHODOLOGY ..............................................13 1. Timing Concerns Specific to Initiating P-POD Deployment .........13 2. Chosen Approach ...............................................................................14 B. RADIATION HARDENING ........................................................................15 1. Single-Event Effects (SEEs) ..............................................................16 a. Single-Event Upsets (SEUs) ...................................................17 b. Single-Event Transients (SETs) .............................................18 c. Single-Event Latch-ups (SELs) ..............................................19 2. Total Ionizing Dose (TID) .................................................................19 3. Testing of FPGA Hardware in Radiation Environments ...............20 4. Radiation Protection Approaches ....................................................20 C. FAULT TOLERANCE ..................................................................................23 1. Scrubbing / Re-programming at Intervals ......................................23 2. Triple Modular Redundancy (TMR) ...............................................24 a. Block TMR (BTMR) ...............................................................24 b. Local TMR (LTMR) ................................................................25 c. Global TMR (GTMR)..............................................................25 d. Distributed TMR (DTMR) ......................................................26 3. Quadded Logic ...................................................................................27 4. Triplicated Interwoven Redundancy (TIR) ....................................28 5. Quadruple Force Decide Redundancy (QFDR) ..............................30 6. Advantages and Disadvantages of Various Fault-Tolerant Techniques ..........................................................................................31 D. CHAPTER
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