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January 1977 I
CALIFORNIA STATE UN:::VERSITY, NORTHRIDGE HICROPROCESSORS / A graduate p~ojc~t report s~~oitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering .. I by Thor,las Carson Hecht ~- .January 1977 i The graduate project report of Thomas Carson Hecht is approved: California State University, Northridge Oitober 1976 ii TABLE OF CONTENTS TITLE PAGE i. 1-.PPROVAL PAGE i.i LIST OF FIGURES i.v ABSTRP.C'I' vii INTRODUCTION 1 INTRODUCTION 1'0 MICROPROCESSORS 3 THE 6800 HINIHAL SYSTEM 7 THE HICROCOMPUTER ... , .. ,~ .. c•<~c•••••••••••••,.tt•••••••.••,•·•••••-~~·•'~••oo 18 }!ICROELECTRONIC P.ESISTOiZS AND RESISTOR TRH'lMING 31 AJ!FL ICATT.O!'·! OF THE HICROCOI'-1PUTER TO LASER TRIH~llNG R),DJIR ERRORS AND THEIR CORRECTION 65 THE ERROR COF,RECI'TON SYSTEM •••••••c••••.,••••••••••••••• .. •-ta•••••·• 69 THE HICROPROCESSOR SYSTEN 34 LIHJ.TATWNS AND ACCURACY 97 SUNNARY 100 APPENDIX A 6800 IN.~)J'RUC.TIO.N S.&T •••••••••••••••••••• 102 APPEND IX E HOTOIWLA 6800 .CI.ROJ LTS -t.~ ...... ~ ... , ............. ~ ............... 105 lJ:'FENDIX C C.ALCJJL.A.TOR .CHIP DATA SH.EET •• , , .•••• , .•••.•••••••••••• llO 'I + .. .;:,. .. t •· II " • • • 115 BIBLlOGR.t,PHY ••••••••• otto'W ...... ll9 Li.i LIST OF FIGURES FIGURE 1: THE 6800 Mli'Hr·L'\L SYSTEH FIGURE 2: OPERATION OF THE ACIA FIGURE 3: OPERATION OF THE PIA FIGURE Lf: BLOCK DIAGRP..H OF THE PIA/CALCULATOR CHIP INTERFACE FIGURE 5: SCHEHATIC AND TRUTH TABLE OF THE PRIOP.ITY ENCODER FIGURE 6: SCHElv!ATIC OF THE QUAD AND FIGURE 7: SCHEHATIC OF 'I'JIE TNTERRUPT PRIORITY CIRCUIT FIGURE 8: LOCATIONS ADDRESSED BY THE MPU FOR DIFFERENT PRIORITY Ii'fTERlWPTS FIGURE 9: .tv1EHORY H1\P OF THE MICROCOl1PUTER FIGURE 10: CALCULATION OF RESISTANCE USING SQUARES AND SHEET RESISTANCE FIGURE 11: DIFFERENT TYPES OF TRIHS FIGURE 12: RESISTANCE AS A FUNCTION OF TRHllviiNG FIGURE 13: PLOT OF % OF INCREASE IN RESISTANCE VS. -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
ED135388.Pdf
DOCUMENT RESUME ED 135 388 IB 004 499 AUTHOR Kirby, Paul J.; Gardner, Edward M. Tin! Microcomputer Controlled, interactive Testing Terminal Development. INSTITUTION Air Force Human Resources lab., Lowry AFB, Colo. Technical Training Div. SPONS AGENCY Air Force Human Resources Lab., Brooks AFB, Texas. REPORT NO AIHEI-TR-76-66 PUB DATE Oct 76 NOTE 27p. EDRS PRICE MF-$0.83 HC-$2.06 Plus Postage. DESCRIPTORS Autcinstructional Aids; Computer Programs; *Computer Science; *Individual Tests; Man Machine Systems; Self Pacing Machines; *Testing; *Test Scoring Machines IDENTIFIERS Microcomputers ABSTRACT The evolution of a self-contained test scoring terminal is presented. The rationale for thedesign is presented along with an evolutionary description ofthe requirements for the system. The sequence of software andhardware tools, which were developed in order to build the device, are alsodescribed in this report. The resulting device,which contains an imbedded microcomputer is functionally described and the testingstrategies which it cur.rently supports axe presented.(Author) *********************************************************************** * Dcraents acquired by ERIC include many informalunpublished * *materls not available from other sources. ERICmakes every effort * *to obtain tbe best copyavailable. Nevertheless, items of marginal * *reproducibility are often encountered andthis affects the quality * *of the microfiche and hardcopyxeproductions ERIC makes available * *via the ERIC Document ReproductionService (EDRS). EDRS is not * *responsible -
Technician's Guide to 68HC11 Microcontroller.Pdf
chapter 1 Introduction to Computer Hardware Objectives I ntr odu ct ion to Com put er H ardw are After completing this chapter, you should be able to: ◗ Describe the fundamental elements of every computer system: proces- sor, memory, and input/output ◗ Compare elements of the HC11 block diagram to the fundamentals of every computer system ◗ Describe the use of busses to connect computer elements ◗ Explain the three major functional units of a processor ◗ Illustrate the typical registers inside the processor ◗ List the HC11 processor registers ◗ Discuss the HC11 processor modes ◗ Compare and contrast various memory types ◗ Describe the on-chip memory of the HC11 ◗ Specify input/output functions present on most computers ◗ Use some basic BUFFALO commands to control the EVBU Outline ◗ 1.1 Elements of Every Computer ◗ 1.2 Elements of Processors ◗ 1.3 Introduction to Memory ◗ 1.4 Memory Types ◗ 1.5 Input/Output 1 ◗ 1.6 EVBU/BUFFALO Technician’s Guide to the 68HC11 Microcontroller Introduction Computer systems have been developed for a variety of functions and purposes. General-application desktop machines are the most common. They run a variety of software applications, such as word processing, financial management and data processing. They have all but replaced the typewriter as a necessary business tool. Computers are also present in automobiles, appliances, airplanes and all types of controllers and electromechanical devices. Despite the differences among these computer systems, they all share fundamental components and design. The purpose of this chapter is to provide an understanding of the fundamental components of a computer system. A conceptual presentation regarding the elements of every computer system is made with sufficient detail to establish a foundation for these concepts. -
Part 21 Rept Re Marking of Motorola 8-Bit Microprocessor Family
. o *" ']w', ('', , . 1, ;, * , ' i VICTOREEN, INC. - 10101 WDODLAND AVE., CLE(ELAND, DillD 44104 . VICTOREEN "" "*:'''*1'****** = m i n o l a :'' * * * ' August 19, 1983 'i ' . ' U. S. Nuclear Regulatory Commission Region III 799 Roosevelt Road Glen Allyn, IL 60137 . Attentior. Mr. Robert Gregor Subject: 10CFR21 Repertable Data . Reference: Phone conversation of 8/18/83 Dear Mr. Gregor: In accordance with 10CFR21, VICT0REEN, INC. shall use this letter to formally document our phone co'nversation of 8/18/83 as well as transmit our written report. On 8/18/83, your department was notified by phone . of a potential defect involving the marking of the Motorola 8-Bit Microprocessor (MPU's) Family. The defect involves the letter designa- tion utilized on the Hi-Re1 products which was changed to indicate tem- perature classifications of the microprocessor. What follows is the written report required as per 10CFR21 Paragraph 21.21 b2 and b3., , MD Ref: B3.i.) q VICTOREEN, INC. t 10101 Woodland Avenue ,g O-[* Cleveland, Ohio 44104 /k Attention: Roger Zimmerman, Q. A. Manager, and Attention: Ken Stafford, Reliability Manager | | Ref: B3.ii) i The facilities which may contain the basic component is as follows: Facility Type of VICTOREEN Equipment . Midland, Units 1 & 2 Quantity of 12 Class IE Area Radiation Monitors Model No. M861CD Indian Point Ouantity of 2 Class 1E High i Range Containment Monitor Model No. M861CD h , s p 8309070411 830831 g gDRADOCK05000 A shener o obe comoreon sues.o ry | . m . _ _ ._ . d - . P:gs 2 - , ~ . U. S. Nuclear Regulatory Commission , . Region III Clen Allyn, IL 60137 ,. -
Renesas General-Purpose Microcontrollers/Microprocessors Lineup Catalog
Renesas General-Purpose Microcontrollers/Microprocessors Lineup Catalog Notes: Renesas General-Purpose Microcontrollers/Microprocessors 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or Lineup Catalog others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. -
Eindhoven University of Technology MASTER Embedded Sensing Platform for Smart Urban Spaces Garza Salas, A
Eindhoven University of Technology MASTER Embedded sensing platform for smart urban spaces Garza Salas, A. Award date: 2015 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Embedded Sensing Platform for Smart Urban Spaces Eindhoven University of Technology Faculty of Electrical Engineering Royal Philips N.V. - Research Master Embedded Systems Author: Amado Garza Salas - 0827000 [email protected] Date: 9 January 2015 Supervisors: prof. dr. ir. Gerard de Haan dr. ir. Frank van Heesch ir. Ruben Rajagopalan Acknowledgement I would like to express my gratitude towards prof. dr. ir. Gerard de Haan for providing me with this opportunity, as well as for his involvement, supervision and support during the realization of this project. -
Addressing Mode 1 Addressing Mode
Addressing mode 1 Addressing mode Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. In computer programming, addressing modes are primarily of interest to compiler writers and to those who write code directly in assembly language. Caveats Note that there is no generally accepted way of naming the various addressing modes. In particular, different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer (CISC) computer architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal/immediate constants as just another addressing mode. Others, such as the IBM System/390 and most reduced instruction set computer (RISC) designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single "MOV" instruction. -
System-On-A-Chip
System-on-a-chip From Wikipedia, the free encyclopedia Jump to: navigation, search System-on-a-chip or system on chip (SoC or SOC) is an idea of integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. SoC is believed to be more cost effective since it increases the yield of the fabrication and because its packaging is simpler. Contents [hide] • 1 Structure • 2 Design flow • 3 Fabrication • 4 See also • 5 External links [edit] Structure y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller-based System-on-a-Chip A typical SoC consists of: • One or more microcontroller, microprocessor or DSP core(s). • Memory blocks including a selection of ROM, RAM, EEPROM and Flash. • Timing sources including oscillators and phase-locked loops. • Peripherals including counter-timers, real-time timers and power-on reset generators. • External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI. • Analog interfaces including ADCs and DACs. • Voltage regulators and power management circuits. These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. -
Dimsport Spain C/ Alt De Gironella, 11 - 13 08017 BARCELONA - SPAIN T (+34) 932895900 F (+34) 932233 E-Mail: [email protected] a Company of Empresa Del Grupo
Dimsport Spain C/ Alt de Gironella, 11 - 13 08017 BARCELONA - SPAIN T (+34) 932895900 F (+34) 932233 E-mail: [email protected] a company of empresa del grupo SPAIN www.dimsport.es REPROGRAMACIÓN DE CENTRALITAS CARS & TRUCKS TRACTORS MOTORBIKES MARINE OFFROAD CVC Performance Febbraio 2015 SPAIN [email protected] www.dim-sport.com www.cvc-performance.com Holdim Srl gathers and promotes solid companies operating in the Automotive feld such as Dimsport and Ecomotive Solutions. The founders operate together since 1991: thanks to their experience in the electronics, software and technologies applied to the Automotive, the structure has grown fast and frmly, becoming a point of reference worldwide. Through its brands, manufacturing facilities and commercial branches operating all over the world, Holdim offers a complete range of products and solutions dedicated to professionals aiming at achieving outstanding results on the customization of electronically managed engines of cars, bikes, light commercial vehicles, heavy duty trucks, buses, tractors and marine applications. D-GID – technological platform to convert diesel engines to Our leading product lines are: dual fuel systems (DDF) RACE – customization of the engine working parameters of original ECUs/ECMs Research and excellence in engineering are the keys to RAPID – add-on modules for electronically controlled turbo Holdim’s advanced solutions. The Group puts customers frst; diesel and turbo petrol engines their professional needs are met since their frst approach and RAPID BIKE – add-on modules & racing control units for bikes are guaranteed by a whole lot of quality products and services DYNO – chassis dynamometers and road simulators for all provided after purchase. -
Electronic Design Automation Software the Aha! Moment
THE AUTHORITY ON EMERGING TECHNOLOGIES FOR DESIGN SOLUTIONS March 2015 electronicdesign.com Powered by 503EDECover-Tip.indd 1 2/2/15 2:56 PM 150112_BOMM_ELECDES_US.indd 1 1/5/15 4:26 PM SMT Assembly for Engineers THE AUTHORITY ON EMERGING TECHNOLOGIES FOR DESIGN SOLUTIONSS March 2015 electronicdesign.com Powered by 300 Watts. Zero Wait. Coilcraft PL300 Series planar transformers. Stacked with performance. Available from stock. We’ve packed a lot of performance into our Best of all, these Coilcraft planars are new compact planar transformers. Rated available from stock, so order your free for 300 Watts, the PL300 Series offers DCR evaluation samples today! as low as 7.2 mOhms and leakage induc- Learn more about the tance down to 0.25 µH. PL300 and its 160 Watt They are AEC-Q200 Grade 1 qualifed companion, the PL160, for automotive applications and provide by visiting us online at 1500 Vrms primary-to-secondary isolation. www.coilcraft.com/PL. Coilcraft also offers the 160 W rated PL160 Series ® WWW.COILCRAFT.COM Keysight W2211BP Advanced Design System electronic design automation software The Aha! moment. W2351EP ADS DDR4 Compliance Test Bench We’ll help you feel it. It takes more than silicon to push the limits of DDR memory. It also takes gray matter. The stuff inside your head. A brain capable of genuine insight. If you’re a DDR design engineer, we can give you expert advice from some of the brightest minds in the measurement world. And our end-to-end solutions range from simulation software to advanced hardware. Working together, they can help you determine precisely where your memory challenges are and how to overcome them. -
The Embedded Experts
The Embedded Experts Debug Probes Software Tools RTOS File System Compression Connectivity Security & IoT User Interface Production Debug Probes J-Link SEGGER Embedded Studio n Features n J-Link Debug Probes n Supports Arm® Cortex®-M / R / A cores, including the 64-bit cores (ARMv8-A) and Arm® 7 / 9 / 11, Microchip PIC32, Renesas RX, RISC-V and Silicon Labs 8051 SEGGER J-Links are the most widely used line of also adds support for corner cases that cannot be debug probes available today. They have proven their supported without such intelligence. n Maximum JTAG speed 15 MHz, J-Link ULTRA+ / PRO: 50 MHz worth for more than 15 years with over 1 Mio units in A sample for such a scenario is: Accessing a slowly n Download speed up to 1.5 MB/s (J-Link® / J-Link® PLUS), 3 MB/s (J-Link® ULTRA+ / PRO) the field. This popularity stems from the unparalleled running CPU at high target interface speeds. J-Links n Power profiling (J-Link® ULTRA+ / PRO) performance, extensive feature set, large number of are the most robust probe in these situations. n Very fast flash loader supported CPUs and compatibility with all popular n Supported by all popular debuggers development environments. n Software Development Kit (SDK) n Support for different debug interfaces: JTAG / SWD / FINE / SPD / ICSP For customers who want to build their n Debug smarter and faster with J-Link! own applications using J-Link, and for n Serial Wire Viewer (SWV) with up to 7.5 / 25 MHz supported With up to 3 MByte per second download speed IDE vendors who implement J-Link n Host interface: USB, Ethernet to RAM and record-breaking flashloaders, and with support for their IDE, SEGGER n Power over USB the ability to set an unlimited number of breakpoints offers a J-Link SDK which n Support for adaptive clocking in flash memory of MCUs, J-Link debug probes comes with the J-Link DLL, n Multi-core debugging supported are undoubtedly the best choice to optimize your the API documentation and debugging and flash programming experience.