Addressing Mode 1 Addressing Mode
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January 1977 I
CALIFORNIA STATE UN:::VERSITY, NORTHRIDGE HICROPROCESSORS / A graduate p~ojc~t report s~~oitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering .. I by Thor,las Carson Hecht ~- .January 1977 i The graduate project report of Thomas Carson Hecht is approved: California State University, Northridge Oitober 1976 ii TABLE OF CONTENTS TITLE PAGE i. 1-.PPROVAL PAGE i.i LIST OF FIGURES i.v ABSTRP.C'I' vii INTRODUCTION 1 INTRODUCTION 1'0 MICROPROCESSORS 3 THE 6800 HINIHAL SYSTEM 7 THE HICROCOMPUTER ... , .. ,~ .. c•<~c•••••••••••••,.tt•••••••.••,•·•••••-~~·•'~••oo 18 }!ICROELECTRONIC P.ESISTOiZS AND RESISTOR TRH'lMING 31 AJ!FL ICATT.O!'·! OF THE HICROCOI'-1PUTER TO LASER TRIH~llNG R),DJIR ERRORS AND THEIR CORRECTION 65 THE ERROR COF,RECI'TON SYSTEM •••••••c••••.,••••••••••••••• .. •-ta•••••·• 69 THE HICROPROCESSOR SYSTEN 34 LIHJ.TATWNS AND ACCURACY 97 SUNNARY 100 APPENDIX A 6800 IN.~)J'RUC.TIO.N S.&T •••••••••••••••••••• 102 APPEND IX E HOTOIWLA 6800 .CI.ROJ LTS -t.~ ...... ~ ... , ............. ~ ............... 105 lJ:'FENDIX C C.ALCJJL.A.TOR .CHIP DATA SH.EET •• , , .•••• , .•••.•••••••••••• llO 'I + .. .;:,. .. t •· II " • • • 115 BIBLlOGR.t,PHY ••••••••• otto'W ...... ll9 Li.i LIST OF FIGURES FIGURE 1: THE 6800 Mli'Hr·L'\L SYSTEH FIGURE 2: OPERATION OF THE ACIA FIGURE 3: OPERATION OF THE PIA FIGURE Lf: BLOCK DIAGRP..H OF THE PIA/CALCULATOR CHIP INTERFACE FIGURE 5: SCHEHATIC AND TRUTH TABLE OF THE PRIOP.ITY ENCODER FIGURE 6: SCHElv!ATIC OF THE QUAD AND FIGURE 7: SCHEHATIC OF 'I'JIE TNTERRUPT PRIORITY CIRCUIT FIGURE 8: LOCATIONS ADDRESSED BY THE MPU FOR DIFFERENT PRIORITY Ii'fTERlWPTS FIGURE 9: .tv1EHORY H1\P OF THE MICROCOl1PUTER FIGURE 10: CALCULATION OF RESISTANCE USING SQUARES AND SHEET RESISTANCE FIGURE 11: DIFFERENT TYPES OF TRIHS FIGURE 12: RESISTANCE AS A FUNCTION OF TRHllviiNG FIGURE 13: PLOT OF % OF INCREASE IN RESISTANCE VS. -
Programming Model, Address Mode, HC12 Hardware Introduction
EEL 4744C: Microprocessor Applications Lecture 2 Programming Model, Address Mode, HC12 Hardware Introduction Dr. Tao Li 1 Reading Assignment • Microcontrollers and Microcomputers: Chapter 3, Chapter 4 • Software and Hardware Engineering: Chapter 2 Or • Software and Hardware Engineering: Chapter 4 Plus • CPU12 Reference Manual: Chapter 3 • M68HC12B Family Data Sheet: Chapter 1, 2, 3, 4 Dr. Tao Li 2 EEL 4744C: Microprocessor Applications Lecture 2 Part 1 CPU Registers and Control Codes Dr. Tao Li 3 CPU Registers • Accumulators – Registers that accumulate answers, e.g. the A Register – Can work simultaneously as the source register for one operand and the destination register for ALU operations • General-purpose registers – Registers that hold data, work as source and destination register for data transfers and source for ALU operations • Doubled registers – An N-bit CPU in general uses N-bit data registers – Sometimes 2 of the N-bit registers are used together to double the number of bits, thus “doubled” registers Dr. Tao Li 4 CPU Registers (2) • Pointer registers – Registers that address memory by pointing to specific memory locations that hold the needed data – Contain memory addresses (without offset) • Stack pointer registers – Pointer registers dedicated to variable data and return address storage in subroutine calls • Index registers – Also used to address memory – An effective memory address is found by adding an offset to the content of the involved index register Dr. Tao Li 5 CPU Registers (3) • Segment registers – In some architectures, memory addressing requires that the physical address be specified in 2 parts • Segment part: specifies a memory page • Offset part: specifies a particular place in the page • Condition code registers – Also called flag or status registers – Hold condition code bits generated when instructions are executed, e.g. -
The Birth, Evolution and Future of Microprocessor
The Birth, Evolution and Future of Microprocessor Swetha Kogatam Computer Science Department San Jose State University San Jose, CA 95192 408-924-1000 [email protected] ABSTRACT timed sequence through the bus system to output devices such as The world's first microprocessor, the 4004, was co-developed by CRT Screens, networks, or printers. In some cases, the terms Busicom, a Japanese manufacturer of calculators, and Intel, a U.S. 'CPU' and 'microprocessor' are used interchangeably to denote the manufacturer of semiconductors. The basic architecture of 4004 same device. was developed in August 1969; a concrete plan for the 4004 The different ways in which microprocessors are categorized are: system was finalized in December 1969; and the first microprocessor was successfully developed in March 1971. a) CISC (Complex Instruction Set Computers) Microprocessors, which became the "technology to open up a new b) RISC (Reduced Instruction Set Computers) era," brought two outstanding impacts, "power of intelligence" and "power of computing". First, microprocessors opened up a new a) VLIW(Very Long Instruction Word Computers) "era of programming" through replacing with software, the b) Super scalar processors hardwired logic based on IC's of the former "era of logic". At the same time, microprocessors allowed young engineers access to "power of computing" for the creative development of personal 2. BIRTH OF THE MICROPROCESSOR computers and computer games, which in turn led to growth in the In 1970, Intel introduced the first dynamic RAM, which increased software industry, and paved the way to the development of high- IC memory by a factor of four. -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
ED135388.Pdf
DOCUMENT RESUME ED 135 388 IB 004 499 AUTHOR Kirby, Paul J.; Gardner, Edward M. Tin! Microcomputer Controlled, interactive Testing Terminal Development. INSTITUTION Air Force Human Resources lab., Lowry AFB, Colo. Technical Training Div. SPONS AGENCY Air Force Human Resources Lab., Brooks AFB, Texas. REPORT NO AIHEI-TR-76-66 PUB DATE Oct 76 NOTE 27p. EDRS PRICE MF-$0.83 HC-$2.06 Plus Postage. DESCRIPTORS Autcinstructional Aids; Computer Programs; *Computer Science; *Individual Tests; Man Machine Systems; Self Pacing Machines; *Testing; *Test Scoring Machines IDENTIFIERS Microcomputers ABSTRACT The evolution of a self-contained test scoring terminal is presented. The rationale for thedesign is presented along with an evolutionary description ofthe requirements for the system. The sequence of software andhardware tools, which were developed in order to build the device, are alsodescribed in this report. The resulting device,which contains an imbedded microcomputer is functionally described and the testingstrategies which it cur.rently supports axe presented.(Author) *********************************************************************** * Dcraents acquired by ERIC include many informalunpublished * *materls not available from other sources. ERICmakes every effort * *to obtain tbe best copyavailable. Nevertheless, items of marginal * *reproducibility are often encountered andthis affects the quality * *of the microfiche and hardcopyxeproductions ERIC makes available * *via the ERIC Document ReproductionService (EDRS). EDRS is not * *responsible -
IBM Z/Architecture Reference Summary
z/Architecture IBMr Reference Summary SA22-7871-06 . z/Architecture IBMr Reference Summary SA22-7871-06 Seventh Edition (August, 2010) This revision differs from the previous edition by containing instructions related to the facilities marked by a bar under “Facility” in “Preface” and minor corrections and clari- fications. Changes are indicated by a bar in the margin. References in this publication to IBM® products, programs, or services do not imply that IBM intends to make these available in all countries in which IBM operates. Any reference to an IBM program product in this publication is not intended to state or imply that only IBM’s program product may be used. Any functionally equivalent pro- gram may be used instead. Additional copies of this and other IBM publications may be ordered or downloaded from the IBM publications web site at http://www.ibm.com/support/documentation. Please direct any comments on the contents of this publication to: IBM Corporation Department E57 2455 South Road Poughkeepsie, NY 12601-5400 USA IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring any obligation to you. © Copyright International Business Machines Corporation 2001-2010. All rights reserved. US Government Users Restricted Rights — Use, duplication, or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. ii z/Architecture Reference Summary Preface This publication is intended primarily for use by z/Architecture™ assembler-language application programmers. It contains basic machine information summarized from the IBM z/Architecture Principles of Operation, SA22-7832, about the zSeries™ proces- sors. It also contains frequently used information from IBM ESA/390 Common I/O- Device Commands and Self Description, SA22-7204, IBM System/370 Extended Architecture Interpretive Execution, SA22-7095, and IBM High Level Assembler for MVS & VM & VSE Language Reference, SC26-4940. -
ARM® Developer Suite Version 1.1
ARM® Developer Suite Version 1.1 Assembler Guide Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A ARM Developer Suite Assembler Guide Copyright © 2000 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Change November 2000 A Release 1.1 Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. ii Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A Contents Assembler Guide Preface About this book .............................................................................................. vi Feedback ....................................................................................................... ix Chapter 1 Introduction 1.1 About the ARM Developer Suite assemblers .............................................. 1-2 Chapter 2 Writing ARM and Thumb Assembly Language 2.1 Introduction ................................................................................................ -
Computer Organization
Chapter 12 Computer Organization Central Processing Unit (CPU) • Data section ‣ Receives data from and sends data to the main memory subsystem and I/O devices • Control section ‣ Issues the control signals to the data section and the other components of the computer system Figure 12.1 CPU Input Data Control Main Output device section section Memory device Bus Data flow Control CPU components • 16-bit memory address register (MAR) ‣ 8-bit MARA and 8-bit MARB • 8-bit memory data register (MDR) • 8-bit multiplexers ‣ AMux, CMux, MDRMux ‣ 0 on control line routes left input ‣ 1 on control line routes right input Control signals • Originate from the control section on the right (not shown in Figure 12.2) • Two kinds of control signals ‣ Clock signals end in “Ck” to load data into registers with a clock pulse ‣ Signals that do not end in “Ck” to set up the data flow before each clock pulse arrives 0 1 8 14 15 22 23 A IR T3 M1 0x00 0x01 2 3 9 10 16 17 24 25 LoadCk Figure 12.2 X T4 M2 0x02 0x03 4 5 11 18 19 26 27 5 C SP T1 T5 M3 0x04 0x08 5 6 7 12 13 20 21 28 29 B PC T2 T6 M4 0xFA 0xFC 5 30 31 A CPU registers M5 0xFE 0xFF CBus ABus BBus Bus MARB MARCk MARA MDRCk MDR MDRMux AMux AMux MDRMux CMux 4 ALU ALU CMux Cin Cout C CCk Mem V VCk ANDZ Addr ANDZ Z ZCk Zout 0 Data 0 0 0 N NCk MemWrite MemRead Figure 12.2 (Expanded) 0 1 8 14 15 22 23 A IR T3 M1 0x00 0x01 2 3 9 10 16 17 24 25 LoadCk X T4 M2 0x02 0x03 4 5 11 18 19 26 27 5 C SP T1 T5 M3 0x04 0x08 5 6 7 12 13 20 21 28 29 B PC T2 T6 M4 0xFA 0xFC 5 30 31 A CPU registers M5 0xFE 0xFF CBus ABus BBus -
Chapter 1: Microprocessor Architecture
Chapter 1: Microprocessor architecture ECE 3120 – Fall 2013 Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ [email protected] Outline 1.1 Computer hardware organization 1.1.1 Number System 1.1.2 Computer hardware organization 1.2 The processor 1.3 Memory system operation 1.4 Program Execution 1.5 HCS12 Microcontroller 1.1.1 Number System - Computer hardware uses binary numbers to perform all operations. - Human beings are used to decimal number system. Conversion is often needed to convert numbers between the internal (binary) and external (decimal) representations. - Octal and hexadecimal numbers have shorter representations than the binary system. - The binary number system has two digits 0 and 1 - The octal number system uses eight digits 0 and 7 - The hexadecimal number system uses 16 digits: 0, 1, .., 9, A, B, C,.., F 1 - 1 - A prefix is used to indicate the base of a number. - Convert %01000101 to Hexadecimal = $45 because 0100 = 4 and 0101 = 5 - Computer needs to deal with signed and unsigned numbers - Two’s complement method is used to represent negative numbers - A number with its most significant bit set to 1 is negative, otherwise it is positive. 1 - 2 1- Unsigned number %1111 = 1 + 2 + 4 + 8 = 15 %0111 = 1 + 2 + 4 = 7 Unsigned N-bit number can have numbers from 0 to 2N-1 2- Signed number %1111 is a negative number. To convert to decimal, calculate the two’s complement The two’s complement = one’s complement +1 = %0000 + 1 =%0001 = 1 then %1111 = -1 %0111 is a positive number = 1 + 2 + 4 = 7. -
Technician's Guide to 68HC11 Microcontroller.Pdf
chapter 1 Introduction to Computer Hardware Objectives I ntr odu ct ion to Com put er H ardw are After completing this chapter, you should be able to: ◗ Describe the fundamental elements of every computer system: proces- sor, memory, and input/output ◗ Compare elements of the HC11 block diagram to the fundamentals of every computer system ◗ Describe the use of busses to connect computer elements ◗ Explain the three major functional units of a processor ◗ Illustrate the typical registers inside the processor ◗ List the HC11 processor registers ◗ Discuss the HC11 processor modes ◗ Compare and contrast various memory types ◗ Describe the on-chip memory of the HC11 ◗ Specify input/output functions present on most computers ◗ Use some basic BUFFALO commands to control the EVBU Outline ◗ 1.1 Elements of Every Computer ◗ 1.2 Elements of Processors ◗ 1.3 Introduction to Memory ◗ 1.4 Memory Types ◗ 1.5 Input/Output 1 ◗ 1.6 EVBU/BUFFALO Technician’s Guide to the 68HC11 Microcontroller Introduction Computer systems have been developed for a variety of functions and purposes. General-application desktop machines are the most common. They run a variety of software applications, such as word processing, financial management and data processing. They have all but replaced the typewriter as a necessary business tool. Computers are also present in automobiles, appliances, airplanes and all types of controllers and electromechanical devices. Despite the differences among these computer systems, they all share fundamental components and design. The purpose of this chapter is to provide an understanding of the fundamental components of a computer system. A conceptual presentation regarding the elements of every computer system is made with sufficient detail to establish a foundation for these concepts. -
Chapter 5 the LC-3
Instruction Set Architecture ISA = Programmer-visible components & operations • Memory organization Address space -- how may locations can be addressed? Addressibility -- how many bits per location? • Register set Chapter 5 How many? What size? How are they used? • Instruction set The LC-3 Opcodes Data types Addressing modes All information needed to write/gen machine language program Based on slides © McGraw-Hill Additional material © 2004/2005 Lewis/Martin CSE 240 5-2 LC-3 Overview: Memory and Registers LC-3 Overview: Instruction Set Memory Opcodes • Address space: 216 locations (16-bit addresses) • 16 opcodes • Addressibility: 16 bits • Operate instructions: ADD, AND, NOT, (MUL) • Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Registers • Control instructions: BR, JSR, JSRR, RET, RTI, TRAP • Temporary storage, accessed in a single machine cycle • Some opcodes set/clear condition codes, based on result Memory access generally takes longer N = negative (<0), Z = zero (=0), P = positive (> 0) • Eight general-purpose registers: R0 - R7 Data Types Each 16 bits wide • 16-bit 2’s complement integer How many bits to uniquely identify a register? Addressing Modes • Other registers • How is the location of an operand specified? Not directly addressable, but used by (and affected by) • Non-memory addresses: register, immediate (literal) instructions PC (program counter), condition codes, MAR, MDR, etc. • Memory addresses: base+offset, PC-relative, indirect CSE 240 5-3 CSE 240 5-4 1 LC-3 Instruction Summary Operate Instructions (inside back cover) Only three operations • ADD, AND, NOT Source and destination operands are registers • Do not reference memory • ADD and AND can use “immediate” mode, (i.e., one operand is hard-wired into instruction) Will show abstracted datapath with each instruction • Illustrate when and where data moves to accomplish desired op. -
Instruction Set Architecture
Instruction Set Architecture EE3376 1 –Adapted from notes from BYU ECE124 Topics to Cover… l MSP430 ISA l MSP430 Registers, ALU, Memory l Instruction Formats l Addressing Modes l Double Operand Instructions l Single Operand Instructions l Jump Instructions l Emulated Instructions – http://en.wikipedia.org/wiki/TI_MSP430 2 –Adapted from notes from BYU ECE124 Levels of Transformation –Problems –Algorithms – C Instructions –Language (Program) –Programmable –Assembly Language – MSP 430 ISA –Machine (ISA) Architecture –Computer Specific –Microarchitecture –Manufacturer Specific –Circuits –Devices 3 –Adapted from notes from BYU ECE124 Instruction Set Architecture l The computer ISA defines all of the programmer-visible components and operations of the computer – memory organization l address space -- how may locations can be addressed? l addressibility -- how many bits per location? – register set (a place to store a collection of bits) l how many? what size? how are they used? – instruction set l Opcodes (operation selection codes) l data types (data types: byte or word) l addressing modes (coding schemes to access data) l ISA provides all information needed for someone that wants to write a program in machine language (or translate 4 from a high-level language to machine language). –Adapted from notes from BYU ECE124 MSP430 Instruction Set Architecture l MSP430 CPU specifically designed to allow the use of modern programming techniques, such as: – the computation of jump addresses – data processing in tables – use of high-level languages such as C. l 64KB memory space with 16 16-bit registers that reduce fetches to memory. l Implements RISC architecture with 27 instructions and 7 addressing modes.