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UNIT 2 Q.1 Explain Addressing Modes of PIC Microcontroller. the PIC 18 Microcontroller Supports Following Addressing Modes. 1. Immediate Addressing Mode 2

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UNIT 2 Q.1 Explain Addressing Modes of PIC Microcontroller. the PIC 18 Microcontroller Supports Following Addressing Modes. 1. Immediate Addressing Mode 2 UNIT 2 Q.1 Explain addressing modes of PIC microcontroller. The PIC 18 microcontroller supports following addressing modes. 1. Immediate addressing mode 2. Direct addressing mode 3. Register addressing mode 4. Indexed ROM addressing mode 1. Immediate addressing mode: In immediate addressing mode, the immediate data is specified in the instruction. The immediate addressing mode is used to load the data into PIC registers and WREG register. However, it cannot use to load data into any of the file register. Example: 1. MOVLW 50H 2. ANDLW 40H 3. IORLW 60H 2. Direct addressing mode: In direct addressing mode, the 8- bit data in RAM memory location whose address is specified in the instruction. This mode is used for accessing the RAM file register. Example: 1. MOVWF 0X10 2. MOVFF PORTB, POTRC 3. MOVFF 0X30, PORTC 3. Register indirect addressing mode: Register indirect addressing mode is used for accessing data stored in the RAM part of file register. In this addressing mode a register is used as pointer to the memory location of the file register. Three file select registers are used. They are FSR0, FSR1 and FSR2. Example: 1. LFSR1,0X55 2. MOVWF INDF2 4. Indexed ROM addressing mode: This addressing mode is used for accessing the data from look up tables that reside in the PIC18 program ROM. Q.2 Explain following instructions: 1. ADDLW ADD literal to W Syntax: ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (WREG) + k → WREG Status Affected: N, OV, C, DC, Z Description: The contents of WREG are added to the 8-bit literal ’k’ and the result is placed in WREG. Example: ADDLW 0x15 2. ADDWF ADD W to f Syntax: ADDWF f [,d] [,a] Operation: (WREG) + (f) → dest Status Affected: N, OV, C, DC, Z Description: Add WREG to register ’f’. If ’d’ is 0, the result is stored in WREG. If ’d’ is 1, the result is stored back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected. If ’a’ is 1, the Bank will be selected as per the BSR value. Example: ADDWF REG, W 3.ADDWFC ADD WREG and Carry bit to f Syntax: ADDWFC f [ ,d [,a] ] Operation: (WREG) + (f) + (C) → dest Status Affected: N, OV, C, DC, Z Description: Add WREG, the Carry Flag and data memory location ’f’. If ’d’ is 0, the result is placed in WREG. If ’d’ is 1, the result is placed in data memory location 'f'. If ’a’ is 0, the Access Bank will be selected. If ’a’ is 1, the Bank will be selected as per the BSR value. Example: ADDWFC REG, W 4. ANDLW AND literal with WREG Syntax: ANDLW k Operation: (WREG) .AND. k → WREG Status Affected: N, Z Description: The contents of WREG are AND’ed with the 8-bit literal 'k'. The result is placed in WREG. Example: ANDLW 0x5F 5. ANDWF AND WREG with f Syntax: ANDWF f [ ,d [,a] ] Operation: (WREG) .AND. (f) → dest Status Affected: N, Z Description: The contents of WREG are AND’ed with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If ’a’ is 0, the Access Bank will be selected. If ’a’ is 1, the bank will be selected as per the BSR value. Example: ANDWF REG, W 6.BCF Bit Clear f Syntax: BCF f,b Operation: 0 → f Description: Bit 'b' in register 'f' is cleared. Example : BCF FLAG_REG, 7 7. BN Branch if Negative Syntax: BN n Operation: if Negative bit is ‘1’ (PC) + 2 + 2n → PC Description: If the Negative bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Example: BN 7 8. Remaining instructions read from book .
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