14EI606 Hall Ticket Number:

III/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION April, 2018 Electronics & Instrumentation Engineering Sixth Semester Embedded Systems Time: Three Hours Maximum : 60 Marks Answer Question No.1 compulsorily. (1X12 = 12 Marks) Answer ONE question from each unit. (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a) What is function of ALE pin of 8051? b) Discuss the functions of RS0 and RS1 bits in PSW? c) What do you mean the term embedded controllers and external memory devices? d) How RETI and RET instructions differ? e) What is function of SCON register? f) What is importance of Interrupt Enable Register? g) List the different members of Atmel flash microcontrollers? h) How to decide the operating frequency of 89CXX or 89CXXXX microcontrollers? i) What is pin P3.2 of microcontroller 89C51? j) What is the function of watchdog timer? k) List various interrupt sources in PIC 16C71? l) What is the function of status register of PIC16CXX?

UNIT I 2. a) List and explain the functions of all special function registers in 8051? 8M b) Write about ports in 8051. 4M (OR) 3. a) Draw and explain pin diagram of 8051? 8M b) Discuss the criteria for selecting a microcontroller device. 4M

UNIT II 4. a) Define addressing mode? Explain addressing modes supported by 8051 MC, with 8M example for each? b) Summarize 8051 interrupts. 4M (OR) 5. a) Discuss various timer modes supported by 8051. 8M b) Draw the format and explain the flag bits of Interrupt priority register? 4M

UNIT III 6. a) Write a program to generate a triangular waveform with a period of 1ms using 89C51? 6M b) Write a program to generate 2KHZ Square wave on pin1.0 of port 1. 6M (OR) 7. a) Discuss and comment on the program and data memories of 89C51. 6M b) What are the power saving options of 89C51 and explain? 6M

NIT IV 8. a) Discuss the interrupt structure in PIC microcontrollers. List various interrupt sources in 8M PIC16c71. b) List PIC reset action mechanisms and explain. 4M (OR) 9. a) Describe PIC memory Organization. 6M b) Explain the addressing modes of PIC with example? 6M

SCHEM OF EVALUTION: 1. Carries equal marks for all -1M

2. a) List special function registers - 2M Explanation -6M b) Ports explanation -4M

3. a) Pin diagram - 3M Explanation -5M b) Criteria for selecting a microcontroller -4M

4. a)Definition of addressing mode -2M Types -2M Explanation -4M b) Types -2M Explanation -2M

5. a)Mode types -2M Explanation -6M b) Format -1M Explanation -3M

6. a) Program -6M b) program- -6M

7. a)Program memory -3M b) Data memory -3M

8. a) Interrupt structure -4M Sources of interrupts -4M b) reset mechanisms -4M

9. a) Memory organization -2M Explanation -4M b) Types -2M Explanation -4M

BAPATLA ENGINEERING COLLEGE:BAPATLA

III/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION

EI ENGINEERING

EMBEDDED SYSTEMS(14EI606D)

APRIL,2018

SCHEME AND SOLUTION

TOTAL MARKS:60

1.Answer all questions. a)what is function of ALE pin of 8051?

A:ALE is used for latching the low address byte during external memory access.ALE is activated periodically with a constant rate of 1/6 the oscillator frequency. b)Discuss the functions of RS0 and RS1 BITS IN PSW?

A:RS0 and RS1 are used to select register banks like BANK 0,BANK 1 etc. c)What do you mean the term embedded controllers and external memory devices?

A:Embedded controller or devices has all functional block on chip ,including the program and data memory. There is no external data/address bus provided.

Normally devices like 8031 from MCS-51 family need external memory interface.These devices are External Memory devices. d)How RETI and RET differ?

A:RETI and RET both transfer control to the return address stored on stack;the only difference is that in addition to return function,RETI instruction enables interrupts of the current priority level. e)what is the function of SCON register?

A:SCON register controls the serial communication operation.No of data bits and serial mode(data rate) are set by the user in SCON register. f)What is the importance of Interrupt enable register?

A:The interrupt enable register allows the programmer to enable interrupts as needed like serial interrupt,timer interrupts,external interrupts.

g)List the different members of Atmel flash microcontrollers?

A:89CXX and 89C20XX have flash programmable and erasable read only memory. h)How to decide the operating frequency of 89CXX and 89CXXXX microcontrollers?

A:In applications where fast processing is needed without any power constraints, operating frequency must be as high as possible.

In some applications ,the power available for operating the instrument itself is limited. For example ,in battery operated instruments, the power consumption must be as low as possible. i)What is pin P3.2 of microcontroller 89C51?

A:It is port 3 ,bit 2 which can act as input or output port when programmed or as external interrupt 0. j)What is the function of watchdog timer?

A:In case the CPU goes into a hanging situation, it cannot reset the watchdog timer. If it happens so, the watch dog timer resets the CPU and the CPU comes out of the hanging situation. k)List various interrupt sources in PIC 16C71?

A:Ex:external interrupt, timer interrupt, PORTB change interrupt and analog-to-digital conversion interrupt. l)what is the function of status register of PIC16CXX?

A:Carry and Digital carry,zero flag are set according to arithmetic and logical operations and sleep can be selected.Bank 0 or 1 also selected by RP0 in status register.

2a)List and explain the functions of all special function registers in 8051? -8M

A: Special function registers(SFR):

The 128 bytes of on-chip additional RAM locations from 80H to 0FFH are reserved for the special functions and therfore these are called as Special Function Registers(SFRs).

These SFRs are used for control or to show the status of various functions done by 8051 micontroller.All SFRs are directly addressable and can be read or written to as well. some SFRs are addressable and allow their individual bits to be set or cleared by instructions. For example,one can set or clear port1 bit P1.1 using SETB P1.0 OR CLR P1.0.The address of P1.1 bit is 91H.Port 1 has 90H as its byte address, and it is byte addressable too.

PROGRAM STATUS WORD(PSW)

Program status word is an 8-bit register.It consists of carry,auxiliary carry,overflow and parity flags.There are bits RS1 and RS0 for register bank selection.PSW is a bit addressable register.

Data Pointer(DPTR)

DPTR is a 16-bit register consisting of two bytes.The higher byte is referred to as DPH,where as the lower byte is referred to as DPL.The dta pointer is used for addressing the off-chip data and code with MOVX and MOVC commands respectively.

Timer Registers:TH0,TL0;TH1,TL1 form 16-bit timer/counter registers 0,1 respectively.the operation may be timing or counting.there are various modes in which timers can be configured.For this purpose there are timer control (TCON) and timer mode register(TMOD).

Ports 0 to 3:P0,P1,P2,P3 are the SFRs corresponding to four I/O ports respectively.

Control Registers:TCON,TMOD,IE,IP,SCON,PCON contain the control and status for interrupts,serial I/O and timers/counters.

2.b) Write about ports in 8051. -6M(1+1+3+1)

• The 8051 has four I/O ports

– Port 0 （pins 32-39）：P0（P0.0～P0.7）

– Port 1（pins 1-8） ：P1（P1.0～P1.7）

– Port 2（pins 21-28）：P2（P2.0～P2.7）

– Port 3（pins 10-17）：P3（P3.0～P3.7）

– Each port has 8 pins

. • Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X

• Ex：P0.0 is the bit 0（LSB）of P0 • Ex：P0.7 is the bit 7（MSB）of P0

• These 8 bits form a byte. -1M

• Each port can be used as input or output (bi-direction). -1M

• Each pin of I/O ports – Internal CPU bus：communicate with CPU – A D latch store the value of this pin • D latch is controlled by “Write to latch”

• Write to latch＝1：write data into the D latch

– 2 Tri-state buffer：

• TB1: controlled by “Read pin”

• Read pin＝1：really read the data present at the pin

• TB2: controlled by “Read latch”

• Read latch＝1：read value from internal latch

– A transistor M1 gate

• Gate=0: open

• Gate=1: close

• P1, P2, and P3 have internal pull-up resisters. - 3M

– P1, P2, and P3 are not open drain.

• P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. – P0 is open drain.

– Compare the figures of P1.X and P0.X.

• However, for a programmer, it is the same to program P0, P1, P2 and P3.

• All the ports upon RESET are configured as output.

- 1M

OR

3.a.Draw and explain pin diagram of 8051? 8M

The pin diagram of 8051 microcontroller looks as follows −

A: Pins 1 to 8 − These pins are known as Port 1. This port doesn‟t serve any other functions. It is internally pulled up, bi-directional I/O port. Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values. Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals, serial communication signals RxD and TxD, etc. Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock. Pin 20 − This pin provides the power supply to the circuit. Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus signals are also multiplexed using this port. Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory. Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing. Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port. Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed using this port. Pin 40 − This pin is used to provide power supply to the circuit.

3.b.Discuss the criteria for selecting a microcontroller device? -4M

A:The selection criteria among several microcontrollers are only based on the functional requirements power supply constraints, available printed board space, pin count and the cost of production.

1.For a mass production, the designer may go for ROM versions.

2.However for lesser production, EPROM version or CPU version with external program memory is suitable. It is preferred to go for the EPROM/ROM versions to avoid the external memory connections, provided the size of the code is less than the size of on-chip program memory. EPROM has limited write/erase cycles, typically 1000 write/erase.

3.From maintenance point of view one may prefer EPROM or ROM version, because it requires replacing only a single IC from the board.

4.For the development work, an eprom eraser and programmer is needed to write or change the code, along with the testing and debugging tools.

4.a.Define addressing mode?Explain addressing modes supported by 8051 MC,with example for each?-8M

A:Addressing modes define the way in which th e operands are accessed by the instruction.

-1M

The addressing modes are as follows, with an example of each: 1. Immediate Addressing -1M a. MOV A,#20h 2. Register Addressing a. MOV A,R0 3. Direct Addressing MOV A,30h 4. Indirect Addressing MOV A,@R0 5. External Direct MOVX A,@DPTR 6. Code Indirect MOVC A,@A+DPTR

Each of these addressing modes provides important flexibility . Immediate Addressing Immediate addressing is so-named because the value to be stored in memory immediately follows the operation code in memory. For example, the instruction: MOV A,#20h Immediate addressing is very fast since the value to be loaded is included in the instruction.

Register Addressing: contents of one register can copied to other register. EX: MOV A,R0;RO contents are copied to A

Direct Addressing Direct addressing is so-named because the value to be stored in memory is obtained by directly retrieving it from another memory location. For example: MOV A,30h This instruction will read the data out of Internal RAM address 30 (hexidecimal) and store it in the Accumulator. Direct addressing is generally fast since, although the value to be loaded isnt included in the instruction, it is quickly accessable since it is stored in the 8051s Internal RAM Also, it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself. Indirect Addressing: Indirect addressing is also the only way to access the extra 128 bytes of InternalRAM found on an 8052. Indirect addressing appears as follows: MOV A,@R0 The 8051 will load the accumulator with the value from Internal RAM which is found at the address indicated by R0. For example, lets say R0 holds the value 40h and Internal RAM address 40h holds the value 67h. When the above instruction is executed the 8051 will check the value of R0. Since R0 holds 40h the 8051 will get the value out of Internal RAM address 40h (which holds 67h) and store it in the Accumulator. Thus, the Accumulator up holding 67h.

External Direct: There are only two commands that use External Direct addressing mode: MOVX A,@DPTR MOVX @DPTR,A Both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address of external memory that you wish to read or write. Once DPTR holds the correct external memory address, the first command will move the contents of that external memory address into the Accumulator. The second command will do the opposite: it will allow us to write the value of the Accumulator to the external memory address pointed to by DPTR.

External Indirect: This form of addressing is usually only used in relatively small projects that have a very small amount of external RAM. An example of this addressing mode is: MOVX @R0,A Once again, the value of R0 is first read and the value of the Accumulator is written to that address in External RAM. Since the value of @R0 can only be 00h through FFh the project would effectively be limited to 256 bytes of External RAM.

4.b.Summarize 8051 interrupts. 4M

Interrupts are the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off. 8051 has 5 interrupt signals, i.e. INT0, TFO, INTR1, TF1, RI/TI. Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register.

IE (Interrupt Enable) Register:

This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure.

EA -IE.7 It enable/disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually. - IE.6 Reserved for future use. - IE.5 Reserved for future use. ES - IE.4 Enables/disables serial port interrupt. ET1 - IE.3 Enables/disables timer1 overflow interrupt. EX1 - IE.2 Enables/disables external interrupt1. ET0 -IE.1 Enables/disables timer0 overflow interrupt. EX0 - IE.0 Enables/disables external interrupt0.

OR

5.a.Discuss various timer modes supported by 8051. 8M

A:Table -1M,Description-4M,figures-3m

Mode0- Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13- bit counter can hold values between 0000 to 1FFFH in TH-TL. Therefore, when the timer reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised.

Mode 1 - 16-bit mode The high byte (THx) is cascaded with the low byte (TLx) to produce a 16-bit timer. This timer counts from 0000H to FFFFH - it has 216 (65,536) states. An overflow occurs during the FFFFH to 0000H transition, setting the overflow flag . Mode 2- 8-bit auto-reload mode The timer low byte (TLx) operates as an 8-bit timer (counting to FFH) while the high byte holds a reload value. When the timer overflows from FFH, rather than starting again from 00H, the value in THx is loaded into TLx and the count continues from there. Mode3- Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3; timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer 0.

5.b.Draw the format and explain the flag bits of Interrupt priority register? 4M

A:Figures-1m+1m+description 2m

IP (Interrupt Priority) Register: We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure.

Fig.5.b. IP (Interrupt Priority) Register

A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt. Ex:When CPU is servicing PT0,it may not be interrupted PX0. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. Ex:If PS and PT1 comes at a time,PS will be serviced first. If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced.

6.a.Write a program to generate a triangular waveform with a period of 1ms using 89c51? 6M

A:program -3M

CALCULATIONS-2m circuit -1M Let P0 as output port

Assume triangular waveform starts at 0v and ends at

START:MOV A,#55

LOOP1:MOV P0,A

INC A

INC A

JNZ LOOP1

MOV A,#200

LOOP2: MOV P0,A

DEC A

DEC A

JNZ LOOP2

LJMP START

Triangular waveform is generated by connecting DAC at P0 port.

T1-INCREASING RAMP=0.5ms

T2-DECREASING RAMP=0.5ms no of iterations 200 and loop iteration time is 5 usec assuming clock frequency as 12MHZ.

SO T1=100x5us=500us=0.5ms it starts with a count of 55 and ends at 255. similarly T2 starts at 200 and decremented twice at a time and loop is repeated 100 times and soT2=100x5us=500us=0.5ms and the voltage range as 0 to 5v depending DAC specifications. 6.b.Generate a square wave on pin 1.0 of port 1 using program? 6M a: Program 3M+explanation 3M

Program to generate a 2Khz square waaves on pin 1.0 of port 1 Oscillator frequency =12MHz.

Square waves can be generated on any of the port pins of 89CXX.

In this program, timer 0 is used in mode2.Mode 2 is auto-reload mode in which the timer TH0 preserves the preload value. After each overflow of TL0,it is loaded with TH0.Timer TL0 is controlled by TR0 bit in TCON.TH0 is initialized with 06h by the program and later at each TL0 overflow by the mode 2 itself.

For 2Khz frequency, the ON time (equal to 0FF time) of 0.25ms is required. It means that at 12Mhz,the number of timer clocks required will be 250.

If the 8-bit timer TL0 is loaded with 06H and overflows from FFH to 00H,pin 1.0 status is complemented to get the square waves.

MOV SP,#54H ;Initialize the stack pointer MOV TMOD ,0000 0010 ;Timer 0 in mode 2 (auto-reload mode) MOV TH0,#06H ;preload value for 2khz square waves MOV TL0,#06H ;starting value in timer register TL0 SETB TR0 ;start timer 0 JB TF0,COMPLMNT LOOP: SJMP LOOP COMPLMNT :CPL P1.0 ;Toggle bit P1.0 SJMP LOOP

7.a.Discuss and comment on the program and data memories of 89c51. 6M a: Memory Organization Program Memory The AT89C Microcontroller has separate address spaces for program memory and data memory. The program memory can be up to 64K bytes long. The lower addresses may reside on-chip.

Figure 1 shows a map of the AT89C51 program memory

Data Memory The AT89C can directly address up to 64K bytes of data memory external to the chip. The MOVX instruction accesses the external data memory. The AT89C51 has 128 bytes of on-chip RAM (256 bytes in the AT89C52) plus a number of Special Function Registers (SFRs). The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing (MOV @Ri).

Figure 2: The AT89C51 Data Memory

Indirect Address Area In Figure 3b, the SFRs and the indirect address RAM have the same addresses (80H through 0FFH). Nevertheless, they are two separate areas and are accessed in two different ways. For example, the following instruction writes 0AAH to Port 0, which is one of the SFRs. MOV 80H, # 0AAH The following instruction writes 0BBH in location 80H of the data RAM. MOVR0, # 80H MOV@ R0, # 0BBH Thus, after executing both of these instructions, Port 0 contains 0AAH, and location 80H of the RAM contains 0BBH. The stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space in devices that implement 256 bytes of internal RAM. Direct and Indirect Address Area The 128 bytes of RAM that can be accessed by both direct and indirect addressing can be divided into 3 segments as described in this section and as shown in Figure 3.

Figure 3. 128 Bytes of Directly and Indirectly Addressable RAM

1. Register Banks 0-3: Locations 0 through 1FH (32 bytes). Reset default is to register bank 0. To use the other register banks, the user must select them in the software. Each register bank contains eight 1-byte registers, 0 through 7. Reset initializes the Stack Pointer to location 07H. The Stack Pointer is then incremented once to start from location 08H, which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location of the RAM that is not used for data storage (that is, a higher part of the RAM). 2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H through 2FH. Each of the 128 bits of this segment can be directly addressed (0 through 7FH). These bits can be referred to in two ways. One way is to refer to their addresses, that is, 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0 through 7 can also be referred to as bits 20.0 through 20.7, and bits 8 through FH are the same as 21.0 through 21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if the stack pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.

7.B.What are the power saving options of 89C51 and explain? .-6m(2X3=6m)

A: 8951/89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Idle Mode 3M In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode 3M In the power-down mode, the oscillator is stopped, and the instruction that invokes power- down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

8.a.Discuss the interrupt structure in PIC microcontrollers. List various interrupt sources in PIC 16C71.-8m

The PIC16C7X family has up to 6 sources of interrupt:

Interrupt Sources Applicable Devices

• External interrupt RB0/INT • TMR0 overflow interrupt • PORTB change interrupts (pins RB7:RB4) • A/D Interrupt • TMR1 overflow interrupt • serial port interrupt -2M

The interrupt control register (INTCON) records individual interrupt requests in flag bits.

-1M

Description-3M

It also has individual and global interrupt enable bits A global interrupt enable bit, GIE (INTCON) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.

When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately.

Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit.

The GIE bit is cleared on reset. The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.

The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re- enabling interrupts to avoid recursive interrupts.

8.b.List PIC reset action mechanisms and explain. 4M(2M+2M)

Fig a :A simple PIC Reset circuit Fig b. PIC Reset circuit

PIC reset action takes place due to different mechanisms. Those are 1.Power on reset(POR),/MCLR reset during normal operation. Master clear /MCLR reset during sleep mode, Watch dog timer during normal operation , 2.Brown-out-reset(BOR).

1.Power on reset(POR): PIC reset function is very simple./MCLR is the master clear pin, which when made low causes PIC to reset. A power-on-reset pulse is generated when VDD rise is detected. The range of VDD through which it should rise is from 1.5 to 2.1v. A very simple circuit can be a pull-up resistor through which /MCLR is tied to VDD. This is shown in fig a. A power-up timer operating on the internal PC oscillator generates 72ms fixed delay on power-up. This time delay allows VDD to rise to the required level .Power-up timer may be enabled or disabled by writing a configuration bit. In case of XT,LP,HS oscillator modes immediately after the power-up delay, the oscillator start-up timers starts. The reset function will set the program counter to the starting address of the program.

Normally an RC circuit is not necessarily needed, but it is recommended by Microchip to have a reset circuit using external RC components as shown in fig b. This circuit is required only if VDD power-up slope is not sufficient. The value of R must be 40kohms to make ensure that the voltage drop across R does not exceed the electrical spefications.1k resister again limits the current in to /MCLR pin. 2.The Brown-out reset: The Brown-out reset occurs when the supply voltage falls below 4 volts. The device remains in the Brown-out reset state till the supply voltage is restored. The Brown-out reset also includes another feature .If VDD is hit with a transient noise spike ,causing Vdd to drop below 4.0Volts for longer than 100 micro seconds ,the Brown-out reset circuit detects that and reset the chip. where as in most of the other microcontrollers many erroneous executions takes place during this time. The PIC brown-out reset will also help if the power-on reset conditions are not met. There is a provision of power-up timer of about 72ms.Once this is enabled the Brown-out reset occurs once again in case of non-restoration of supply within 72 ms.

9.A.Describe PIC memory organization. 6M a: CPU Architecture: The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates instruction fetch and the operation on data/accessing of variables simultaneously.

Fig CPU Architecture of PIC microcontroller

PIC Memory Organisation: PIC microcontroller has 13 bits of program memory address. Hence it can address up to 8k of program memory. The program counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or 4k. While addressing 2k of program memory, only 11- bits are required. Hence two most significant bits of the program counter are ignored. Similarly, while addressing 4k of memory, 12 bits are required. Hence the MSb of the program counter is ignored.

Fig 9.A.1 Program Memory map The program memory map of PIC16C74A is shown in Fig 9.a.1. On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes the processor to the mainline program.When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the interrupt service routine (ISR) is written at 004H. Data memory (Register Files): Data Memory is also known as Register File. Register File consists of two components. 1. General purpose register file (same as RAM). 2. Special purpose register file (similar to SFR in 8051).

Fig 9.A.2 Data Memory map The special purpose register file consists of input/output ports and control registers. Addressing from 00H to FFH requires 8 bits of address. However, the instructions that use direct addressing modes in PIC to address these register files use 7 bits of instruction only. Therefore the register bank select (RP0) bit in the STATUS register is used to select one of the register banks. In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the data memory.

9.B.Explain the addressing modes of PIC with example?

1.Immediate addressing mode: -2M

In this addressing mode, the operand is a number or constant not an address as MOVLW 43h, the operand here is data not address. So in this addressing mode of pic microcontroller data is direct transfer and data is immediate after opcode that is why this type of addressing is called immediate addressing. This way is fast in execution.

2. Register operand addressing mode: -2M

In this addressing mode, the operand is a Register which holds the data to be execute. Register operand addressing mode deals with the registers like: CLR W 3.Memory operand addressing mode : 4M In this addressing mode, the operand is an address of Memory location which holds the data to be execute. Again memory operand addressing mode is fallen under two category 1) Direct addressing like CLRF 13h. We deal with the address or the memory location. 2) Indirect addressing which we use in it INDF and FSR registers.

3.a.Direct addressing: Direct Addressing is done through a 9-bit address. This address is obtained by connecting 7th bit ofdirect address of an instruction with two bits (RP1, RP0) from STATUS register as is shown on below Figure9.b. Any access to SFR registers can be an example of direct addressing.

3.b.Indirect addressing: 4M It does not take an address from an instruction, but it derives it from IRP bit of STATUS and FSR registers. Addressed location is accessed through INDF register which in fact holds the address indicated by the FSR. Indirect addressing is very convenient for manipulating data arrays located in GPR registers. In this case, it is necessary to initialize FSR register with a starting address of the array, and the rest of the data can be accessed by incrementing the FSR register. Figure9-bshows the indirect addressing concept.