ARM® Developer Suite Version 1.1

Total Page:16

File Type:pdf, Size:1020Kb

ARM® Developer Suite Version 1.1 ARM® Developer Suite Version 1.1 Assembler Guide Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A ARM Developer Suite Assembler Guide Copyright © 2000 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Change November 2000 A Release 1.1 Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. ii Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A Contents Assembler Guide Preface About this book .............................................................................................. vi Feedback ....................................................................................................... ix Chapter 1 Introduction 1.1 About the ARM Developer Suite assemblers .............................................. 1-2 Chapter 2 Writing ARM and Thumb Assembly Language 2.1 Introduction ................................................................................................. 2-2 2.2 Overview of the ARM architecture .............................................................. 2-3 2.3 Structure of assembly language modules ................................................. 2-12 2.4 Conditional execution ................................................................................ 2-19 2.5 Loading constants into registers ............................................................... 2-24 2.6 Loading addresses into registers .............................................................. 2-29 2.7 Load and store multiple register instructions ............................................. 2-38 2.8 Using macros ............................................................................................ 2-47 2.9 Describing data structures with MAP and FIELD directives ...................... 2-50 2.10 Using frame directives ............................................................................... 2-65 Chapter 3 Assembler Reference 3.1 Command syntax ........................................................................................ 3-2 3.2 Format of source lines ................................................................................ 3-8 ARM DUI 0068A Copyright © 2000 ARM Limited. All rights reserved. iii Confidential Draft Contents 3.3 Predefined register and coprocessor names .............................................. 3-9 3.4 Built-in variables ....................................................................................... 3-10 3.5 Symbols .................................................................................................... 3-12 3.6 Expressions, literals, and operators ......................................................... 3-18 Chapter 4 ARM Instruction Reference 4.1 Conditional execution ................................................................................. 4-4 4.2 ARM memory access instructions .............................................................. 4-6 4.3 ARM general data processing instructions ............................................... 4-23 4.4 ARM multiply instructions ......................................................................... 4-39 4.5 ARM saturating arithmetic instructions ..................................................... 4-54 4.6 ARM branch instructions .......................................................................... 4-56 4.7 ARM coprocessor instructions .................................................................. 4-61 4.8 Miscellaneous ARM instructions ............................................................... 4-70 4.9 ARM pseudo-instructions ......................................................................... 4-76 Chapter 5 Thumb Instruction Reference 5.1 Thumb memory access instructions ........................................................... 5-4 5.2 Thumb arithmetic instructions ................................................................... 5-15 5.3 Thumb general data processing instructions ............................................ 5-22 5.4 Thumb branch instructions ....................................................................... 5-31 5.5 Thumb software interrupt and breakpoint instructions .............................. 5-37 5.6 Thumb pseudo-instructions ...................................................................... 5-39 Chapter 6 Vector Floating-point Programming 6.1 The vector floating-point coprocessor ........................................................ 6-4 6.2 Floating-point registers ............................................................................... 6-5 6.3 Vector and scalar operations ...................................................................... 6-7 6.4 VFP and condition codes ............................................................................ 6-8 6.5 VFP system registers ............................................................................... 6-10 6.6 Flush-to-zero mode .................................................................................. 6-13 6.7 VFP instructions ....................................................................................... 6-15 6.8 VFP pseudo-instruction ............................................................................ 6-34 6.9 VFP directives and vector notation ........................................................... 6-35 Chapter 7 Directives Reference 7.1 Alphabetical list of directives ...................................................................... 7-2 7.2 Symbol definition directives ........................................................................ 7-3 7.3 Data definition directives .......................................................................... 7-12 7.4 Assembly control directives ...................................................................... 7-25 7.5 Frame description directives ..................................................................... 7-31 7.6 Reporting directives .................................................................................. 7-42 7.7 Miscellaneous directives ........................................................................... 7-47 Glossary iv Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A Confidential Draft Preface This preface introduces the documentation for the ARM Developer Suite (ADS) assemblers and assembly language. It contains the following sections: • About this book on page vi • Feedback on page ix. ARM DUI 0068A Copyright © 2000 ARM Limited. All rights reserved. v Preface About this book This book provides tutorial and reference information for the ADS assemblers (armasm, the free-standing assembler, and inline assemblers in the C and C++ compilers). It describes the command-line options to the assembler, the pseudo-instructions and directives available to assembly language programmers, and the ARM, Thumb®,and Vector Floating-point (VFP) instruction sets. Intended audience This book is written for all developers who are producing applications using ADS. It assumes that you are an experienced software developer and that you are familiar with the ARM development tools as described in ADS Getting Started. Using this book This book is organized into the following chapters: Chapter 1 Introduction Read this chapter for an introduction to the ADS version 1.1 assemblers and assembly language. Chapter 2 Writing ARM and Thumb Assembly Language Read this chapter for tutorial information to help you use the ARM assemblers and assembly language. Chapter 3 Assembler Reference Read this chapter for reference material about the syntax and structure of the language provided by the ARM assemblers. Chapter 4 ARM Instruction Reference Read this chapter for reference material on the ARM instruction set. Chapter 5 Thumb Instruction Reference Read this chapter for reference material on the Thumb instruction set. Chapter 6 Vector Floating-point Programming Read this chapter for reference material on the VFP instruction set, and other VFP-specific assembly language information. Chapter 7 Directives Reference Read this chapter for reference material on the assembler directives available in the ARM assembler, armasm. vi Copyright © 2000 ARM Limited. All rights reserved. ARM DUI 0068A Preface Typographical conventions The following typographical conventions are used in this book: typewriter Denotes text that can be entered at the keyboard, such as commands, file and program names, and source code. typewriter Denotes a permitted abbreviation for a command or option. The underlined text can be
Recommended publications
  • ARM Compiler Armasm User Guide
    ARM® Compiler Version 6.01 armasm User Guide Copyright © 2014 ARM. All rights reserved. ARM DUI 0801B (ID121814) ARM Compiler armasm User Guide Copyright © 2014 ARM. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change 14 March 2014 A Non-Confidential ARM Compiler v6.00 Release 15 December 2014 B Non-Confidential ARM Compiler v6.01 Release Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
    [Show full text]
  • Addressing Mode 1 Addressing Mode
    Addressing mode 1 Addressing mode Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. In computer programming, addressing modes are primarily of interest to compiler writers and to those who write code directly in assembly language. Caveats Note that there is no generally accepted way of naming the various addressing modes. In particular, different authors and computer manufacturers may give different names to the same addressing mode, or the same names to different addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single addressing mode may represent functionality that, in another architecture, is covered by two or more addressing modes. For example, some complex instruction set computer (CISC) computer architectures, such as the Digital Equipment Corporation (DEC) VAX, treat registers and literal/immediate constants as just another addressing mode. Others, such as the IBM System/390 and most reduced instruction set computer (RISC) designs, encode this information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one register to another, copying a literal constant into a register, and copying the contents of a memory location into a register, while the VAX has only a single "MOV" instruction.
    [Show full text]
  • Armv7-M Architecture Reference Manual
    ARM®v7-M Architecture Reference Manual Copyright © 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 (ID021910) ARMv7-M Architecture Reference Manual Copyright © 2006-2010 ARM Limited. All rights reserved. Release Information The following changes have been made to this document. Change history Date Issue Confidentiality Change June 2006 A Non-confidential Initial release July 2007 B Non-confidential Second release, errata and changes documented separately September 2008 C Non-confidential, Restricted Access Options for additional watchpoint based trace in the DWT, plus errata updates and clarifications. July 2009 C_errata Non-confidential Marked-up errata PDF, see page iii for more information. February 2010 C_errata_v3 Non-confidential Additional marked-up errata PDF, see page iii for more information. Proprietary Notice This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture Reference Manual. Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations
    [Show full text]
  • ARM Compiler Toolchain Using the Assembler
    ARM® Compiler toolchain Version 4.1 Using the Assembler Copyright © 2010-2011 ARM. All rights reserved. ARM DUI 0473C (ID080411) ARM Compiler toolchain Using the Assembler Copyright © 2010-2011 ARM. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change May 2010 A Non-Confidential ARM Compiler toolchain v4.1 Release 30 September 2010 B Non-Confidential Update 1 for ARM Compiler toolchain v4.1 28 January 2011 C Non-Confidential Update 2 for ARM Compiler toolchain v4.1 Patch 3 30 April 2011 C Non-Confidential Update 3 for ARM Compiler toolchain v4.1 Patch 4 30 September 2011 C Non-Confidential Update 4 for ARM Compiler toolchain v4.1 Patch 5 Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product.
    [Show full text]
  • X86 Assembly Language
    Introduction to Compilers and Language Design Copyright © 2020 Douglas Thain. Paperback ISBN: 979-8-655-18026-0 Second edition. Anyone is free to download and print the PDF edition of this book for per- sonal use. Commercial distribution, printing, or reproduction without the author’s consent is expressly prohibited. All other rights are reserved. You can find the latest version of the PDF edition, and purchase inexpen- sive hardcover copies at http://compilerbook.org Revision Date: January 15, 2021 149 Chapter 10 – Assembly Language 10.1 Introduction In order to build a compiler, you must have a working knowledge of at least one kind of assembly language. And, it helps to see two or more variations of assembly, so as to fully appreciate the distinctions between architectures. Some of these differences, such as register structure, are quite fundamental, while some of the differences are merely superficial. We have observed that many students seem to think that assembly lan- guage is rather obscure and complicated. Well, it is true that the complete manual for a CPU is extraordinarily thick, and may document hundreds of instructions and obscure addressing modes. However, it’s been our ex- perience that it is really only necessary to learn a small subset of a given assembly language (perhaps 30 instructions) in order to write a functional compiler. Many of the additional instructions and features exist to handle special cases for operating systems, floating point math, and multi-media computing. You can do almost everything needed with the basic subset. We will look at two different CPU architectures that are in wide use to- day: X86 and ARM.
    [Show full text]
  • TASKING VX-Toolset for ARM User Guide
    TASKING VX-toolset for ARM User Guide MA101-800 (v4.4) April 15, 2013 Copyright © 2013 Altium Limited. All rights reserved.You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, TASKING, and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. Table of Contents 1. C Language .................................................................................................................. 1 1.1. Data Types ......................................................................................................... 1 1.2. Changing the Alignment: __unaligned, __packed__ and __align() ................................. 2 1.3. Placing an Object at an Absolute Address: __at() ......................................................
    [Show full text]
  • ARM Compiler Toolchain V5.02 for Μvision Using the Assembler
    ARM® Compiler toolchain v5.02 for µVision Using the Assembler Copyright © 2007-2008, 2011-2012 ARM. All rights reserved. ARM DUI 0379D (ID062912) ARM Compiler toolchain v5.02 for µVision Using the Assembler Copyright © 2007-2008, 2011-2012 ARM. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change May 2007 A Non-Confidential Release for RVCT v3.1 for µVision December 2008 B Non-Confidential Release for RVCT v4.0 for µVision June 2011 C Non-Confidential Release for ARM Compiler toolchain v4.1 for µVision July 2012 D Non-Confidential Release for ARM Compiler toolchain v5.02 for µVision Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product.
    [Show full text]
  • A Syntax Directed Imperative Language Microprocessor for Reduced Power Consumption and Improved Performance
    A Syntax Directed Imperative Language Microprocessor for Reduced Power Consumption and Improved Performance Glenn Coates PhD University of York Computer Science August 2018 Abstract This thesis investigates high-level Instruction Set Architectures (ISAs) and supporting processor architectures. A Syntax Directed Imperative Language Processor (SDLP) and associated ISA have been defined with the ultimate aim of reducing power consumption and improving performance. The findings of this thesis suggest that there may be a number of benefits of the SDLP over traditional ISAs and architectures. Initial results suggest that the SDLP ISA places less burden on the memory system by reducing the number of instructions executed for a given program. It also appears that the SDLP could reduce the number of interactions with the memory system for data. These results are significant since a large portion of the total power for a system is consumed by the memory system. It is illustrated how the SDLP requires fewer cycle counts for the equivalent throughput of traditional microprocessor architectures. The implication is that further perfor- mance improvements could be obtained with uniprocessors, before considering multiprocessors. The main contributions of this thesis include: • The design of a hybrid control flow and data flow architecture with a supporting Instruction Set Architecture; • Implementation of an assembler and software-based cycle accurate simulator for the SDLP processor; • Comparisons of the SDLP architecture with traditional CISC and RISC processors; • It has been shown that high-level ISAs and supporting processor architectures can reduce the burden on the memory system for both instructions and data; and can reduce the cycle count of programs.
    [Show full text]