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ARM Compiler Armasm User Guide ARM® Compiler Version 6.01 armasm User Guide Copyright © 2014 ARM. All rights reserved. ARM DUI 0801B (ID121814) ARM Compiler armasm User Guide Copyright © 2014 ARM. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change 14 March 2014 A Non-Confidential ARM Compiler v6.00 Release 15 December 2014 B Non-Confidential ARM Compiler v6.01 Release Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DUI 0801B Copyright © 2014 ARM. All rights reserved. ii ID121814 Non-Confidential Contents ARM Compiler armasm User Guide Chapter 1 Conventions and Feedback Chapter 2 Overview of armasm 2.1 About the ARM Compiler toolchain assemblers ...................................................... 2-2 2.2 Key features of the assembler ................................................................................ 2-3 2.3 How the assembler works ........................................................................................ 2-4 2.4 Directives that can be omitted in pass 2 of the assembler ...................................... 2-6 Chapter 3 Overview of the ARM Architecture 3.1 About the ARM architecture ..................................................................................... 3-2 3.2 A64, A32, and T32 instruction sets .......................................................................... 3-3 3.3 Changing between AArch64 and AArch32 states .................................................... 3-4 3.4 Advanced SIMD ....................................................................................................... 3-5 3.5 Floating-point hardware ........................................................................................... 3-6 Chapter 4 Overview of AArch32 state 4.1 Changing between A32 and T32 instruction set states ........................................... 4-2 4.2 Processor modes, and privileged and unprivileged software execution .................. 4-3 4.3 Registers in AArch32 state ...................................................................................... 4-4 4.4 General-purpose registers in AArch32 state ............................................................ 4-6 4.5 Register accesses in AArch32 state ........................................................................ 4-7 4.6 Predeclared core register names in AArch32 state ................................................. 4-8 4.7 Predeclared extension register names in AArch32 state ......................................... 4-9 4.8 Program Counter in AArch32 state ........................................................................ 4-10 4.9 Application Program Status Register ..................................................................... 4-11 4.10 The Q flag in AArch32 state ................................................................................... 4-12 4.11 Current Program Status Register in AArch32 ........................................................ 4-13 4.12 Saved Program Status Registers (SPSRs) in AArch32 state ................................ 4-14 4.13 A32 instruction set overview .................................................................................. 4-15 ARM DUI 0801B Copyright © 2014 ARM. All rights reserved. iii ID121814 Non-Confidential Contents 4.14 Media processing instructions ............................................................................... 4-17 4.15 Access to the inline barrel shifter in AArch32 state ............................................... 4-18 Chapter 5 Overview of AArch64 state 5.1 Registers in AArch64 state ...................................................................................... 5-2 5.2 Exception levels ....................................................................................................... 5-3 5.3 Link registers ........................................................................................................... 5-4 5.4 Stack Pointer register .............................................................................................. 5-5 5.5 Predeclared core register names in AArch64 state ................................................. 5-6 5.6 Predeclared extension register names in AArch64 state ......................................... 5-7 5.7 Program Counter in AArch64 state .......................................................................... 5-8 5.8 Conditional execution in AArch64 state ................................................................... 5-9 5.9 The Q flag in AArch64 state ................................................................................... 5-10 5.10 Process State ........................................................................................................ 5-11 5.11 Saved Program Status Registers (SPSRs) in AArch64 state ................................ 5-12 5.12 A64 instruction set overview .................................................................................. 5-13 Chapter 6 Structure of Assembly Language Modules 6.1 Syntax of source lines in assembly language .......................................................... 6-2 6.2 Literals ..................................................................................................................... 6-4 6.3 ELF sections and the AREA directive ...................................................................... 6-5 6.4 An example assembly language module ................................................................. 6-6 Chapter 7 Writing A32/T32 Assembly Language 7.1 Unified Assembler Language ................................................................................... 7-3 7.2 Syntax differences between UAL and A64 assembly language .............................. 7-4 7.3 Subroutine calls ....................................................................................................... 7-5 7.4 Load immediates into registers ................................................................................ 7-6 7.5 Load immediate values using MOV and MVN ......................................................... 7-7 7.6 Load 32-bit values to a register using MOV32 ....................................................... 7-10 7.7 Load immediate 32-bit values to a register using LDR Rd, =const ........................ 7-11 7.8 Literal pools ........................................................................................................... 7-12 7.9 Load addresses into registers ................................................................................ 7-14 7.10 Load addresses to a register using ADR ............................................................... 7-15 7.11 Load addresses to a register using ADRL ............................................................. 7-17 7.12 Load addresses to a register using LDR Rd, =label .............................................. 7-18 7.13 Other ways to load and store registers .................................................................. 7-20 7.14 Load and store multiple register instructions ......................................................... 7-21 7.15 A32 and T32 load and store multiple instructions .................................................. 7-22 7.16 Stack implementation using LDM and STM ........................................................... 7-23 7.17 Stack operations for nested subroutines ............................................................... 7-25 7.18 Block copy with LDM and STM .............................................................................. 7-26 7.19 Memory accesses .................................................................................................. 7-28 7.20 Read-Modify-Write procedure ................................................................................ 7-29 7.21 Optional hash ......................................................................................................... 7-30 7.22 Use of macros .......................................................................................................
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