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Armv7-M Architecture Reference Manual ARM®v7-M Architecture Reference Manual Copyright © 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 (ID021910) ARMv7-M Architecture Reference Manual Copyright © 2006-2010 ARM Limited. All rights reserved. Release Information The following changes have been made to this document. Change history Date Issue Confidentiality Change June 2006 A Non-confidential Initial release July 2007 B Non-confidential Second release, errata and changes documented separately September 2008 C Non-confidential, Restricted Access Options for additional watchpoint based trace in the DWT, plus errata updates and clarifications. July 2009 C_errata Non-confidential Marked-up errata PDF, see page iii for more information. February 2010 C_errata_v3 Non-confidential Additional marked-up errata PDF, see page iii for more information. Proprietary Notice This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture Reference Manual. Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture infringe any third party patents. This ARM Architecture Reference Manual is provided “as is”. ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or that any practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third party patents, copyrights, trade secrets, or other rights. This ARM Architecture Reference Manual may include technical inaccuracies or typographical errors. To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this ARM Architecture Reference Manual, even if ARM has been advised of the possibility of such damages. Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Copyright © 2006-2010 ARM Limited 110 Fulbourn Road Cambridge, England CB1 9NJ ii Copyright © 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 Non-Confidential, Unrestricted Access ID021910 Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out above. In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as appropriate”. Note The term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way. Note • This errata PDF is regenerated from the source files of issue C of this document, but: — Some pseudocode examples, that are imported into the document, have been updated. Markups highlight significant changes in these pseudocode inserts. Other pseudocode updates are made using the standard Acrobat editing tools. — Pages ii and iii of the PDF have been replaced, by an edit to the PDF, to include an updated Proprietary Notice. With these exceptions, this PDF corresponds to the released PDF of issue C of the document, with errata indicated by markups to the PDF: — the original errata markups, issued June 2009, are identified as ARM_2009_Q2 — additional errata markups, issued February 2010, are identified as ARM_2009_Q4. • In the revised pseudocode, the function BadReg(x) is replaced by a new construct, x IN {13,15}, that can be used in other contexts. This is a format change only. • From February 2010, issue C of the ARMv7-M ARM is superseded by issue D of the document. ARM strongly recommends you to use issue D of the document in preference to using this errata PDF. ARM DDI 0403C_errata_v3 Copyright © 2006-2010 ARM Limited. All rights reserved. iii ID021910 Non-Confidential, Unrestricted Access iv Copyright © 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 Non-Confidential, Unrestricted Access ID021910 Contents ARMv7-M Architecture Reference Manual Preface About this manual .............................................................................. xviii Using this manual ............................................................................... xix Conventions ....................................................................................... xxii Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv Part A Application Level Architecture Chapter A1 Introduction A1.1 The ARM Architecture – M profile .................................................... A1-2 Chapter A2 Application Level Programmers’ Model A2.1 About the Application level programmers’ model ............................. A2-2 A2.2 ARM core data types and arithmetic ................................................ A2-3 A2.3 Registers and execution state ........................................................ A2-11 A2.4 Exceptions, faults and interrupts .................................................... A2-15 A2.5 Coprocessor support ...................................................................... A2-16 Chapter A3 ARM Architecture Memory Model A3.1 Address space ................................................................................. A3-2 ARM DDI 0403C Copyright © 2006-2008 ARM Limited. All rights reserved. v Restricted Access Non-Confidential Contents A3.2 Alignment support ............................................................................ A3-3 A3.3 Endian support ................................................................................. A3-5 A3.4 Synchronization and semaphores .................................................... A3-8 A3.5 Memory types and attributes and the memory order model .......... A3-18 A3.6 Access rights .................................................................................. A3-28 A3.7 Memory access order .................................................................... A3-30 A3.8 Caches and memory hierarchy ...................................................... A3-38 Chapter A4 The ARMv7-M Instruction Set A4.1 About the instruction set .................................................................. A4-2 A4.2 Unified Assembler Language ........................................................... A4-4 A4.3 Branch instructions .......................................................................... A4-7 A4.4 Data-processing instructions ............................................................ A4-8 A4.5 Status register access instructions ................................................ A4-15 A4.6 Load and store instructions ............................................................ A4-16 A4.7 Load/store multiple instructions ..................................................... A4-19 A4.8 Miscellaneous instructions ............................................................. A4-20 A4.9 Exception-generating instructions .................................................. A4-21 A4.10 Coprocessor instructions ............................................................... A4-22 Chapter A5 Thumb Instruction Set Encoding A5.1 Thumb instruction set encoding ....................................................... A5-2 A5.2 16-bit Thumb instruction encoding ................................................... A5-5 A5.3 32-bit Thumb instruction encoding ................................................. A5-13 Chapter A6 Thumb Instruction Details A6.1 Format of instruction descriptions .................................................... A6-2 A6.2 Standard assembler syntax fields .................................................... A6-7 A6.3 Conditional execution ....................................................................... A6-8 A6.4 Shifts applied to a register ............................................................. A6-12 A6.5 Memory accesses .......................................................................... A6-15 A6.6 Hint Instructions ............................................................................. A6-16 A6.7 Alphabetical list of ARMv7-M Thumb instructions .......................... A6-17 Part B System Level Architecture Chapter B1 System Level Programmers’ Model B1.1 Introduction
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