68000 MICROPROCESSOR Also by the Author from TAB BOOKS Inc
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Build a Swtpc 6800
Southwest Technical Products Corporation 6800 Computer System The Southwest Technical Products 6800 computer system is based upon the Motorola MC6800 microprocessor unit (MPU) and its matching support devices. The 6800 system was chosen for our computer because this set of parts is currently in our opinion the "Benchmark Family" for microprocessor computer systems. It makes it possible for us to provide you with an outstanding computer system having a minimum of parts, but with outstanding versatility and ease of use. In addition to the outstanding hardware system, the Motorola 6800 has without question the most complete set of documentation yet made available for a microprocessor system. The 714 page Applications Manual, for example, contains material on programming techniques, system organization, input/output techniques, hardware characteristics, peripheral control techniques, and more. Also available is a Programmers Manual which details the various types of software available for the system and instructions for programming and using the unique interface system that is part of the 6800 system. The M6800 family of parts minimizes the number of, required components and support parts, provides extremely simple interfacing to external devices and has outstanding documentation. The MC6800 is an eight-bit parallel microprocessor with addressing capability of up to 45,536 words (BYTES) of data. The system is TTL compatible requiring only a single fine-volt power supply. All devices and memory in the 6800 computer family are connected to an 8-bit bi-directional data bus. In addition to this a 16-bit address bus is provided to specify memory location. This later bus is also used as a tool to specify the particular input/ output device to be selected when the 6800 family interface devices are used. -
Exorciser USER's GUIDE
M6809EXOR(D1) ®MOTOROLA M6809 EXORciser User's Guide MICROSYSTEMS M6809EXOR (Dl} SEPTEMBER 1979 M6809 EXORciser USER'S GUIDE The information in this document has been carefully checked and is believed to be entirely reliable. However, no res pons i bi 1ity is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any products herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. EXORciser®, EXORdisk, and EXbug are trademarks of Motorola Inc. First Edition ©Copyright 1979 by Motorola Inc. TABLE OF CONTENTS Page CHAPTER 1 GENERAL INFORMATION 1.1 INTRODUCTION 1-1 1.2 FEATURES 1-1 1.3 SPECIFICATIONS 1-2 1.4 EQUIPMENT SUPPLIED 1-2 1.5 GENERAL DESCRIPTION 1-3 1.5.1 EXORciser Memory Parity 1-3 1.5.2 Dual Map Concepts 1-5 1.5.3 Second level Interrupt Feature 1-7 1.5.4 Dynamic System Bus 1-10 CHAPTER 2 INSTALLATION INSTRUCTIONS AND HARDWARE PREPARATION 2.1 INTRODUCTION 2-1 2.2 UNPACKING INSTRUCTIONS 2-1 2.3 INSPECTION 2-1 2.4 INSTALLATION INSTRUCTIONS 2-1 2.5 DATA TERMINAL SELECTION AND CONNECTIONS 2-2 2.5.1 RS-232C Interconnections 2-2 2.5.2 20mA Current loop Interconnections 2-2 2.6 PREPARATION OF SYSTEM MODULES 2-2 CHAPTER 3 OPERATING INSTRUCTIONS 3.1 INTRODUCTION 3-1 3.2 SWITCHES AND INDICATORS 3-1 3.2.1 Front Panel Switches and Indicators 3-1 3.2.2 Switches on the DEbug Module 3-2 3.3 INITIALIZATION 3-3 3.3.1 -
January 1977 I
CALIFORNIA STATE UN:::VERSITY, NORTHRIDGE HICROPROCESSORS / A graduate p~ojc~t report s~~oitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering .. I by Thor,las Carson Hecht ~- .January 1977 i The graduate project report of Thomas Carson Hecht is approved: California State University, Northridge Oitober 1976 ii TABLE OF CONTENTS TITLE PAGE i. 1-.PPROVAL PAGE i.i LIST OF FIGURES i.v ABSTRP.C'I' vii INTRODUCTION 1 INTRODUCTION 1'0 MICROPROCESSORS 3 THE 6800 HINIHAL SYSTEM 7 THE HICROCOMPUTER ... , .. ,~ .. c•<~c•••••••••••••,.tt•••••••.••,•·•••••-~~·•'~••oo 18 }!ICROELECTRONIC P.ESISTOiZS AND RESISTOR TRH'lMING 31 AJ!FL ICATT.O!'·! OF THE HICROCOI'-1PUTER TO LASER TRIH~llNG R),DJIR ERRORS AND THEIR CORRECTION 65 THE ERROR COF,RECI'TON SYSTEM •••••••c••••.,••••••••••••••• .. •-ta•••••·• 69 THE HICROPROCESSOR SYSTEN 34 LIHJ.TATWNS AND ACCURACY 97 SUNNARY 100 APPENDIX A 6800 IN.~)J'RUC.TIO.N S.&T •••••••••••••••••••• 102 APPEND IX E HOTOIWLA 6800 .CI.ROJ LTS -t.~ ...... ~ ... , ............. ~ ............... 105 lJ:'FENDIX C C.ALCJJL.A.TOR .CHIP DATA SH.EET •• , , .•••• , .•••.•••••••••••• llO 'I + .. .;:,. .. t •· II " • • • 115 BIBLlOGR.t,PHY ••••••••• otto'W ...... ll9 Li.i LIST OF FIGURES FIGURE 1: THE 6800 Mli'Hr·L'\L SYSTEH FIGURE 2: OPERATION OF THE ACIA FIGURE 3: OPERATION OF THE PIA FIGURE Lf: BLOCK DIAGRP..H OF THE PIA/CALCULATOR CHIP INTERFACE FIGURE 5: SCHEHATIC AND TRUTH TABLE OF THE PRIOP.ITY ENCODER FIGURE 6: SCHElv!ATIC OF THE QUAD AND FIGURE 7: SCHEHATIC OF 'I'JIE TNTERRUPT PRIORITY CIRCUIT FIGURE 8: LOCATIONS ADDRESSED BY THE MPU FOR DIFFERENT PRIORITY Ii'fTERlWPTS FIGURE 9: .tv1EHORY H1\P OF THE MICROCOl1PUTER FIGURE 10: CALCULATION OF RESISTANCE USING SQUARES AND SHEET RESISTANCE FIGURE 11: DIFFERENT TYPES OF TRIHS FIGURE 12: RESISTANCE AS A FUNCTION OF TRHllviiNG FIGURE 13: PLOT OF % OF INCREASE IN RESISTANCE VS. -
Lecture 1: Course Introduction G Course Organization G Historical Overview G Computer Organization G Why the MC68000? G Why Assembly Language?
Lecture 1: Course introduction g Course organization g Historical overview g Computer organization g Why the MC68000? g Why assembly language? Microprocessor-based System Design 1 Ricardo Gutierrez-Osuna Wright State University Course organization g Grading Instructor n Exams Ricardo Gutierrez-Osuna g 1 midterm and 1 final Office: 401 Russ n Homework Tel:775-5120 g 4 problem sets (not graded) [email protected] n Quizzes http://www.cs.wright.edu/~rgutier g Biweekly Office hours: TBA n Laboratories g 5 Labs Teaching Assistant g Grading scheme Mohammed Tabrez Office: 339 Russ [email protected] Weight (%) Office hours: TBA Quizes 20 Laboratory 40 Midterm 20 Final Exam 20 Microprocessor-based System Design 2 Ricardo Gutierrez-Osuna Wright State University Course outline g Module I: Programming (8 lectures) g MC68000 architecture (2) g Assembly language (5) n Instruction and addressing modes (2) n Program control (1) n Subroutines (2) g C language (1) g Module II: Peripherals (9) g Exception processing (1) g Devices (6) n PI/T timer (2) n PI/T parallel port (2) n DUART serial port (1) g Memory and I/O interface (1) g Address decoding (2) Microprocessor-based System Design 3 Ricardo Gutierrez-Osuna Wright State University Brief history of computers GENERATION FEATURES MILESTONES YEAR NOTES Asia Minor, Abacus 3000BC Only replaced by paper and pencil Mech., Blaise Pascal, Pascaline 1642 Decimal addition (8 decimal figs) Early machines Electro- Charles Babbage Differential Engine 1823 Steam powered (3000BC-1945) mech. Herman Hollerith, -
The Birth, Evolution and Future of Microprocessor
The Birth, Evolution and Future of Microprocessor Swetha Kogatam Computer Science Department San Jose State University San Jose, CA 95192 408-924-1000 [email protected] ABSTRACT timed sequence through the bus system to output devices such as The world's first microprocessor, the 4004, was co-developed by CRT Screens, networks, or printers. In some cases, the terms Busicom, a Japanese manufacturer of calculators, and Intel, a U.S. 'CPU' and 'microprocessor' are used interchangeably to denote the manufacturer of semiconductors. The basic architecture of 4004 same device. was developed in August 1969; a concrete plan for the 4004 The different ways in which microprocessors are categorized are: system was finalized in December 1969; and the first microprocessor was successfully developed in March 1971. a) CISC (Complex Instruction Set Computers) Microprocessors, which became the "technology to open up a new b) RISC (Reduced Instruction Set Computers) era," brought two outstanding impacts, "power of intelligence" and "power of computing". First, microprocessors opened up a new a) VLIW(Very Long Instruction Word Computers) "era of programming" through replacing with software, the b) Super scalar processors hardwired logic based on IC's of the former "era of logic". At the same time, microprocessors allowed young engineers access to "power of computing" for the creative development of personal 2. BIRTH OF THE MICROPROCESSOR computers and computer games, which in turn led to growth in the In 1970, Intel introduced the first dynamic RAM, which increased software industry, and paved the way to the development of high- IC memory by a factor of four. -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features.......................... -
ED135388.Pdf
DOCUMENT RESUME ED 135 388 IB 004 499 AUTHOR Kirby, Paul J.; Gardner, Edward M. Tin! Microcomputer Controlled, interactive Testing Terminal Development. INSTITUTION Air Force Human Resources lab., Lowry AFB, Colo. Technical Training Div. SPONS AGENCY Air Force Human Resources Lab., Brooks AFB, Texas. REPORT NO AIHEI-TR-76-66 PUB DATE Oct 76 NOTE 27p. EDRS PRICE MF-$0.83 HC-$2.06 Plus Postage. DESCRIPTORS Autcinstructional Aids; Computer Programs; *Computer Science; *Individual Tests; Man Machine Systems; Self Pacing Machines; *Testing; *Test Scoring Machines IDENTIFIERS Microcomputers ABSTRACT The evolution of a self-contained test scoring terminal is presented. The rationale for thedesign is presented along with an evolutionary description ofthe requirements for the system. The sequence of software andhardware tools, which were developed in order to build the device, are alsodescribed in this report. The resulting device,which contains an imbedded microcomputer is functionally described and the testingstrategies which it cur.rently supports axe presented.(Author) *********************************************************************** * Dcraents acquired by ERIC include many informalunpublished * *materls not available from other sources. ERICmakes every effort * *to obtain tbe best copyavailable. Nevertheless, items of marginal * *reproducibility are often encountered andthis affects the quality * *of the microfiche and hardcopyxeproductions ERIC makes available * *via the ERIC Document ReproductionService (EDRS). EDRS is not * *responsible -
Programmable Digital Microcircuits - a Survey with Examples of Use
- 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention. -
Technician's Guide to 68HC11 Microcontroller.Pdf
chapter 1 Introduction to Computer Hardware Objectives I ntr odu ct ion to Com put er H ardw are After completing this chapter, you should be able to: ◗ Describe the fundamental elements of every computer system: proces- sor, memory, and input/output ◗ Compare elements of the HC11 block diagram to the fundamentals of every computer system ◗ Describe the use of busses to connect computer elements ◗ Explain the three major functional units of a processor ◗ Illustrate the typical registers inside the processor ◗ List the HC11 processor registers ◗ Discuss the HC11 processor modes ◗ Compare and contrast various memory types ◗ Describe the on-chip memory of the HC11 ◗ Specify input/output functions present on most computers ◗ Use some basic BUFFALO commands to control the EVBU Outline ◗ 1.1 Elements of Every Computer ◗ 1.2 Elements of Processors ◗ 1.3 Introduction to Memory ◗ 1.4 Memory Types ◗ 1.5 Input/Output 1 ◗ 1.6 EVBU/BUFFALO Technician’s Guide to the 68HC11 Microcontroller Introduction Computer systems have been developed for a variety of functions and purposes. General-application desktop machines are the most common. They run a variety of software applications, such as word processing, financial management and data processing. They have all but replaced the typewriter as a necessary business tool. Computers are also present in automobiles, appliances, airplanes and all types of controllers and electromechanical devices. Despite the differences among these computer systems, they all share fundamental components and design. The purpose of this chapter is to provide an understanding of the fundamental components of a computer system. A conceptual presentation regarding the elements of every computer system is made with sufficient detail to establish a foundation for these concepts. -
Gestalt Manager 1
CHAPTER 1 Gestalt Manager 1 This chapter describes how you can use the Gestalt Manager and other system software facilities to investigate the operating environment. You need to know about the 1 operating environment if your application takes advantage of hardware (such as a Gestalt Manager floating-point unit) or software (such as Color QuickDraw) that is not available on all Macintosh computers. You can also use the Gestalt Manager to inform the Operating System that your software is present and to find out about other software registered with the Gestalt Manager. The Gestalt Manager is available in system software versions 6.0.4 and later. The MPW software development system and some other development environments supply code that allows you to use the Gestalt Manager on earlier system software versions; check the documentation provided with your development system. In system software versions earlier than 6.0.4, you can retrieve a limited description of the operating environment with the SysEnvirons function, also described in this chapter. You need to read this chapter if you take advantage of specific hardware or software features that may not be present on all versions of the Macintosh, or if you wish to inform other software that your software is present in the operating environment. This chapter describes how the Gestalt Manager works and then explains how you can ■ determine whether the Gestalt Manager is available ■ call the Gestalt function to investigate the operating environment ■ make information about your own hardware or software available to other applications ■ retrieve a limited description of the operating environment even if the Gestalt Manager is not available About the Gestalt Manager 1 The Macintosh family of computers includes models that use a number of different processors, some accompanied by a floating-point unit (FPU) or memory management unit (MMU). -
Dissertation Applications of Field Programmable Gate
DISSERTATION APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL Submitted by Matthew Viele Department of Mechanical Engineering In partial fulfillment of the requirements For the Degree of Doctor of Philosophy Colorado State University Fort Collins, Colorado Summer 2012 Doctoral Committee: Advisor: Bryan D. Willson Anthony J. Marchese Robert N. Meroney Wade O. Troxell ABSTRACT APPLICATIONS OF FIELD PROGRAMMABLE GATE ARRAYS FOR ENGINE CONTROL Automotive engine control is becoming increasingly complex due to the drivers of emissions, fuel economy, and fault detection. Research in to new engine concepts is often limited by the ability to control combustion. Traditional engine-targeted micro controllers have proven difficult for the typical engine researchers to use and inflexible for advanced concept engines. With the advent of Field Programmable Gate Array (FPGA) based engine control system, many of these impediments to research have been lowered. This dissertation will talk about three stages of FPGA engine controller appli- cation. The most basic and widely distributed is the FPGA as an I/O coprocessor, tracking engine position and performing other timing critical low-level tasks. A later application of FPGAs is the use of microsecond loop rates to introduce feedback con- trol on the crank angle degree level. Lastly, the development of custom real-time computing machines to tackle complex engine control problems is presented. This document is a collection of papers and patents that pertain to the use of FPGAs for the above tasks. Each task is prefixed with a prologue section to give the history of the topic and context of the paper in the larger scope of FPGA based engine control.