Using and Porting the GNU Compiler Collection

Total Page:16

File Type:pdf, Size:1020Kb

Using and Porting the GNU Compiler Collection Using and Porting the GNU Compiler Collection Richard M. Stallman Last updated 28 July 1999 for gcc-2.95 Copyright c 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1998, 1999 Free Software Foundation, Inc. For GCC Version 2.95 Published by the Free Software Foundation 59 Temple Place - Suite 330 Boston, MA 02111-1307, USA Last printed April, 1998. Printed copies are available for $50 each. ISBN 1-882114-37-X Permission is granted to make and distribute verbatim copies of this manual provided the copyright notice and this permission notice are preserved on all copies. Permission is granted to copy and distribute modified versions of this manual under the conditions for verbatim copying, provided also that the sections entitled \GNU General Public License" and \Funding for Free Software" are included exactly as in the original, and provided that the entire resulting derived work is distributed under the terms of a permission notice identical to this one. Permission is granted to copy and distribute translations of this manual into another lan- guage, under the above conditions for modified versions, except that the sections entitled \GNU General Public License" and \Funding for Free Software", and this permission no- tice, may be included in translations approved by the Free Software Foundation instead of in the original English. Chapter 1: Compile C, C++, Objective C, or Fortran 1 1 Compile C, C++, Objective C, or Fortran The C, C++, and Objective C, and Fortran versions of the compiler are integrated; this is why we use the name \GNU Compiler Collection". GCC can compile programs written in C, C++, Objective C, or Fortran. The Fortran compiler is described in a separate manual. \GCC" is a common shorthand term for the GNU Compiler Collection. This is both the most general name for the compiler, and the name used when the emphasis is on compiling C programs (as the abbreviation formerly stood for \GNU C Compiler"). When referring to C++ compilation, it is usual to call the compiler \G++". Since there is only one compiler, it is also accurate to call it \GCC" no matter what the language context; however, the term \G++" is more useful when the emphasis is on compiling C++ programs. We use the name \GCC" to refer to the compilation system as a whole, and more specifically to the language-independent part of the compiler. For example, we refer to the optimization options as affecting the behavior of \GCC" or sometimes just \the compiler". Front ends for other languages, such as Ada 9X, Fortran, Modula-3, and Pascal, are under development. These front-ends, like that for C++, are built in subdirectories of GCC and link to it. The result is an integrated compiler that can compile programs written in C, C++, Objective C, or any of the languages for which you have installed front ends. In this manual, we only discuss the options for the C, Objective-C, and C++ compilers and those of the GCC core. Consult the documentation of the other front ends for the options to use when compiling programs written in other languages. G++ is a compiler, not merely a preprocessor. G++ builds object code directly from your C++ program source. There is no intermediate C version of the program. (By contrast, for example, some other implementations use a program that generates a C program from your C++ source.) Avoiding an intermediate C representation of the program means that you get better object code, and better debugging information. The GNU debugger, GDB, works with this information in the object code to give you comprehensive C++ source-level editing capabilities (see section \C and C++" in Debugging with GDB). 2 Using and Porting the GNU Compiler Collection (GCC) Chapter 2: GCC Command Options 3 2 GCC Command Options When you invoke GCC, it normally does preprocessing, compilation, assembly and link- ing. The \overall options" allow you to stop this process at an intermediate stage. For example, the `-c' option says not to run the linker. Then the output consists of object files output by the assembler. Other options are passed on to one stage of processing. Some options control the pre- processor and others the compiler itself. Yet other options control the assembler and linker; most of these are not documented here, since you rarely need to use any of them. Most of the command line options that you can use with GCC are useful for C programs; when an option is only useful with another language (usually C++), the explanation says so explicitly. If the description for a particular option does not mention a source language, you can use that option with all supported languages. See Section 2.3 [Compiling C++ Programs], page 11, for a summary of special options for compiling C++ programs. The gcc program accepts options and file names as operands. Many options have mul- tiletter names; therefore multiple single-letter options may not be grouped: `-dr' is very different from `-d -r'. You can mix options and other arguments. For the most part, the order you use doesn't matter. Order does matter when you use several options of the same kind; for example, if you specify `-L' more than once, the directories are searched in the order specified. Many options have long names starting with `-f' or with `-W'|for example, `-fforce-mem', `-fstrength-reduce', `-Wformat' and so on. Most of these have both positive and negative forms; the negative form of `-ffoo' would be `-fno-foo'. This manual documents only one of these two forms, whichever one is not the default. 2.1 Option Summary Here is a summary of all the options, grouped by type. Explanations are in the following sections. Overall Options See Section 2.2 [Options Controlling the Kind of Output], page 10. -c -S -E -o file -pipe -v --help -x language C Language Options See Section 2.4 [Options Controlling C Dialect], page 12. -ansi -fstd -fallow-single-precision -fcond-mismatch -fno-asm -fno-builtin -ffreestanding -fhosted -fsigned-bitfields -fsigned-char -funsigned-bitfields -funsigned-char -fwritable-strings -traditional -traditional-cpp -trigraphs C++ Language Options See Section 2.5 [Options Controlling C++ Dialect], page 16. -fno-access-control -fcheck-new -fconserve-space -fdollars-in-identifiers -fno-elide-constructors -fexternal-templates -ffor-scope -fno-for-scope -fno-gnu-keywords -fguiding-decls -fhandle-signatures 4 Using and Porting the GNU Compiler Collection (GCC) -fhonor-std -fhuge-objects -fno-implicit-templates -finit-priority -fno-implement-inlines -fname-mangling-version-n -fno-default-inline -foperator-names -fno-optional-diags -fpermissive -frepo -fstrict-prototype -fsquangle -ftemplate-depth-n -fthis-is-variable -fvtable-thunks -nostdinc++ -Wctor-dtor-privacy -Wno-deprecated -Weffc++ -Wno-non-template-friend -Wnon-virtual-dtor -Wold-style-cast -Woverloaded-virtual -Wno-pmf-conversions -Wreorder -Wsign-promo -Wsynth Warning Options See Section 2.6 [Options to Request or Suppress Warnings], page 22. -fsyntax-only -pedantic -pedantic-errors -w -W -Wall -Waggregate-return -Wbad-function-cast -Wcast-align -Wcast-qual -Wchar-subscripts -Wcomment -Wconversion -Werror -Wformat -Wid-clash-len -Wimplicit -Wimplicit-int -Wimplicit-function-declaration -Wimport -Werror-implicit-function-declaration -Winline -Wlarger-than-len -Wlong-long -Wmain -Wmissing-declarations -Wmissing-noreturn -Wmissing-prototypes -Wmultichar -Wnested-externs -Wno-import -Wparentheses -Wpointer-arith -Wredundant-decls -Wreturn-type -Wshadow -Wsign-compare -Wstrict-prototypes -Wswitch -Wtraditional -Wtrigraphs -Wundef -Wuninitialized -Wunused -Wwrite-strings -Wunknown-pragmas Debugging Options See Section 2.7 [Options for Debugging Your Program or GCC], page 29. -a -ax -dletters -fdump-unnumbered -fpretend-float -fprofile-arcs -ftest-coverage -g -glevel -gcoff -gdwarf -gdwarf-1 -gdwarf-1+ -gdwarf-2 -ggdb -gstabs -gstabs+ -gxcoff -gxcoff+ -p -pg -print-file-name=library -print-libgcc-file-name -print-prog-name=program -print-search-dirs -save-temps Optimization Options See Section 2.8 [Options that Control Optimization], page 35. -fbranch-probabilities -foptimize-register-moves -fcaller-saves -fcse-follow-jumps -fcse-skip-blocks -fdelayed-branch -fexpensive-optimizations -ffast-math -ffloat-store -fforce-addr -fforce-mem -fdata-sections -ffunction-sections -fgcse -finline-functions -finline-limit-n -fkeep-inline-functions -fno-default-inline -fno-defer-pop -fno-function-cse -fno-inline -fno-peephole -fomit-frame-pointer -fregmove -frerun-cse-after-loop -frerun-loop-opt -fschedule-insns -fschedule-insns2 -fstrength-reduce -fthread-jumps -funroll-all-loops -funroll-loops -fmove-all-movables -freduce-all-givs -fstrict-aliasing Chapter 2: GCC Command Options 5 -O -O0 -O1 -O2 -O3 -Os Preprocessor Options See Section 2.9 [Options Controlling the Preprocessor], page 41. -Aquestion(answer) -C -dD -dM -dN -Dmacro[=defn] -E -H -idirafter dir -include file -imacros file -iprefix file -iwithprefix dir -iwithprefixbefore dir -isystem dir -isystem-c++ dir -M -MD -MM -MMD -MG -nostdinc -P -trigraphs -undef -Umacro -Wp,option Assembler Option See Section 2.10 [Passing Options to the Assembler], page 44. -Wa,option Linker Options See Section 2.11 [Options for Linking], page 44. object-file-name -llibrary -nostartfiles -nodefaultlibs -nostdlib -s -static -shared -symbolic -Wl,option -Xlinker option -u symbol Directory Options See Section 2.12 [Options for Directory Search], page 46. -Bprefix -Idir -I- -Ldir -specs=file Target Options See Section 2.13 [Target Options], page 47. -b machine -V version Machine Dependent Options See Section 2.14 [Hardware Models
Recommended publications
  • Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences
    Downloaded from orbit.dtu.dk on: Oct 02, 2021 Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo; Karlsson, Sven Published in: Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) Publication date: 2014 Link back to DTU Orbit Citation (APA): Hindborg, A. E., Schleuniger, P., Jensen, N. B., & Karlsson, S. (2014). Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. In A. Morawiec, & J. Hinderscheit (Eds.), Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP) IEEE. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research. You may not further distribute the material or use it for any profit-making activity or commercial gain You may freely distribute the URL identifying the publication in the public portal If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences Andreas Erik Hindborg, Pascal Schleuniger Nicklas Bo Jensen, Sven Karlsson DTU Compute – Technical University of Denmark fahin,pass,nboa,[email protected] Abstract—Field-programmable gate arrays, FPGAs, are at- speedup of up to 64% over a Xilinx MicroBlaze based baseline tractive implementation platforms for low-volume signal and system.
    [Show full text]
  • Computer Architectures
    Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative ..
    [Show full text]
  • RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
    RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features..........................
    [Show full text]
  • MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev
    Order this document by: MOTOROLA AN2109/D SEMICONDUCTOR APPLICATION NOTE MPC555 Interrupts by John Dunlop, Josef Fuchs, and Steve Mihalik Rev. 0, 26 July 2001 1 Introduction The MPC555 has numerous timers, peripherals and input pins that can generate interrupts. This appli- cation note describes how the interrupts work and how to write software for their initialization and ser- vice routines. Examples illustrate how interrupt handler routines written in assembler, C and even controlled by an operating system can have a dramatic variation in overhead. This overhead is almost entirely caused by the amount of context, (i.e., registers), saved and restored in the routine. Although this application note focuses on interrupts, the discussion of context saving and restoring ap- plies to other exceptions as well as other Motorola PowerPC™ microcontrollers. In addition, later MPC5xx microprocessors include an enhanced interrupt controller which has features to reduce laten- cy. A summary of these features, which are optional to use in these later microcontrollers is listed in Section Appendix B Enhanced Interrupt Controller Summary. 2 Background 2.1 Interrupts versus Exceptions Definitions of “interrupts” and “exceptions” are not always consistent in PowerPC™ literature. The fol- lowing definitions are used for this application note. Exceptions are events that change normal program flow and machine state. Some examples of excep- tions are reset, decrementer passing zero, system call instruction, various bus access errors, and even a software or hardware debugger. When an exception occurs, a short hardware context switch takes place and the processor branches to an address (exception vector) which is unique for each type of ex- ception.
    [Show full text]
  • Bringing Virtualization to the X86 Architecture with the Original Vmware Workstation
    12 Bringing Virtualization to the x86 Architecture with the Original VMware Workstation EDOUARD BUGNION, Stanford University SCOTT DEVINE, VMware Inc. MENDEL ROSENBLUM, Stanford University JEREMY SUGERMAN, Talaria Technologies, Inc. EDWARD Y. WANG, Cumulus Networks, Inc. This article describes the historical context, technical challenges, and main implementation techniques used by VMware Workstation to bring virtualization to the x86 architecture in 1999. Although virtual machine monitors (VMMs) had been around for decades, they were traditionally designed as part of monolithic, single-vendor architectures with explicit support for virtualization. In contrast, the x86 architecture lacked virtualization support, and the industry around it had disaggregated into an ecosystem, with different ven- dors controlling the computers, CPUs, peripherals, operating systems, and applications, none of them asking for virtualization. We chose to build our solution independently of these vendors. As a result, VMware Workstation had to deal with new challenges associated with (i) the lack of virtual- ization support in the x86 architecture, (ii) the daunting complexity of the architecture itself, (iii) the need to support a broad combination of peripherals, and (iv) the need to offer a simple user experience within existing environments. These new challenges led us to a novel combination of well-known virtualization techniques, techniques from other domains, and new techniques. VMware Workstation combined a hosted architecture with a VMM. The hosted architecture enabled a simple user experience and offered broad hardware compatibility. Rather than exposing I/O diversity to the virtual machines, VMware Workstation also relied on software emulation of I/O devices. The VMM combined a trap-and-emulate direct execution engine with a system-level dynamic binary translator to ef- ficiently virtualize the x86 architecture and support most commodity operating systems.
    [Show full text]
  • Static Fault Attack on Hardware DES Registers
    Static Fault Attack on Hardware DES Registers Philippe Loubet-Moundi, Francis Olivier, and David Vigilant Gemalto, Security Labs, France {philippe.loubet-moundi,david.vigilant,francis.olivier}@gemalto.com http://www.gemalto.com Abstract. In the late nineties, Eli Biham and Adi Shamir published the first paper on Differential Fault Analysis on symmetric key algorithms. More specifically they introduced a fault model where a key bit located in non-volatile memory is forced to 0=1 with a fault injection. In their scenario the fault was permanent, and could lead the attacker to full key recovery with low complexity. In this paper, another fault model is considered: forcing a key bit to 0=1 in the register of a hardware block implementing Data Encryption Stan- dard. Due to the specific location of the fault, the key modification is not permanent in the life of the embedded device, and this leads to apply a powerful safe-error like attack. This paper reports a practical validation of the fault model on two actual circuits, and discusses limitations and efficient countermeasures against this threat. Keywords: Hardware DES, fault attacks, safe-error, register attacks 1 Introduction Fault attacks against embedded systems exploit the disturbed execution of a given program to infer sensitive data, or to execute unauthorized parts of this program. Usually a distinction is made between permanent faults and transient faults.A permanent fault alters the behavior of the device from the moment it is injected, and even if the device is powered off [8]. On the other hand, a transient fault has an effect limited in time, only a few cycles of the process are affected.
    [Show full text]
  • Bdigdb User Manual
    bdiGDB BDM interface for GNU Debugger PowerPCMPC8xx/MPC5xx User Manual Manual Version 1.16 for BDI2000 ©1997-2001 by Abatron AG bdiGDB for GNU Debugger, BDI2000 (MPC8xx/MPC5xx) User Manual 2 1 Introduction ................................................................................................................................. 3 1.1 BDI2000................................................................................................................................. 3 1.2 BDI Configuration .................................................................................................................. 4 2 Installation ................................................................................................................................... 5 2.1 Connecting the BDI2000 to Target......................................................................................... 5 2.1.1 Changing Target Processor Type ................................................................................. 7 2.2 Connecting the BDI2000 to Power Supply............................................................................. 8 2.2.1 External Power Supply................................................................................................. 8 2.2.2 Power Supply from Target System ............................................................................... 9 2.3 Status LED «MODE»........................................................................................................... 10 2.4 Connecting the BDI2000 to Host ........................................................................................
    [Show full text]
  • Validating Register Allocation and Spilling
    Validating Register Allocation and Spilling Silvain Rideau1 and Xavier Leroy2 1 Ecole´ Normale Sup´erieure,45 rue d'Ulm, 75005 Paris, France [email protected] 2 INRIA Paris-Rocquencourt, BP 105, 78153 Le Chesnay, France [email protected] Abstract. Following the translation validation approach to high- assurance compilation, we describe a new algorithm for validating a posteriori the results of a run of register allocation. The algorithm is based on backward dataflow inference of equations between variables, registers and stack locations, and can cope with sophisticated forms of spilling and live range splitting, as well as many architectural irregular- ities such as overlapping registers. The soundness of the algorithm was mechanically proved using the Coq proof assistant. 1 Introduction To generate fast and compact machine code, it is crucial to make effective use of the limited number of registers provided by hardware architectures. Register allocation and its accompanying code transformations (spilling, reloading, coa- lescing, live range splitting, rematerialization, etc) therefore play a prominent role in optimizing compilers. As in the case of any advanced compiler pass, mistakes sometimes happen in the design or implementation of register allocators, possibly causing incorrect machine code to be generated from a correct source program. Such compiler- introduced bugs are uncommon but especially difficult to exhibit and track down. In the context of safety-critical software, they can also invalidate all the safety guarantees obtained by formal verification of the source code, which is a growing concern in the formal methods world. There exist two major approaches to rule out incorrect compilations. Com- piler verification proves, once and for all, the correctness of a compiler or compi- lation pass, preferably using mechanical assistance (proof assistants) to conduct the proof.
    [Show full text]
  • V810 Familytm 32-Bit Microprocessor
    V810 FAMILYTM 32-BIT MICROPROCESSOR ARCHITECTURE V805TM V810TM V820TM V821TM Document No. U10082EJ1V0UM00 (1st edition) Date Published October 1995P © 11995 Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti- static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Gestalt Manager 1
    CHAPTER 1 Gestalt Manager 1 This chapter describes how you can use the Gestalt Manager and other system software facilities to investigate the operating environment. You need to know about the 1 operating environment if your application takes advantage of hardware (such as a Gestalt Manager floating-point unit) or software (such as Color QuickDraw) that is not available on all Macintosh computers. You can also use the Gestalt Manager to inform the Operating System that your software is present and to find out about other software registered with the Gestalt Manager. The Gestalt Manager is available in system software versions 6.0.4 and later. The MPW software development system and some other development environments supply code that allows you to use the Gestalt Manager on earlier system software versions; check the documentation provided with your development system. In system software versions earlier than 6.0.4, you can retrieve a limited description of the operating environment with the SysEnvirons function, also described in this chapter. You need to read this chapter if you take advantage of specific hardware or software features that may not be present on all versions of the Macintosh, or if you wish to inform other software that your software is present in the operating environment. This chapter describes how the Gestalt Manager works and then explains how you can ■ determine whether the Gestalt Manager is available ■ call the Gestalt function to investigate the operating environment ■ make information about your own hardware or software available to other applications ■ retrieve a limited description of the operating environment even if the Gestalt Manager is not available About the Gestalt Manager 1 The Macintosh family of computers includes models that use a number of different processors, some accompanied by a floating-point unit (FPU) or memory management unit (MMU).
    [Show full text]
  • Cyclone LC Programmers User Manual Purchase Agreement
    Cyclone LC Programmers User Manual Purchase Agreement P&E Microcomputer Systems, Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. P&E Microcomputer Systems, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein. This software and accompanying documentation are protected by United States Copyright law and also by International Treaty provisions. Any use of this software in violation of copyright law or the terms of this agreement will be prosecuted. All the software described in this document is copyrighted by P&E Microcomputer Systems, Inc. Copyright notices have been included in the software. P&E Microcomputer Systems authorizes you to make archival copies of the software and documentation for the sole purpose of back-up and protecting your investment from loss. Under no circumstances may you copy this software or documentation for the purpose of distribution to others. Under no conditions may you remove the copyright notices from this software or documentation. This software may be used by one person on as many computers as that person uses, provided that the software is never used on two computers at the same time. P&E expects that group programming projects making use of this software will purchase a copy of the software and documentation for each user in the group. Contact P&E for volume discounts and site licensing agreements. P&E Microcomputer Systems does not assume any liability for the use of this software beyond the original purchase price of the software.
    [Show full text]