P. 6 Editor's Foreword Celebrating VME's Strength and Endurance P

p. 6 Editor’s Foreword p. 20 Special Feature Celebrating VME’s VITA Technologies strength and endurance Hall of Fame Let’s face it: what’s probably top of your mind is how to ensure your program stands the best WE INNOVATE. WE DELIVER. chance of success: getting to deployment faster, at lower cost and with less risk. That’s what your YOU SUCCEED. customers are demanding.

At Abaco Systems, that’s our business. We could Find out more at abaco.com talk forever about how everything we do is or follow us @AbacoSys based on industry standards and modular, open architectures – but that’s not so important. It’s just a starting point for our innovation. What’s important is that you work with a company with the experience to back up our promises, and that’s entirely committed to your success.

portfolio_advert_March2016_v2.indd 1 23/03/2016 11:59

SPRING/SUMMER 2016 | VOLUME 34 | NUMBER 1 @VitaTechnology

On the cover The VITA Technologies 2016 Resource Guide showcases technologies based on VITA standards, including FMC, OpenVPX, XMC/PMC, and related rugged boards, systems, and components. Featured on the cover: Annapolis Micro Systems Wild40 Ecosystem for OpenVPX 3U and Curtiss- Wright Defense Solutions AFT Cooled 3U VPX COTS System.

FMC+ standard propels embedded design to new heights By Jeremy Banks, Curtiss-Wright, ADDITIONAL FEATURES » p. 10 and Jim Everett, Xilinx 20 Special Feature Jerry Gipper VITA Technology Hall of Fame 2016

DEPARTMENTS

6 Editor’s Foreword Jerry Gipper Celebrating VME’s strength and endurance

8 VITA Standards Update Jerry Gipper VITA Standards Organization activity updates Very high-speed sampling and serial ADCs in embedded systems By Thierry Wastiaux, 22 Primetime Choices » p. 14 Interface Concept

24 VITA Technologies Resource Guide FMC ...... 25 Networking ...... 26 OpenVPX ...... 27 Operating Systems and Tools ...... 38 PMC ...... 37 Small Form Factor ...... 40 VME ...... 40 Modular Open Radio Frequency VPX...... 43 Architecture boot camp XMC/PMC ...... 47 By Jerry Gipper, » p. 17 Editorial Director

All registered brands and trademarks within VITA Technologies magazine are the property of their respective owners. ™VPX and its logo is a registered product/trademark of VITA. © 2016 OpenSystems Media © 2016 VITA Technologies

enviroink.indd 1 10/1/08 10:44:38 AM 4 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com Advertiser Index

2 Abaco Systems – We innovate. We deliver. You succeed. 3 Annapolis Micro Systems, Inc. – EDITORIAL DIRECTOR Jerry Gipper [email protected] WILDSTAR OpenVPX Ecosystem MANAGING EDITOR Jennifer Hesse [email protected] 15 Elma Electronic – We take our GROUP EDITORIAL DIRECTOR John McHale [email protected] leadership role seriously E-CAST MANAGER Joy Gilmore [email protected] 7 Excalibur Systems, Inc. – mil-1553.com CREATIVE DIRECTOR Steph Sweet [email protected] 24 Highland Technology, Inc. – DIGITAL MEDIA MANAGER Rachel Wallace [email protected] Continuing our long term commitment SENIOR WEB DEVELOPER Konrad Witte [email protected] to VME WEB DEVELOPER Paul Nelson [email protected] 9 Interface Concept – Build your CONTRIBUTING DESIGNER Joann Toth [email protected] own VPX system 13 LCR Embedded Systems – SALES Rugged chassis, backplanes, and SALES MANAGER Tom Varcie [email protected] integrated systems (586) 415-6500 19 Pentair Electronics Protection – STRATEGIC ACCOUNT MANAGER Rebecca Barker [email protected] VPX & VME systems chassis and front (281) 724-8021 panels express delivery STRATEGIC ACCOUNT MANAGER Bill Barron [email protected] (516) 376-9838 48 Pentek, Inc. – Got tough software radio design challenges? STRATEGIC ACCOUNT MANAGER Eric Henry [email protected] (541) 760-5361 16 Themis Computer – NanoSWITCH STRATEGIC ACCOUNT MANAGER Kathleen Wackowski [email protected] 23 Vector Electronics & Technology, Inc. – (978) 888-7367 VME/VXS/cPCI chassis, backplanes & SOUTHERN CALIFORNIA REGIONAL SALES MANAGER Len Pettek [email protected] accessories (805) 231-9582 18 VEROTEC Electronics Packaging – SOUTHWEST REGIONAL SALES MANAGER Barbara Quinlan [email protected] (480) 236-8818 19" desktop cases, integrated systems, NORTHERN CALIFORNIA REGIONAL SALES MANAGER Twyla Sulesky [email protected] card cages and components (408) 779-0005 ASIA-PACIFIC SALES ACCOUNT MANAGER Elvi Lee [email protected] EUROPE SALES ACCOUNT MANAGER James Rhoades-Brown [email protected]

ECASTS WWW.OPENSYSTEMSMEDIA.COM Space Rovers PUBLISHER Patrick Hopper [email protected] and Surgical Robots: PRESIDENT Rosemary Kristoff [email protected] System Architecture Lessons EXECUTIVE VICE PRESIDENT John McHale [email protected] from Mars EXECUTIVE VICE PRESIDENT Rich Nass [email protected] May 5 CHIEF TECHNICAL OFFICER Wayne Kristoff 2:00 p.m. EDT ASSISTANT MANAGING EDITOR Lisa Daigle [email protected] SENIOR EDITOR Sally Cole [email protected] Solving Aerospace Tech ASSOCIATE EDITOR Mariana Iriarte [email protected] Development Challenges PICMG EDITORIAL DIRECTOR Joe Pavlat [email protected] June 7 EMBEDDED COMPUTING BRAND DIRECTOR Rich Nass [email protected] 2:00 p.m. EDT EMBEDDED COMPUTING EDITORIAL DIRECTOR Curt Schwaderer [email protected] ecast.opensystemsmedia.com TECHNOLOGY EDITOR Brandon Lewis [email protected] TECHNICAL CONTRIBUTOR Rory Dear [email protected] CREATIVE PROJECTS Chris Rassiccia [email protected] FINANCIAL ASSISTANT Emily Verhoeks [email protected] SUBSCRIPTION MANAGER [email protected]

CORPORATE OFFICE EVENTS 16626 E. Avenue of the Fountains, Ste. 201 • Fountain Hills, AZ 85268 • Tel: (480) 967-5581 XPONENTIAL 2016 SALES AND MARKETING OFFICE 30233 Jefferson • St. Clair Shores, MI 48082 May 2-5 New Orleans, Louisiana REPRINTS www.xponential.org WRIGHT’S MEDIA REPRINT COORDINATOR Wyndell Hamilton [email protected] (281) 419-5725 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 5 Editor’s Foreword By Jerry Gipper, Editorial Director

@VitaTechnology [email protected]

Celebrating VME’s strength and endurance

Embedded Tech Trends 2016 is now in to do so; IOxOS also has an FPGA-based bridge chip that is sold as a stand-alone the books. We had a record number of component and is being used by other VMEbus board suppliers. sponsors and media representatives at the event, which is a business and tech- In 2014 the industry was in a panic that VMEbus as we knew it would end when IBM nology forum focused on the critical and informed IDT that they would no longer build the Tsi148 VMEbus to PCI-X bridge for intelligent embedded systems industry. them, forcing IDT to announce the end-of-life of that popular part. Strong demand for The theme this year was “Houston – We VME incentivized suppliers to look for alternate solutions, from lifetime purchases to have a problem!” All of the presentations custom FPGA implementations. Many are taking the opportunity to make it a VMEbus and associated videos have been posted to PCI Express bus bridge, which is more popular with today’s designs. to the Embedded Tech Trends website at www.embeddedtechtrends.com. The industry lost a giant in January with the passing of Lym Hevle, the founder of the VMEbus International Trade Association (VITA). I was saddened to hear the news. I had Last year was a very busy time at VITA. the fortune of knowing Lym in the early days of VITA and VMEbus. My last contact with Twenty-two new members joined from him was while I was doing research for the 25th anniversary of VMEbus. Read more companies around the world, truly about Lym’s contributions in the Hall of Fame feature. reflecting the international significance of the organization. These memberships I was excited when I got a call from NAVAIR late last year asking if they could attend were driven primarily by the growing a VITA Standards Organization (VSO) meeting to discuss some ideas they had on popularity of VPX and FMC. The activity open architecture platforms. They have been following the work of the U.S. Army’s level is high for standards develop- VICTORY program and have been struggling with many of the same development ment and design-wins for both of these issues. A NAVAIR representative presented the Hardware Open System Technology technologies. (HOST) strategy to VSO meeting attendees. NAVAIR has a vision of creating a hardware technical reference framework for developing embedded computing systems At the same time, we are preparing to through successful development of the HOST strategy to maximize platform and celebrate the 35th anniversary of the system “openness,” modularity, interoperability, scalability, sustainability, and reuse. announcement of VMEbus. Looking The VSO decided to form a study group to continue working on this proposal. Formal back, it is hard to imagine the strength release of a document is imminent. and longevity of VME. I had graduated from college and was just getting my Growing a company in the critical embedded computing industry is extremely chal- feet wet in the world of embedded com- lenging. I spent several years of my career at Motorola leading a small strategy puting when it debuted. Please feel free team tasked with that goal. I am always on the watch for news on acquisitions in our to visit our LinkedIn site to add your own industry. The recent announcement by Mercury Systems to acquire the embedded comments to the conversation. I will be security, RF and microwave, and custom microelectronics businesses from Microsemi pulling comments and stories from the Corporation was especially of interest. Mercury Systems has been active in acquisi- LinkedIn conversation to be published in tions for many years, primarily at a system level. This acquisition takes a different our 35th anniversary feature in the Fall/ slant that I am not quite sure I understand yet. While I have observed semiconductor Winter issue. companies purchase board and system companies over the years, I have never seen a computer system company in this space purchase a semiconductor company. This will New products based on VMEbus con- be a fun acquisition to follow in the coming months. It begs me to ask why someone tinue to be introduced today, as evi- wouldn’t be interested in purchasing the IDT VME chip business? denced by some of my Primetime product selections. News from Curtiss- I extend an invitation for everyone to join in the conversations at the VITA Technologies Wright that they have developed an LinkedIn group (www.linkedin.com/groups/2565867). FPGA-based PCI Express to VME64x bridge chip with a 15-year life-cycle If the rest of 2016 is anything like the first quarter, then this year should be a fun time! commitment is mind-boggling to me I look forward to a great 2016. in this age of rapid technology turn- over! And they were not even the first Jerry Gipper, [email protected]

6 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com

VITA Standards Update By Jerry Gipper

[email protected]

VITA Standards Organization activity updates

The March VITA Standards Organization (VSO) meeting was held in Orlando, Florida. This update is based on the results of that meeting. Contact VITA if you are interested in participating in any of these working groups. Visit the VITA website (www.vita.com) for details on upcoming VSO meetings.

ANSI accreditation Status: ANSI/VITA 47-2005 (R2007) has been opened up for revision to improve Accredited as an American National interoperability, create less reliance on individual supplier ruggedization guidelines, Standards Institute (ANSI) developer and make sure environments are concurrent with new VPX updates. The working and a submitter of Industry Trade group is actively scheduling meetings and working on revisions. Participation is Agreements to the IEC, the VSO pro- encouraged. vides its members with the ability to develop and promote open technology VITA 48.4: VPX REDI: standards. The VSO meets every two Mechanical Speciﬁcation Using Liquid Flow Through (LFT) Applied to VPX months to address embedded bus and Objective: This standard will establish the mechanical design requirements for an board industry standards issues. LFT-cooled electronic VPX module.

VSO study and working group Status: The working group is developing a vibration test plan, as well as designing a activities simplified prototype vibration test module and backplane fixture to further validate Standards within the VSO may be initi- the concept of removing the two outer guide pins. A first draft version of the standard ated through the formation of a study is out for review to establish the content structure, with details filling in as the design group and developed by a working solidifies. The goal is to have testing complete and a draft standard ready for review group. A study group requires the spon- by the end of the year. sorship of one VITA member, and a working group requires sponsorship of VITA 48.8: VPX REDI: at least three VITA members. Mechanical Standard for 3U, 6U Air Flow Through (AFT) Cooling Objective: This standard will develop an AFT standard using VPX connectors without Work in progress need for retainers and uses jackscrews instead of levers. Several working groups have current project work underway; the following Status: The first draft of the standard is under review by the working group. Interested roundup summarizes those projects. parties are invited to join the effort.

VITA 49.2: VITA Radio Transport (VRT) Control Packet Rules ANSI/VITA 42.0: Objective: The VRT standard defines a transport-layer protocol designed to promote XMC Switched Mezzanine Card interoperability between radio frequency receivers and signal processing equip- Base Specification ment in a wide range of applications. The VRT protocol provides a variety of format- Objective: This standard defines a PMC ting options allowing the transport layer to be optimized for each application. The form factor with open-standard switch VITA 49.2 standard specifies the rules governing control packets. fabric interconnects. Status: The working group has developed a draft document for review and discussion. Status: The draft specification has com- Interested parties are invited to join the working group. pleted the ANSI balloting phase, and comments received during the ballot are VITA 57.4: FMC+ under review. Objective: The goal of this project is to develop a next-generation specification calling for a new set of connectors to support higher-speed serial interfaces. ANSI/VITA 47: Environments, Design and Construction, Safety, Status: The working group ballot has passed, and comments are under review before and Quality for Plug-in Units the document will be submitted to ANSI ballot. Objective: Supplying vendors’ certifica- tion of COTS plug-in units to this standard ANSI/VITA 65: OpenVPX Architectural Framework for VPX will facilitate the cost-effective integra- Objective: The OpenVPX architectural framework specification is a living document tion of these items in larger systems. that is continuously being updated with new profile information and corrections.

8 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com Status: The working group is reviewing necessary to take this specification to clocking, keying, and nomenclature pro- ANSI accredited status. Several addi- posals for the next release. tional dot specifications have been introduced to expand the capability of VNX. VITA 66: Optical Interconnect on Interested parties are invited to join the VPX – Half Width MT working group. Objective: The VITA 66 base standard defines physical features of a stand- VITA 76: alone compliant blind mate optical High Performance Cable – interconnect for use in VPX systems. This Ruggedized 10 Gbaud Bulkhead standard defines a half width MT style Connector for Cu and AOC Cables contact variant. Objective: Describe the copper interface Build your own of a new generation of ruggedized cir- Status: VITA 66.4 has completed the cular connectors with a MIL-DTL-38999L VPX system ! ANSI public review ballot. The working series III shell. INTERFACE CONCEPT product range of Sin- group is reviewing comments. gle Board Computers, FPGA boards, ADC/ Status: ANSI/VITA 76.0-2016 High Per- DAC FMC and Graphic boards are ideal to VITA 67.3: VPX: formance Cable – Ruggedized 10 Gbaud devise a complete VPX system for compute Coaxial Interconnect, 6U, Bulkhead Connector for Cu and AOC intensive and image processing applications (radar, electronic warfare, electro Four Position SMPM Configuration Cables has been ratified by ANSI. The optical and IR, visualization systems) Objective: This specification details the standard is available for download by configuration and interconnect within VITA members and is posted at the VITA the structure of VITA 67.0, enabling a 6U Store for purchase by the general public. ® TM VPX interface containing multi-position Intel Core i7 SBC blind mate analog connectors with up to VITA 78.1: SpaceVPX Lite Systems four SMPM contacts. Objective: This document leverages the work done on ANSI/VITA 78 to create Status: The working group has com- a specification with an emphasis on 3U pleted working group balloting and is module implementations. The most sig- • Two CorCoreTM i7 Processors (Dual / Quad Core) addressing the open comments. nificant change from SpaceVPX is to shift • One Ethernet switch, XMC slot... the distribution of utility signals from • One KintexTM 7 FPGA & FMC site VITA 68: VPX: Compliance Channel the SpaceUM to the System Controller Objective: This standard defines a VPX to allow a radial distribution of supply Virtex®-7 FPGA Boards compliance channel including common power to up to eight payload modules. backplane performance criteria required to support multiple fabric types across a Status: The working group has developed range of defined baud rates. This allows a draft document of the specification. backplane developers to design a backplane that supports required Bit Error VITA 84: Hardware Open System Rates (BER) for multiple fabric types. Technology (HOST) Study Group • Two Virtex®-7 690T & FMC sites TM This also allows module developers to Objective: This is a newly formed study • One Freescale QorIQ T1042 (or T2081) design plug-in modules that are interop- group with the vision of creating a hard- erable with other modules when used ware technical reference framework for Graphic Boards with a compliant backplane. developing embedded computing systems through successful development of Status: The working group has approved an overarching HOST strategy to maxi- moving the specification to “VITA mize platform and system “openness,” Draft Standard for Trial Use” status. modularity, interoperability, scalability, Specifications are available for down- sustainability, and reuse. • One AMD RadeonTM E8860 load by VITA members and are posted • One KintexTM-7 325T FPGA • Support for DP, HDMI, VGA, Stanag3350, at the VITA Store for purchase by the Status: The study group was kicked off Arinc8181... general public. in February by NAVAIR. The first public • One PMC/XMC site release of HOST draft specification is VITA 74: VNX awaiting approval. Objective: VNX describes a rugged small form factor subsystem intended to Copies of all standards reaching ANSI be rugged for deployed environments. recognition are available from the VITA website. For a more complete list of Status: The working group has started VITA standards and their status, go to www.interfaceconcept.com +33 (0)2 98 57 30 30 several activities to complete the work www.vita.com/Standards. www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 9

IC-Jan15-exe.indd 1 16/01/2015 16:37 MAIN FEATURE

FMC+ standard propels embedded design to new heights

By Jeremy Banks and Jim Everett

The updated FPGA Mezzanine Card (FMC+) speciﬁcation has been developed and reﬁned over the past year, promising unparalleled I/O density and backward compatibility. The VITA 57.4 working group has approved the spec and will present it for ANSI balloting in early 2016. The following article takes a closer look at this important new standard to see its implications for advanced embedded design.

A new mezzanine card standard called mezzanine cards can be easily changed. For system designers, this means both con- FMC+, an important development for figuration flexibility and an easier path to technology upgrades. However, this flexibility embedded computing designs using usually comes at the cost of functionality due to either connectivity issues or the extra FPGAs and high-speed I/O, will extend real estate needed to fit on the board. the total number of gigabit transceivers (GTs) in a card from 10 to 32 and For FPGAs, the primary open standard is ANSI/VITA 57.1, otherwise known as the increase the maximum data rate from FPGA Mezzanine Card (FMC) standard. A new version dubbed FMC+ (or, more for- 10 Gbps to 28 Gbps while maintaining mally, VITA 57.4) extends the capabilities of the current FMC standard with a major backward compatibility with the current enhancement to gigabit serial interface functionality. FMC standard. FMC+ addresses many of the drawbacks of mezzanine-based I/O compared to mono- These capabilities mesh nicely with lithic solutions, simultaneously delivering both flexibility and performance. At the new devices such as those using the same time, the FMC+ standard stays true to the FMC history and its installed base by JESD204B serial interface standard, supporting backward compatibility. as well as 10G and 40G fiber optics and high-speed serial memory. FMC+ The FMC standard defines a small-format mezzanine card, similar in width and height addresses the most challenging I/O to the long-established XMCs or PMCs, but about half the length. This means FMCs requirements, offering developers the have less component real estate than open-standard formats. However, FMCs do best of two worlds: the flexibility of a not need bus interfaces such as PCI-X, which often take up a considerable amount mezzanine card with the I/O density of of board real estate. Instead, FMCs have direct I/O to the host FPGA, with simplified a monolithic design. power supply requirements. This means that despite their size, FMCs could have more I/O capacity than their XMC counterparts. As with the PMC and XMC specifications, The mezzanine card advantage FMC and FMC+ define options for both air and conduction cooling, thereby serving Mezzanine cards are an effective and both benign and rugged applications in commercial and defense markets. widely used way to add specialized functions to an embedded system. Because The anatomy of the FMC specification is simple. The standard allows for up to they attach to a base or carrier card, rather 160 single-ended or 80 differential parallel I/O signals for high-pin-count (HPC) than plugging directly into a backplane, designs or half that number for low-pin-count (LPC) variants. Up to 10 full-duplex

10 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com GT connections are specified. The GTs are useful for fiber optics or other serial Parallel interface JESD204B Serial interfaces. In addition, the FMC speci- 2x 2 GSps ADC 2x 2 GSps ADC fication defines key clock signals. All of this I/O is optional, though most hosts now support the full connectivity. 10 mm x 10 mm The FMC standard also defines a mix of 27 mm x 27 mm power inputs, though the host supplies the primary power supply as defined Figure 1 | Effect of package shrink on FMC through JESD204B by the mezzanine. This approach works › by partially powering up the mezzanine such that the host can interrogate 50 Gbps throughput range. This functionality results from a trade-off between physical the FMC, which responds by defining a package sizes and available connectivity to the host FPGA. voltage range for the VADJ. Assuming the host can provide this range, then In addition to the parallel connections, the FMC specification supports up to 10 full- all should be well. Not having the pri- duplex high-speed serial (GT) links. mary regulation on the mezzanine saves space and reduces mezzanine power These interfaces are useful for such functionality as fiber-optic I/O, Ethernet, emerging dissipation. technologies like Hybrid Memory Cube (HMC) and MoSys’ Bandwidth Engine, and newer-generation analog I/O devices that use the JESD204B interface. FMCs for analog I/O Designers can use FMCs for any function Enter JESD204B that you might want to connect to an Although the JESD204 serial interface standard, currently at revision “B,” has been FPGA, such as digital I/O, fiber optics, around for a while, only recently has it has gained wider market penetration and control interfaces, memory, or additional become the serial interface of choice for newer generations of high-sampling data processing. But analog I/O is the most converters. This wide adoption has been stoked by the telecommunications industry’s common use for FMC technology. The thirst for ever-smaller, lower-power, and lower-cost devices. FMC specification affords a great deal of scope for fast, high-resolution I/O, As mentioned earlier, a dual-channel 2 GSps, 12-bit ADC with a parallel interface but there are still trade-offs, especially requires a large number of I/O signals. This requirement directly impacts the package with high-speed parts using parallel size, in this case mandating a 292-pin package measuring roughly 27 mm x 27 mm interfaces. (though newer-generation pin geometry could shrink the package size to something less than 20 mm x 20 mm). For example, Texas Instruments’ ADC12D2000RF dual-channel, 2 GSps A JESD204B-connected equivalent device can be provided in a 68-pin, 10 mm x 12-bit analog-to-digital converters 10 mm package with reduced power. This dramatic reduction in package size marries (ADCs) use a 1:4 multiplexed bus inter- well with evolving FPGAs, which are providing more GT links at higher and higher face, so the bus speed is not too fast for speeds. Figure 1 illustrates an example of package size and FMC/FMC+ board size. the host FPGA. The digital data interface alone requires 96 signals (48 LVDS Typical high-speed ADCs and digital-to-analog converters (DACs) using the JESD204B pairs). For a device of this class, FMC interface have between one and eight GT links operating at 3 Gbps to 12 Gbps each, can support only one of these ADCs, depending on the data throughput required based on sample rate, resolution, and even if there is sufficient space for more, number of analog I/O channels. because it is limited to 160 signals. Lower-resolution devices, even at higher The FMC specification defines a relatively small mezzanine card, but with the emer- speeds such as those with 8-bit data gence of JESD204B devices, there is room to fit more parts onto the available real paths, can allow more channels even estate. The maximum of 10 GT links defined by the FMC specification is a useful quan- with the increased requirements of the tity; even this limited number of GT links provides 80 Gbps or more of throughput front-end analog coupling of the baluns while using a fraction of the pins otherwise required for parallel I/O. or amplifiers, clocking, and the like. The emergence of serially connected I/O devices, not just those using JESD204B, The FMC specification starts to run out does have drawbacks for some application segments in electronic warfare, such as of steam with analog interfaces deliv- digital radio frequency memory (DRFM). Serial interfaces invariably introduce addi- ering more than 8 bits of resolution at tional latency due to longer data pipelines. For DRFM applications, latency for data-in around 5 GSps or 6 GSps (throughputs to data-out is a fundamental performance parameter. Although latency is likely to of > 50 Gbps) using parallel interfaces. vary widely between serially connected devices, new generations of devices will push From a market perspective, leading data through the pipelines faster and faster, with some promising the ability to tune FMCs based on channel density, speed, the depth of the pipeline. It remains to be seen how much of an improvement is to and resolution are in the 25 Gbps to be realized. www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 11 MAIN FEATURE

Some standard ADC devices sampling a separate connector, referred to as an HSPCe (HSPC being the main connector). at > 1 GSps today have latency below Table 1 summarizes FMC and FMC+ connectivity. 100 nanoseconds. Other applications can tolerate this latency or do not care Multiple independent signal integrity teams characterized and validated the higher about it, including software-defined 28 Gbps data rate. The maximum full-duplex throughput can now exceed 900 Gbps in radio (SDR), radar warning receivers, each direction when the parallel interface is included. See Figure 2 for an outline of the and other signals intelligence (SIGINT) net throughputs that can be expected for digitizer solutions supporting the different segments. These applications gain large capabilities of FMC and FMC+. advantages by using a new generation of RF ADCs and DACs, a technology Designers can use the increased throughput enabled by FMC+ to take advantage of driven by the mass-market telecommu- new devices that offer huge I/O bandwidth. There will still be trade-offs, such as how nications infrastructure. many devices can fit on the mezzanine’s real estate budget, but for a moderate number of channels, the realizable throughput is a huge leap over today’s FMC specification. Outside the FPGA community, newer DSP devices are also starting to adopt Next-generation ADCs and DACs JESD204B. However, FPGAs are likely In the next few years, it is reasonable to expect high-resolution ADCs and DACs to to remain the stronghold in taking full break through the 10 GSps barrier to support very wideband communications with advantage of the capabilities of wide- direct RF samplings for L-, S-, and even C-band frequencies. Below 10 GSps, con- band analog I/O devices. That’s because verters are emerging with 12-, 14-, and even 16-bit resolutions, with some supporting FPGAs can deal with vast data volumes multiple channels. The majority of these devices will be using JESD204B (or a newer with better parallelization. revision) signaling with 12 Gbps channels until newer generations inevitably boost this speed even further. These fast-moving advances are fueled by the telecommunica- The evolution of FMC+ tions industry, but the military community can take advantage of them to meet size, To move FMC to the next level, the weight, power, and cost (SWAP-C) requirements. VITA 57.4 working group has created a specification with an increased number Connector-limited of GT links operating at increased speed. 8 FMC+ maintains full FMC backward compatibility by adding to the FMC connector’s outer columns for the addi- 6 tional signals and not changing any of Channels the board profiles or mechanics. 4

The additional rows will be part of an enhanced connector that will minimize 2 any impact on available real estate. The FMC+ specification increases the 2 4 121086 14 16 18 20 22 24 maximum number of available GT links from 10 to 24, with the option of Sample rate per channel (GSps) adding another eight links, for a total of Figure 2 | FMC versus FMC+ digitizer throughput capability 32 full duplex. The additional links use ›

Function FMC FMC+ FMC+ with HSPCe extension

Maximum # parallel I/O 80 diff/160 single-ended 80 diff/160 single-ended 80 diff/160 single-ended

Clocks 4 4 4

Maximum # GTs 10 24 32

GT clocks 2 6 8

Miscellaneous JTAG, SYNC, power good, JTAG, SYNC, power good, JTAG, SYNC, power good, geographic address geographic address geographic address

Power supplies VADJ* (4 pins), 3 V3 (4 pins), VADJ* (4 pins), 3 V3 (8 pins), VADJ* (4 pins), 3 V3 (8 pins), 12 V (2 pins), 3 V3 Aux (1 pin) 12 V (4 pins), 3 V3 Aux (1 pin) 12 V (4 pins), 3 V3 Aux (1 pin)

* VADJ: mezzanine deﬁned for voltage level, but provided by host › Table 1 | Summary of FMC and FMC+ connectivity

12 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com is likely where the higher speeds sup- Jeremy Banks is a product manager ported by FMC+ will first be realized. for sensor and I/O processing at Bandwidths of 28 Gbps per fiber will Curtiss-Wright. He has been involved take the throughputs quickly past 100G in the defense embedded computing and 400G speeds on a single mezzanine. industry for more than 25 years holding Optical throughput of 100G is emerging positions in engineering design, today on the current FMC format. marketing, and product management across DSP, multiprocessing, RF I/O, Another emerging area suitable for SBC, and FPGA disciplines. Jeremy FMC+ is serial memory such as HMC and holds a BSc (Hons) in Electronic Bandwidth Engine. These novel devices and Electrical Engineering from the › Figure 3 | Xilinx KCU114 represent an entirely new category of University of Surrey. He can be reached high-performance memory, delivering at [email protected]. Other advantages and uses unprecedented system performance and of FMC+ bandwidth by utilizing GT connectivity. Jim Everett is product marketing Although FMC+, like FMC, will prob- manager for Virtex evaluation, ably be dominated by ADC, DAC, and Alive and kicking GT characterization, and FMC/FMC+ transceiver products, the increased GT A new generation of the FMC specifica- boards and kits at Xilinx. His 35-year density provided by FPGAs makes it tion has been introduced and is adapting career in electronics spans many useful for other functions. Two functions to new technology driven by serial con- years in design, sales, and marketing of note are fiber optics and new serial nected devices. Key players in the FMC of FPGAs. Jim graduated from memories. industry have already begun adopting Michigan State University with a this specification. Figure 3 shows the first BSEE degree. He can be reached As with JESD204B, there are require- Xilinx demonstration board featuring at [email protected]. ments for faster, denser fiber optics. FMC+, the KCU114. The FMC standard, Curtiss-Wright Those based on fiber-optic ribbon cables through its new incarnation FMC+, is www.curtisswright.com offer the smallest parts. Because the alive and kicking and is prepared for the › FMC+ footprint readily supports 24 full- next generation of high-performance, Xilinx duplex fiber-optic links, this application FPGA-driven applications. www.xilinx.com

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VPX • AdvancedTCA • VME • CompactPCI • Custom (800) 747-5972 • [email protected] • www.lcrembeddedsystems.com www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 13 TECHNOLOGY FEATURE

Very high-speed sampling and serial ADCs in embedded systems

By Thierry Wastiaux

Latest-generation active electronically scaled array (AESA) radar systems can have thousands of TX/RX modules. High bandwidth is needed to connect each array element data converter to the FPGAs that process incoming and generate outgoing data streams. New software-defined radio systems use advanced reconfigurable modulation schemes that increase channel bandwidths and deliver unprecedented wireless data rates. To increase the performance of software radio and electronic warfare systems, it has become critical to use efficient, low-power, low-pin-count, FPGA-connected converter interfaces.

As the performances of analog-to-digital number of trace routes and easier- to baseband. The filtering stages allow converters (ADCs) are quickly improving, to-route board designs. The links use filtering the unwanted part of the spec- the classical approach of transmitting 8b/10b encoding, which incorporates trum. Gain stages allow compensating for samples through low-voltage differential an embedded clock, enabling further mixer and NCO losses. And complex-to- signaling (LVDS) reaches its limits. LVDS pin-count reduction by removing the real conversion enables presenting the lanes connected to last-generation FPGA necessity for routing an additional clock final real signal of interest. I/O are limited to around 1.4 Gbps. As an line and the associated complexity of example, when targeting a four-channel aligning an additional clock signal with These down-converter features dramati- FPGA Mezzanine Card (FMC) with 12-bit the transmitted data at high data rates. cally reduce the complexity of radio and analog to digital sampling at 2.6 GSps, a radar systems, using part of the FPGA minimum of 96 LVDS lanes is required for In addition, trace-to-trace tolerances resources to implement these functions. data only, without taking into account are relaxed relative to synchronous sam- The FPGA capacity is fully used for the the clock and service signals. This is not pling parallel LVDS signals. All these important signal processing part as possible on standard VITA 57.1 connec- simplifications in the design eventu- beamforming for radars, for instance. tors, and it takes too much I/O resource ally lead to cost reduction. Moreover, on the FPGA. this allows reducing the size of the Deterministic latency ADC components, as the output pins It is important to know the timing rela- The insatiable demand for data sampling required for FPGA connection are less tionship between the sampled signal thus has led to the need for the stan- numerous using the low differential and its digital representation. This dardization body JEDEC to introduce swing DC-balanced high-speed current timing relationship is affected by the the JESD204 standard for a high-speed mode logic (CML) standard. Thus, it can latency of the converter, which is defined serial link between data converters and further increase the number of compo- for an ADC as the number of clock cycles logic devices. Serial link data rates have nents on the small FMC footprint. between the instant of the sampling been pushed up to 12.5 Gbps in the last edge of the input signal until the time revision “B” of the standard, released in It must be noted that the last generation that its digital representation is present 2011 for higher-bandwidth requirements. of serial ADCs implements digital down- at the converter’s outputs. This latency This revision also includes provisions for converters with variable decimation is typically in the range of several nano- “deterministic latency” of data transfers. ratios that provide filtering and reduce seconds in classical parallel ADCs. In the output data rate. They might include JESD204B, this latency is increased by Simplification of design frequency translation stages (numerical the process of serialization even if the Compared to the classical parallel controlled oscillators), finite impulse speed of the sampling data transmission approach, the improvements brought by response (FIR) filtering stages, gain lanes is much higher. This latency can JESD204 are many. By moving from high- stages, and complex-to-real conversion typically be several tens of nanoseconds. pin-count, low-speed to low-pin-count, stages. Numerically controlled oscillators high-speed serial interface, the overall (NCOs) and digital mixers allow tuning JESD204B-compliant receivers are out- system design is simplified with a smaller the center of the bandwidth of interest fitted with an elastic buffer that is used

14 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com to compensate for skew across serializer/ The FMC standard defines a small format mezzanine, similar in width and height deserializer (SERDES) lanes, which sim- to XMCs or PMCs, but around half the length. As real estate is limited, some fea- plifies board layout. This elastic buffer tures have been included in the standard. First, to save space, its primary power is stores the data until the data from the supplied by the FPGA carrier board. During the power-up sequence, the host inter- slowest lane arrives. It then releases the rogates the FMC as to what the feeding voltage must be. In addition, FMCs directly data from all lanes simultaneously for connect the I/O devices on the mezzanine to the host FPGA via a high-speed, high- digital processing. This skew manage- density connector as if the device was on the host itself, leading to logic reduction ment is possible because the data clock and saved space. is embedded in the serial data stream. The first generation of the FMC standard allows up to 160 for high-pin-count (HPC) While the JESD204B standard has sim- or 80 for low-pin-count (LPC) “parallel” I/O signals and up to 10 full-duplex high- plified multichannel synchronization speed serial connections (along with some clocks). Figures 1 and 2 shown on page 16 by using deterministic latency, minimal depict an Interface Concept ADC FMC, the IC-ADC-FMC, which can be plugged on latency is needed in some applications a Virtex-7 FPGA carrier board, the IC-FEP-VPX3c, featuring eight high-speed trans- such as electronic warfare (EW) and radar ceivers in front of the mezzanine’s high-speed serial (HSS) links. applications where actions are required immediately after detection. For these applications, the LVDS interface should still be considered, as the JESD204B- compliant data converter’s delay in serial- izing the data is omitted. However, applications such as radar warning receivers (RWR) or COMINT that are receiver-only applications tolerate the latency brought on by the JESD204B serialization. These applications thus can benefit from the last generations of ADCs driven by the mass market of telecommunication infrastructure, allowing very high-speed sampling and reducing the complexity of the analog part of the system.

FPGA vendors have developed fully compliant JESD204B intellectual property (IP) that can be implemented in their products for communication with the serial ADCs. For example, the JESD204B Xilinx IP supports 256 bytes per frame and 32 frames per multiframe. It can be conﬁgured to support up to 32 lanes.

Flexible design follows the fast moving market of ADCs In combining the technologies available on ADCs including the new JESD204B standard and FPGAs, EW system architects can dramatically improve data sample processing. FMC (VITA 57 standard), promoted by the VITA FMC Marketing Alliance, allows high data throughput and very low latency response between an ADC or a digital-to-analog converter (DAC) FMC and the FPGA, simplification of the design, and above all, the cost-efficient ability to simply retarget an FPGA carrier card design. All that is required is swapping out the FMC module and adjusting the FPGA firmware. That is why the standard has become the open standard mezzanine of choice. www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 15 TECHNOLOGY FEATURE

At the inception of the FMC standard, the HPC speciﬁcation appeared as satisfactory in terms of the number of allowed I/O. The evolution of ADC technology, as well as the increasingly demanding requirements of EW system designers, has highlighted the need to go beyond this ﬁrst version of the FMC standard.

An effort to define suitable FMC enhancements is now underway within the VITA 57.4 working group. The focus is on creating a standard with an increased number of HSS links (increased from 10 to 24) operating at increased speed while keeping the existing connector pinout for I/O. The HSS link throughput is targeted at up to 28 Gbps, extending the aggregate bandwidth to the huge level of 672 Gbps, to which the Figure 1 | IC-ADC-FMCc quad 12-bit 1300 MSPS FMC traditional LVDS links can be added. Backward compatibility is ensured by adding to › the FMC connector’s outer columns for additional signals without changing the form factor, real estate, or mechanics (mounting holes, thermal interface, and so on). The approval of this new standard is currently in process.

Layer 2/3 Enterprise Non-Blocking GigE Smart Switch for Demanding SWAP-C Environments TM NANOSWITCH Figure 2 | IC-FEP-VPX3c Virtex-7

The Themis NanoSWITCH is a Size, Weight, Power and Cost (SWAP-C) optimized › carrier with one VITA 57.1 FMC slot rugged multi-layer Gigabit Ethernet switch with an embedded x86 PC. NanoSWITCH brings enterprise level layer 2/3 switching into demanding environments found in The future of converter military ground, air and sea vehicles. digital interfaces The industry is requiring better performing ADCs, leading to huge sample data ﬂows. The big push of the ADC industry has led to the development of the JESD204B standard. Looking to the future, it is clear that JESD204 is poised to become the industry choice for the digital interface to converters. Each revision has answered the demands for improvements on its implementation and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performances increase, the JESD204 standard should be able to Applications Environmental adapt to meet the new design requirements necessary. • Vehicle network switching • IP67 environmentally sealed for water, • Distributed architecture vehicle controller dust, and salt fog) • VICTORY compliant switch, router, timing, • Sealed MIL connectors Thierry Wastiaux is senior VP of and control • Operating temperature: -40°C to 71°C • Shock: 50g @25ms sales for Interface Concept. He has • Shared processing and peripheral • Vibration: 5G RMS.10Hz to 2KHz 25 years of experience in the telecom communications • Status LED blanking control and embedded systems market. Prior to joining Interface Concept, he was www.themis.com/nanoswitch responsible for the operations of the Mobile Communication Group and the Wireless Transmission Business Unit at Alcatel-Lucent. He holds an MSc from Ecole Polytechnique France.

47200 Bayside Parkway, Fremont CA 94538 | 510-252-0870 | www.themis.com Interface Concept

©2016 Themis Computer. All rights reserved. Themis and the Themis logo are trademarks or registered [email protected] trademarks of Themis Computer. All other trademarks are the property of their respective owners. › www.interfaceconcept.com

16 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com TECHNOLOGY FEATURE

Modular Open Radio Frequency Architecture boot camp

By Jerry Gipper

Designers creating the next generation of embedded defense systems face several challenges getting their solutions off the ground. The newly launched Modular Open Radio Frequency Architecture (MORA) aims to enable the development of true open standards-based radio frequency and microwave modules and small form factor subsystem designs to reduce costs, foster commonality, and enable new communications capabilities.

Electronics are a key part of many defense platforms and performance and efficiency through reduced cable loss. Use of are becoming more important as the content percentage is software-defined radio technologies allows the same hardware growing. However, the purchasing influence of defense pro- to run different waveform application to support a multitude of grams has become a smaller percentage of the overall world- missions, including EW and communications. wide electronics industry. Complicating the issue is the demand to get new solutions to deployment in much shorter time frames CERDEC is defining a converged open architecture that will to take advantage of the latest technology. This increase in reli- provide open interfaces to enable rapid insertion of new capa- ance on electronics, reduction in purchasing power, and rapid bilities, interoperability, and a reduced SWaP footprint. shortening of time to deployment have created a challenging dynamic for system architects responsible for the design of The MORA architecture, which extends the U.S. Army’s next-generation defense platforms. VICTORY architecture, will:

Over the years, many initiatives have emerged to drive stan- › Enable sharing of hardware and software components dards for open, flexible platforms, with the most recent among C4ISR/EW capabilities. example being the U.S. Army’s VICTORY program. Recently, › Allow technology refresh to keep pace with threats while the U.S. Army’s Communications-Electronics Research, improving reliability and robustness. Development, and Engineering Center (CERDEC) launched a › Support current and future interoperability requirements new initiative, the Modular Open Radio Frequency Architecture and facilitate transition planning. (MORA), which will enable the development of true open › Permit capabilities that are innovative but unplanned to be standards-based RF and microwave modules and small form rapidly implemented for “future-proofing.” factor subsystem designs that address the size, weight, and › Reduce developmental and acquisition costs through power consumption (SWaP) constraints of today’s ground greater commercial competition. vehicles. MORA is intended to leverage the work done under the VICTORY initiative by adding consideration for RF modules Wide embedded industry support of the modular and scalable and subsystems. MORA architecture will help drive the network-based connectivity of sensors and peripherals on ground vehicles and help About the MORA architecture speed the deployment of new C4ISR/EW capabilities. Current command, control, communications, computers, intelligence, surveillance, and reconnaissance (C4ISR) and electronic MORA is based on the popular OpenVPX module and back- warfare (EW) systems use single-purpose hardware and plane open-standard framework managed by VITA members. software that aren’t shared beyond their defined functions MORA-based hardware and software solutions developed and compete for limited resources on the platform. MORA by VITA member companies will enable enhanced C4ISR/EW decomposes radio systems into high-level components that capabilities to exist within the SWaP constraints of platforms enable sharing of hardware such as amplifiers and antennas. and provide subsystem commonality across the vehicle fleet to Low power distribution of RF signals improves overall system reduce life-cycle costs. www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 17 TECHNOLOGY FEATURE

“One thing we know about the future is that we don’t know to define common standards, a clear picture of which interfaces what the future holds,” said Ben Peddicord, chief of CERDEC are desired must be established across the board. Intelligence and Information Warfare Directorate’s Intel Technology and Architecture Branch. “The interfaces that have “We’ve never been able to tell industry partners exactly been exposed to MORA were chosen based on an analysis of what we want because we never understood standards well the capabilities we’ve wanted to field over the past 15 years.” enough to steer their efforts toward our benefit,” Peddicord said. “Now we have built up enough expertise to actively Compared to a traditional radio solution, MORA provides contribute to standards.” Peddicord presented on overview the system integrator with greater flexibility when addressing of MORA to the audience at Embedded Tech Trends 2015 technical challenges and the ability to insert third-party (www.embeddedtechtrends.com). Figure 1 illustrates how capabilities. MORA extends the VICTORY architecture.

According to Peddicord, nearly all military platforms – to include MORA payoffs include hardware reuse and pooling, rapid soldiers – have RF devices on them, making MORA an impor- third-party technology insertion, reduced dependence on tant element of hardware and software convergence because proprietary hardware and software, and the ability to improve of its ability to share hardware assets across the platform. “It’s compatibility and/or interoperability. The real catch, however, hard to get meaningful improvements, ﬂexibility, and SWaP has been ensuring that industry would build to MORA stan- reduction if you don’t include RF components,” Peddicord said. dards, said Peddicord.

With a continued emphasis on open systems architecture, “Without industry support, it won’t work. If government pro- CERDEC became a sponsor member of VITA, an international grams ask for it, then industry will support, but government is non-proﬁt organization that has championed open system cautious to put out requirements for a standard not supported architectures since 1982. by industry,” he said.

Using common standards ultimately saves money and time, both To deﬁne these standards, CERDEC has worked closely with of which are key components from the Better Buying Power 3.0 industry through VITA, conferences, and third-party vendors, initiative, Peddicord said. The challenge, however, is that in order as well as collaborated with companies that build according to

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18 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com MORA speciﬁcations. CERDEC is being assisted by MIT Lincoln Radioheads VICTORY Shared Laboratory, Georgia Tech Research Institute, Johns Hopkins (Antenna + Processing Unit University Applied Physics Laboratory, and other strategic PA) research partners that are familiar with OpenVPX. VICTORY Data Bus (GbE) “It’s important to have a third party build against the spec because it always makes sense to the person who wrote it, MORA High-Speed Bus so it’s important that someone who didn’t write it builds it to ensure it’s working,” Peddicord said. Power Bus

RF Cables “We believe that MORA provides a path for using true industry open standards to develop rugged COTS solutions to meet [defense] critical requirements,” said Lynn Bamford, senior Software-Defined RF Distribution VP and general manager of the Defense Solutions Division at Radio Device Curtiss-Wright. Several other VPX technology suppliers stand ready to develop products in support of MORA. Figure 1 | VICTORY/MORA relationship The future of RF distribution › The ANSI/VITA 49 VITA Radio Transport (VRT) standard defines cables, improves resistance to EMI, and simplifies cabling in a transport-layer protocol designed to promote interoperability chassis and platforms, all key advantages to MORA. Work con- between RF receivers and signal processing equipment in a tinues on investigating the performance of VITA 49. wide range of applications. The VRT protocol provides a variety of formatting options allowing the transport layer to be opti- Toward the end of 2016, CERDEC is planning a vehicle dem- mized for each application. CERDEC is also evaluating VITA 49 onstration of hardware/software convergence using MORA. as an alternate form of RF distribution within MORA. Specifications for MORA can only be released to U.S. government agencies and their contractors. The current version of VRT potentially eliminates the need for an RF distribution the specification is available through the VICTORY portal at device and RF cables, minimizes power loss due to coaxial http://victory-standards.org.

www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 19 SPECIAL FEATURE

VITA Technology Hall of Fame 2016

Lyman Hevle was the founding executive director of the VMEbus International Trade Association (VITA). He held that role from its inception in 1984 until 1993. During his career Lym was focused on the business and market growth of VMEbus. He passed away in January 2016, and his legacy will live on in the industry. Lym’s own words best describe his involvement with VMEbus and how he came to be the founding executive director of VITA. Lyman Hevle The following discourse is an excerpt from his autobiography.

Genesis and development of business. Our plan was to furnish the systems hardware and systems software, limited VMEbus to operating system and languages. We had already lined up independent established From Lym Hevle’s autobiography distributors who would handle sales and service and develop user application soft- Like any successful human endeavor, ware. A marriage made in heaven. there are many who claim fatherhood. There were actually many true and Glenn Iaggi (our boss), Dick Ruth, and I made a triumphant trip to Shaumberg to excite some untrue claimants. Some of these the brass with our creativity. All the brass was there. About halfway into our presenta- came aboard the VMEbus train several tions, Motorola President John Mitchell abruptly stopped us and told us we were com- years after it had left the station. They puter retreads who would diminish his base business profits. He strongly stated that did, however, fulfill a valuable role as Motorola would never be in the computer business. We protested that Motorola was VMEbus pioneers. The actual birth of already in the revolutionary computer business by virtue of the microprocessors. When VMEbus was painful, though exciting. I I asked him if there was no place for creative people who could lead Motorola into the will relate my role as accurately as I can, future, he said there wasn’t. We packed up our papers in complete defeat and left the with no purpose of denigrating anyone boardroom. We really didn’t know if we had been fired or not. We weren’t. Bob Galvin else’s memory or participation. would visit us quite often for our “Moments of Madness” looks into the future, and told us he understood us and appreciated our forward thinking. We partially satisfied It starts with the [Motorola] 6800 micro- our longings by offering our Exercisor as an end-use system in the process automation processor and the Exercisor. In those market. It wasn’t a good fit and our success was modest at best. days every manufacturer designed their own non-standard boards and guarded The 68000 series came along, and our expansion desires were rekindled. Our them zealously. The engineers who Microsystems engineers designed the EXORmacs development system. Max Loesel established the Exercisor board param- (our Europe Manager) made me aware of the European developing standard called eters did a good job with a fairly small Eurocards. It came in single, double, and triple widths. I argued for this approach. I lost board. When we started Microsystems, because of strongly stated engineering requirements and distaste for anything European we inherited this head start. We imme- at that time. Another reason was that engineers from the large computer businesses diately saw that the same boards that we were used to big boards. There was no way we could sell these big VERSAbus modules would develop for the Exercisor could fit in the process automation market. Max, however, didn’t give up. His engineers retro- nicely in a commercial computer system fitted the VERSAbus onto double Eurocards in his Munich “skunk works.” He kept me business. We gleefully developed a up-to-date and even took me to see some of his prospective customers. I was hooked, prodigious 5-year plan to launch this and the result was called Versa Module Europe. Its acronym became “VME.”

20 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com There was a certain NIH feeling in into Microsystems who I felt were nice guys but incompetent to lead Microsystems Phoenix and a little “we/they” animosity. to any creative new heights. They had zero marketing and/or business acumen. Yes, I was delighted with the VMEbus market I was totally disillusioned with Motorola. I told my new boss that I was going to leave prospects because of not only its size, Motorola but I would stay long enough to produce a comprehensive five-year plan to but also more importantly because it launch VMEbus into the process automation business. This had been my background was a standard that other manufacturers with General Electric. I told him I would do it with Shaumberg Planning cooperation could use. The trick now was to get and management approval. I knew enough from our failures with top management management acceptance and approval. to omit any land mines. For example, I would never mention computer systems, but On a trip to the Shaumberg Corporate rather call them “process controllers.” Planning, I explained that with VMEbus we could catch Intel, whose Multibus The plan was completed, but I felt little understood by the new Microsystems. I left II was quickly gobbling up the market. Motorola and joined Dick Ruth with GEC of England. They were developing a super The next idea was that if we shared the mini-computer and needed some marketing and business planning. A few years later VMEbus with other manufacturers, we I got a call from Jim Gunderson of Microsystems, saying that VMEbus was going would swamp the market with VMEbus nowhere, and did I have any ideas to get it moving? I said I would do an international boards and bury Intel. Sharing a standard study if the three VMEbus principals would foot the bill. They pledged about $300,000 technology was something Intel would and hired me. I listened and made speeches all over the United States and Europe. never consider. Just then John Mitchell I painted an alluring picture of a business that could inure to one billion dollars in five looked in and said these two ideas were years (and it did). The response was a standing ovation in each location. They each stupid. His rationale was: wanted a longer private meeting. This we did, and the results were stunning. They all wanted a piece of a new VMEbus adventure. 1. You have already spent a ton of money developing VERSAbus. The resulting consulting report was easy for me to write because my previously Why spend it again just changing conceived ideas were validated. I presented the report to Motorola, Philips/Signetics, the size? and United Technologies in Las Vegas. All three companies eagerly accepted the 2. You have spent a lot of money formation of an International VMEbus Trade Association … hence VITA was born. The developing the technology. report covered the structure of VITA and how it would operate in detail. Why on earth would you want to give it away? The next step in the report was to hire an executive director. It was decided that each company would produce a candidate. Each candidate would visit each com- I told him the KOA Camp story. Will we pany, which would result in an appointment. Motorola voted for me, but the others settle for 100 percent of a small piece had some reservations. They had two concerns about me. One was that I had been of the pie, or get rich with a smaller an employee of Motorola and might be biased. The other was that I had a reputation percentage of a gigantic pie? He reiter- as an entrepreneur and owned several outside businesses. I told each that I admired ated that computer retreads were dan- Motorola very much, but had left them two years ago with much disappointment. On gerous. He didn’t say no, so I took it as the question of allocation of my time, I said I would write a binding contract to limit my tacit approval. Motorola Microsystems outside activities. I said VITA would be my burning passion, and that if I had nothing embraced the concepts. We sent Jim else, I had integrity. I was hired and started immediately. Gunderson to explore the cooperation concept with Philips/Signetics and The starting point was selling VITA membership in several classifications according to United Technologies [key 68000 sup- the plan. This went extremely well, and we then developed the Compatible Products porters], and they were ecstatic. Thus Directory (CPD), VITA Journal, Mailing Lists, et al. We also published the VMEbus began a series of meetings to deter- specification, as well as a VMEbus technical design manual. We held technical semi- mine which company would build which nars and participated in shows all over the world. We established a very successful boards to share with each other. This VITA office in Europe with brilliant Zoltan Hunor as director. We also had satellite entire group spent a lot of time with offices in Tokyo and Moscow. We were able to get the U.S. Navy to standardize on attorneys to make sure we avoided any VMEbus, then the Army and Air Force. Soon all the world’s military forces followed anti-trust situations. suit. A major accomplishment was the reduction of Intel’s percentage of the market from 95 percent to zero. They eventually discontinued their Multibus II board opera- Philips/Signetics jumped on board and tions. Mission accomplished. I retired in 1995 and have not followed the progress of designed some boards. Time went slowly VITA or the VMEbus since then. VITA was the high point of my professional life, and by with modest results. Management I am eternally grateful to the very many fathers and pioneers of VMEbus. changes were made at the Corporate and Semiconductor levels. Dick Ruth was fired and this troubled me greatly. I was › VITA TECHNOLOGY HALL OF FAME asked if I wanted to be interviewed for Main page: http://opensystemsmedia.com/hall-of-fame/vita-technologies his job and I quickly declined. The new Nomination guidelines and nomination form: http://opensystemsmedia. Microsystems manager knew nothing com/hall-of-fame/vita-technologies/nomination-guidelines of our dream. New blood was inserted www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 21 PRIMETIME CHOICES

VRT protocol engine paves way for the future of signal processing The VITA 49 Radio Transport (VRT) standard defines a transport-layer protocol for data and context packets designed to promote interoperability between radio frequency (RF) receivers and signal processing equipment in a wide range of communication and radar systems. The Pentek Cobalt Model 71664 XMC FPGA module is a 4-channel 200 MHz 16-bit A/D with programmable digital down converter based on the Xilinx Virtex-6 FPGA. Model 71664 is the first Pentek product to include an IP engine for the VRT protocol. “VRT is the future of software-defined radio,” said Paul Mesibov, Pentek’s VP of engineering. “The protocols defined in VRT provide data and context packets that standardize the way information is transported from radio to signal processing equipment.” A front-end A/D converter stage accepts four analog HF or IF inputs on front-panel SSMC connectors, with each transformer coupled to Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The 200 MHz sampling rate handles the needed bandwidth for a wide range of signal processing applications. [Image shows Cobalt Model 71664 on a 3U VPX module, model 53664.] Pentek • www.pentek.com • www.vita-technologies.com/p373439

T2080-based VME SBCs boosts performance at reduced cost Performance, cost, and product longevity are frequently the top buying decisions with SBCs. Curtiss-Wright Defense Solutions’ SVME/DMV-196, its newest Power Architecture (PA) based 6U VME SBC, fits the bill for these requirements. The rugged SBC delivers up to 6x higher performance in a similar power envelope and at a lower price point compared to earlier single- and dual- processor PA VME SBC designs. Highlighting Curtiss-Wright’s commitment to its VME customers, the SVME/DMV-196 is the first in a new family of SBCs designed with the company’s new obsolescence-fighting FPGA-based Helix PCI Express to VME64x interface. To further aid longevity of supply, a key requirement for most rugged embedded defense and aerospace applications, the board’s T2080 processor is backed with NXP Semiconductor’s 15-year life cycle. “This powerful new Power Architecture SBC delivers all the advantages of non-throttled quad-core processing and AltiVec while easing technology insertion for customers using a previous generation of Curtiss-Wright products,” said Lynn Bamford, senior VP and general manager of the Defense Solutions division. Curtiss-Wright Defense Solutions • www.curtisswrightds.com • www.vita-technologies.com/p373440

Broad-bandwidth OpenVPX processor blade opens processing possibilities “Ensemble LDS6526 processing blades are the highest-performing sensor processing blades available in the embedded industry today, with a maximum theoretical processing capability of 576 single-precision GFLOPS supported by an enhanced sensor I/O bandwidth of 5 GBps per channel. These OpenVPX 6U blades are opening the door to a host of new possibilities for sensor chain architects,” said Shaun McQuaid, director of product management at Mercury Systems’ Embedded Products Group. The Ensemble LDS6526 leverages Mercury’s fourth generation of size, weight, and power (SWaP)-efficient packaging technology to securely house the Arria 10 FPGA and Intel Xeon Processor D-1500 system-on-chip (SoC) devices for reliable deployment right to the tactical edge. The Ensemble LDS6526 secures and reliably cools commercial technology to produce a dense, powerful combination of server-class, low-latency, front-end FPGA processing with advanced switch fabric management in an open-systems blade that is designed and made in the United States. Mercury Systems, Inc. • www.mrcy.com • www.vita-technologies.com/p373441

22 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com

2016 RESOURCE GUIDE INDEX

Company Category Page Company Category Page

ADLINK Technology VPX 43 Interface Concept Networking 26 esource Guide ALPHI Technology Corporation PMC 37 Interface Concept OpenVPX 33

Annapolis Micro Systems, Inc. FMC 25 Interface Concept OpenVPX 34

Annapolis Micro Systems, Inc. OpenVPX 27 Intermas US LLC VME 40

Annapolis Micro Systems, Inc. OpenVPX 28 KONTRON OpenVPX 34

Annapolis Micro Systems, Inc. OpenVPX 29 KONTRON OpenVPX 35

R Technologiess VITA Annapolis Micro Systems, Inc. OpenVPX 30 LCR Embedded Systems VPX 46

Annapolis Micro Systems, Inc. OpenVPX 31 North Atlantic Industries, Inc. VME 41

Annapolis Micro Systems, Inc. Operating Systems and Tools 38 Pentair/Schroff OpenVPX 35

Annapolis Micro Systems, Inc. Operating Systems and Tools 39 Pentair/Schroff VME 41

Concurrent Technologies VPX 44 Pentek OpenVPX 36

Curtiss-Wright Defense Solutions VPX 44 Pixus Technologies OpenVPX 37

Dawn VME Products OpenVPX 32 TE Connectivity VPX 46 Highland Technology Elma ElectronicVITA Inc. Summer Issue insertVPX 45 Themis Computer Small Form Factor 40 04/01/15 Hartmann Electronic OpenVPX 33 TTI & TE Connectivity VPX 47

InnovativeNOTE: Integration KEYLINE DOESFMC NOT PRINT 26 Vector Electronics & Technology, Inc. VME 42

InnovativeTRIM Integration as shown XMC/PMC 47

Continuing our long term commitment to VME

HIGHLAND TECHNOLOGY

CRATE CONTROL Cabled PCIe, ethernet / USB OUTPUT and SIMULATION DATA ACQUISITION Arbitrary waveform Precision analog Rotating machine Wide range source measurement Synchro /resolver / LVDT Synchro / resolver / LVDT Thermocouple Tachometer / overspeed Analog and digital / relay I/O Thermocouple / RTD / Cryo Voltage and 4/20 mA I/O Isolated digital input Resistance measurement

www.HighlandTechnology.com tel: 1-415-551-1700 fax: 1-415 551-5129

24 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R FMC esource Guide

Ultra-Low Latency DRFM-Optimized Mezzanine Cards

These ultra-low latency mezzanine cards are specifically designed for DRFM applications with latency as low as 20ns from SMA to SMA. FEATURES Ultra-Low Latency DRFM-Optimized Mezzanine Cards have ĄĄ Single or Dual Channel available running at up to 3GSps been designed from the ground up for latency sensitive DRFM each applications. The Board Support Interface, which is available in ĄĄ Ultra Low latency from ADC SMA input to DAC SMA output VHDL or Open Project Builder, was also designed from the begin- • Digital Bypass Mode (SMA-to-SMA): as low as 21ns ning to be suited for DRFM applications. This interface provides a • Fabric Space Mode (SMA-to-SMA): as low as 39ns Digital Bypass Mode to achieve the lowest possible latency and ĄĄ Digital Bypass Mode has built-in run-time adjustable delay a Fabric Space Mode to allow the user to do additional process- providing additional delay from 0ns up to 124 Sclk periods ing and manipulation of the ADC data before returning it out the ĄĄ Support for a variety of WILDSTAR mainboards DAC. The Fabric Space Mode adds as little as 13ns of latency. The Board Support Interface also includes a built-in Bypass Delay. This ĄĄ Firmware and Software Board Support Interface provided allows the user to “walk” the latency out from the minimum Digital in Open Project Builder Bypass Mode latency to slightly beyond the Fabric Space Latency, ĄĄ Converter channels can be synchronized providing for a smooth latency transition between the two modes. Open Project Builder, Annapolis’ FPGA Design Tool, allows the user to design a DRFM-optimized application in minutes.

Latency Number of Speed Digital Fabric ADC (bits) DAC (bits) Channels Bypass Space (GSps) Mode Mode 3.0GSps 12-Bit ADC & DAC for 1+1 <37ns <50ns 3.0 12 12 WILD FMC+ 2.5GSps 10-Bit ADC 12-Bit DAC 1+1 < 21ns < 42ns 2.5 10 12 for WILD FMC+ WILDSTAR Dual 1.5 GSps 12-Bit ADC & DAC Converter 2+2 < 24ns < 39ns 1.5 12 12 Mezzanine

vita.opensystemsmedia.com/p373414

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/product-category/adc-dac-drfm/  410-841-2514 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 25 FMC esource Guide

FMC Modules

Innovative Integration’s FMC Family of Modules: Module A/D D/A FMC-1000 2x1250MSPS • 14b 2x1250MSPS • 16b R Technologiess VITA FMC-500 2x500MSPS • 14b 2x1230MSPS • 16b FMC-310 4x310MSPS • 16b FMC-250 2x250MSPS • 16b 2x500MSPS • 16b FEATURES FMC-Servo 8x500KSPS • 16b 8x500KSPS • 16b ĄĄ High Speed Digitizing Signal Generation for Wireless FMC-SFP+ 4xSFP+ Ports Transceiver Pulse Generation, Medical Imaging, Precision FMC-QSFP 2xQSFP Ports Recording/Playback, RADAR, LTE WiMAX Physical Layer, FMC-SDF 4x1MSPS • 14b 1x1MSPS • 16b Wireless Receiver and Transmitter FMC-10GE 2x10Gbe ePC-K7 only ĄĄ Remote Radio Head receiver, OBSAI and CPRI interface Download data sheets and pricing now! ĄĄ Serial FPDP and SRIO fiber optic ports

vita.opensystemsmedia.com/p373447

Innovative Integration  [email protected] www.innovative-dsp.com  805-383-8994

Networking

ComEth4080a

The ComEth4080a expands our ComEth40xx range in the 3U VPX world. The ComEth4080a provides up to 21 Giga ports and covers a lack of the current OpenVPX release by offering a mix of 1000Base-T and 1000Base-KX ports on the backplane. The ComEth4080a can cover the needs for 1000-KX CPUs interconnection via the backplane, FEATURES but also the needs to connect legacy boards, external sensors or systems claiming for 1000Base-T interfaces. This switch supports ĄĄ Ethernet port configuration: full-wire speed L2 bridging and L3 routing with L2-L4 advanced • 8 1000Base-BX on P1 (RB) traffic classification, filtering and prioritization with optimized power • 12 1000Base-T on P1/P2 (RB) consumption. It is fully upward compatible with the Switchware of our • 1 auto media detect Ethernet port (FB) ComEth40xx range; it thus benefits from all the latest developments including: IPv6 support, RIPng, OSPF v3, VRRP, additional security • 10/100/1000Base-T (RJ45) or 1000Base SX features (HTTP/SSH client authentications), configurable memory allocation, and new status counters. vita.opensystemsmedia.com/p370370

Interface Concept   www.interfaceconcept.com [email protected] +33(0) 2 98 57 30 30 or 800-445-6194

26 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX esource Guide

Processing – Arria 10 and UltraScale FEATURES

Annapolis FPGA boards are engineered for superior ĄĄ General Features • Altera Arria 10 or Xilinx Kintex UltraScale FPGAs performance and maximum bandwidth. Both Altera • – Hard 8x PCIe Gen3 endpoint for DMA and register access and Xilinx FPGAs are leveraged to offer the best FPGA • – FPGAs programmable from attached flash or Annapolis • provided software API technology available and to fit customer preference, • – 20-nm copper CMOS process • – Available with DDR4 DRAM, QDR-IV SRAM ports on all design requirements and production schedule. • FPGAs • Dual Core ARM Cortex-A9 Processor (Cyclone V or Zynq SoC) • – Host Software: Linux API and Device Drivers These FPGA cards paired with Annapolis OpenVPX • PLX PCI Express Gen3 Switch compliant 6U/3U backplanes enable even the most • – Allows expansion plane “chaining” of PCIe bus between • adjacent slots. No dedicated PCIe switch slot needed bandwidth-intensive applications. • Available in 6U and 3U form factors • A Full Board Support Package using Open Project Builder for Fast and Easy Application Development • System Management ĄĄ Backplane I/O • Two PCIe Gen3 4x Connections to VPX Backplane Annapolis is famous for the high quality of • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed our products and for our unparalleled dedication protocols to ensuring that the customer’s • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK applications succeed. • – Allows reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards We offer training and exceptional ĄĄ Front Panel I/O special application • Wild FMC+ (WFMC+) next generation I/O site based on FMC+ specification development support, as well as • – Accepts standard FMC and FMC+ cards (complies to FMC+ more conventional support. specification) • Up to 32 High Speed Serial and 100 LVDS connections to FPGA ĄĄ Mechanical and Environmental • Available in Extended Temperature Grades • Air or Conduction Cooled path • RTM available for additional I/O

vita.opensystemsmedia.com/p373445

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/products/wildstar-ultrak-3u-openvpx/  410-841-2514 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 27 OpenVPX

esource Guide Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed.

We offer training and exceptional special application development support, as well as more conventional support. R Technologiess VITA

Ruggedized Systems and High Temperatures

Ruggedized COTS systems from Annapolis Micro Systems to various stringent standards such as MIL-STD-810 are designed to withstand the harshest environments. From and RTCA/DO-160 (for airborne equipment). This inde- the bitter cold of an Antarctic radar station to the hottest pendent testing proves the ability to withstand: deserts of the Middle East, AMS equipment is real-world • Temperature extremes & thermal shock deployed for the most demanding embedded applications. • Liquid & dust ingress

Cooling Options • Humidity, fungus & corrosion Depending on the application, AMS chassis are robustly • Vibration & shock designed using Air, Conduction, or Liquid cooling. During • Other application-specific stressors the design process, every board and system is simulated for thermal performance, then subjected to hours of gruel- Designed & Manufactured in USA ing operation to verify its ability to withstand temperature All AMS products are engineered and manufactured stresses. under one roof in the United States. This co-location of engineering and manufacturing allows for more Independently Verified aggressive design, and better quality control and pro- AMS verifies environmental conformance of its equipment duction flexibility.

Thermal Model of an Annapolis Conduction-Cooled WILDSTAR 3U OpenVPX Chassis

vita.opensystemsmedia.com/p373413

Annapolis Micro Systems, Inc.  [email protected] www.annapmicro.com  410-841-2514

28 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX esource Guide

Wild40 OpenVPX EcoSystem Chassis

In May 2013, Annapolis became the first company to bring 40Gb bandwidth to OpenVPX with our line of COTS backplanes, chassis and payload cards that are fully designed, qualified and tested for 40Gb bandwidths. The Wild40 EcoSystem for OpenVPX chassis includes both switched FEATURES and mesh backplane architectures and has already been extensively deployed around the world. ĄĄ OpenVPX High Speed Backplane with RTM Support • 10.3 Gbps Line Rates on Data and Expansion Planes Annapolis tests the interoperability between Wild40 Eco- • 40GBase-KR4 Ethernet • 10GBase-KX4 XAUI System components on each and every chassis to ensure • SDR, DDR and QDR 4x InfiniBand reliability, consistent performance and best possible user • 2.5-10 Gbps AnnapMicro Protocol (Low FPGA utilization protocol for FPGA-FPGA connections) experience. • 8x PCIe Gen 1, 2 or 3 Annapolis is moving towards 100 Gb EcoSystems that are • 1000Base-x on Control Plane ĄĄ easier to both deploy and maintain. System designs are Chassis Management: Voltage, Temperature and Fan Monitoring and Control streamlined by moving as many connections as possible ĄĄ Front Chassis Display Panel to the rear or onto the backplane. ĄĄ Front Panel Power Switch, System Reset Switch and These upgraded EcoSystems simplify maintainability by Maskable Reset Switch, All with Safety Covers removing all or many of the connections from the front of ĄĄ Allows for boards to be Hot Swappable the modules. ĄĄ High Performance Air Cooling with Cleanable Fans and Filters (Conduction Cooling and Liquid Cooling options available) Annapolis is also developing large, modular chassis sys- ĄĄ Electromagnetic Shielding tems. All components of the chassis will be top-mounted. ĄĄ Commercial Environmental Specifications All payload cards, switch cards, 6U power modules, and • Temperature: Operating: 0 to +50 C Storage: -20 to +70 C • Altitude: Operating: 0 to 6,000 Feet Storage: 0 to 50,000 fan trays will plug into one backplane. These chassis will Feet feature hot-swappable components and cables will be • Humidity: Operating and Storage: 5 to 95% Noncondensing minimized. • Vibration Sine: 1.0g @ 10 to 330Hz • Shock: 10 Gs @ 11ms

vita.opensystemsmedia.com/p373409

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/product-category/chassis-openvpx-6u-ecosystem/  410-841-2514 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 29 OpenVPX esource Guide

R Technologiess VITA WILD Data Storage Solution

When Storage capability is needed, Annapolis offers the highest density OpenVPX storage solutions on the market. Available in 6U and 3U form factors, the WILDSTAR Data Storage Solution features a removable hot swappable canister with a connector rated for 10,000+ mating cycles. The WILD Data Storage Solution comes with standard images to support XAUI, 40GbE and AnnapMicro Protocol (Annapolis low FPGA utilization, full flow control protocol ideal for inter-FPGA communication).

The WILD Data Storage Solution is comprised of two pieces fitting in a single 1" OpenVPX slot, the “Storage FEATURES Canister” and the “Storage Carrier” that plugs into the VPX ĄĄ 3U boards feature 8 TB (currently) or 16 TB (available in 2017) Storage Depth and 5-7 GB/s Bandwidth backplane and holds the disk canister. ĄĄ 6U boards feature 16 TB (currently) or 32 TB (available in 2017) Storage Depth and 10-14 GB/s Bandwidth ĄĄ Backplane I/O using PCIe or 40Gb Ethernet ĄĄ Scalable Depth and Bandwidth using multiple Storage Annapolis is famous for the high quality of our Cards products and for our unparalleled dedication to ĄĄ Hot Swappable Drive Canister with 10,000 Insertion ensuring that the customer’s applications succeed. Cycles & Hot Swappable Carrier (exclusive to WILDSTAR OpenVPX EcoSystem) We offer training and exceptional ĄĄ 6U/3U OpenVPX (VITA 65) Compliant, 1" VITA 48.1 spacing special application development support, ĄĄ Air Cooled or Conduction Cooled as well as more conventional support. ĄĄ Proactive Thermal Management

vita.opensystemsmedia.com/p373411

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/product-category/storage-boards/  410-841-2514

30 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX esource Guide

WILDSTAR A5 and WILDSTAR 7 for OpenVPX FPGA Boards

Annapolis FPGA boards are engineered for superior FEATURES performance and maximum bandwidth. Both Altera ĄĄ General Features • Xilinx Virtex 7 or Altera Stratix® V FPGAs and Xilinx FPGAs are leveraged to offer the best FPGA • PCIe Gen3 8x from each FPGA to on-board PCIe switch • Up to 24x High Speed Serial I/O lanes to VPX Backplane (P1/P2) technology available and to fit customer preference, for up to 60 GB/s of Full Duplex Bandwidth • Manufacturing options for SRAM or DRAM on the IOPE as well as design requirements and production schedule. multiple memory sizes • RTM available for additional I/O • Available in 6U and 3U form factors These FPGA cards paired with Annapolis OpenVPX • A Full Board Support Package using Open Project Builder for Fast and Easy Application Development compliant 6U/3U backplanes enable even the most • System Management • Hot Swappable bandwidth-intensive applications. ĄĄ Backplane I/O • Two PCIe Gen3 4x Connections to VPX Backplane • Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK • – Allows reference clock and trigger from backplane to synchronize Annapolis is famous for the high quality of our and clock compatible ADC/DAC mezzanine cards products and for our unparalleled dedication to ĄĄ Front Panel I/O • Accepts Standard Annapolis WILDSTAR Mezzanine Cards, including ensuring that the customer’s applications succeed. a wide variety of WILDSTAR ADC and DAC Mezzanine Cards • Three or six optional built-in Front Panel QSFP+ Transceivers running at up to 52.4 Gbps each for 39 GB/s of Full Duplex We offer training and exceptional Bandwidth special application development support, • QSFP+ Protocol Agnostic connections support 10/40Gb Ethernet, SDR/DDR/QDR InfiniBand, AnnapMicro protocol and user-designed as well as more conventional support. protocols ĄĄ Mechanical and Environmental • Available in Extended Temperature Grades • Air or Conduction Cooled path • RTM available for additional I/O

vita.opensystemsmedia.com/p373415

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/product-category/fpga-boards-openvpx-6u-ecosystem/  410-841-2514 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 31 OpenVPX esource Guide Fabric Mapping Modules

Dawn OpenVPX backplane Fabric Mapping Modules simplify topology customization. Dawn VME Products FABRIC MAPPING MODULES auto- mate optimization of OpenVPX backplane topologies. Newly patented FEATURES FMM micro-overlays quickly customize off-the-shelf OpenVPX back- ĄĄ Off-the-shelf backplanes can be quickly customized to mission planes to mission requirements. requirements R Technologiess VITA ĄĄ Fabric Mapping Modules allow designers to work with flexible configura- Optimize the communication topology between slots within a system’s backplane tions of high speed links. Off-the-shelf backplanes can be quickly cus- ĄĄ Customize inter-slot communications to meet unique system tomized to mission requirements without the time and expense required requirements for new backplane designs, a critical advantage when schedules are ĄĄ Improve signal integrity between system cards beyond requirements of PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards compressed by late system changes. Dawn engineers have successfully ĄĄ Directly connect PCI Express or SerialRapid I/O to multiple cards or used Fabric Mapping Modules to solve many OpenVPX application cards and switches problems in the design phase. ĄĄ Link SATA from a CPU card to a Solid State Drive (SSD) carrier ĄĄ Enable XMC cards to talk to other XMC cards or other I/O like Fabric Mapping Modules provide a natural migratory development PCI Express links environment for moving from the lab to the field with high speed ĄĄ Facilitate rear backplane I/O connections and low profile connector OpenVPX backplanes. interface systems when normal transition modules do not fit the system application envelope vita.opensystemsmedia.com/p372452

Dawn VME Products  [email protected]  www.dawnvme.com 800-258-DAWN (3296) • 510-657-4444

OpenVPX

PSC-6265

VITA 62 compliant 6U power supply for conduction cooled systems. Dawn’s VITA 62 compliant 6U PSC-6265 can operate continuously in diverse environments over a wide range of temperatures at high power levels. The standard model is conduction to wedge lock cooled FEATURES with an operating temperature range of -40C to +85C and a non- ĄĄ Continuous 580W output over temperature range of -40C to +85C operating range of -55C to +105C. ĄĄ True 6 Channel supply provides full OpenVPX support ĄĄ Secondary Side Wedge lock conduction cooled The PSC-6265 operates continuously at a power level of 580 watts. ĄĄ 6U, 1 inch pitch form factor For systems that require higher power levels, up to three supplies may ĄĄ Compatible with Dawn’s HLD-6262 Holdup Module be operated in parallel. ĄĄ Fault monitoring and control ĄĄ Output over-voltage, over-current, and over-temperature shutdown Fault monitoring and control circuits protect the system from over- protection voltage, over-current, and over-temperature conditions. ĄĄ Current/Load share compatible with up to 3 PSC-6265 units ĄĄ Standard INHIBIT*, ENABLE*, FAIL* and SYSRESET* control signals Power supply operational or fault status is displayed using colored ĄĄ VBAT for support of VPX memory backup power bus LEDs on front panel. ĄĄ Front I/O panel includes LED status indicator, and VBAT battery access ĄĄ VITA 48.2 Compliant Inject/Eject levers for easy installation vita.opensystemsmedia.com/p372930

Dawn VME Products  [email protected] www.dawnvme.com  800-258-DAWN (3296) • 510-657-4444

32 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX

OpenVPX Product Range

Hartmann Electronic offers a full product range of OpenVPX products, like esource Guide BACKPLANE, POWER SUPPLY, ATR, Power BACKPLANE, SHELF MANAGER, 19'' RACK, high speed ADAPTERS, BRIDGES, OPEN FRAME Chassis, and LOAD BOARDS. With a long experience in Backplane design, for more than 40 years, Hartmann Electronic started in 2008 with the first VPX-Backplane design. Since 2012 Hartmann Backplanes support 50 GBit PCIe transmission (FP) and 10 GBit Ethernet. The newest Backplanes are VITA 66 based for Fiber Optics and RF Signals. In addition, Hartmann designed VPX Power FEATURES Supplies according to VITA 62, in 3U, 6U, air cooled and conduction cooled. ĄĄ OpenVPX Backplanes 50Gbd PCIe, 10GBit Ethernet Housings are available as ATR or in 19'' form factor. For development ĄĄ purposes, Hartmann offers different Open Frame chassis and a transport- VITA 62 Power Supplies, 3U, 6U, air-, conduction-cooled able Tower Rack. Other accessories like Load Boards, Shelf Managers, and ĄĄ ATR conduction cooled Power Backplanes are also available in different sizes. ĄĄ Open Frame and Tower Chassis for VPX Hartmann specialties are custom designed high speed Backplanes and ĄĄ System Platforms for different Standards or complete custom. At the Load Boards 3U, 6U, air-, conduction-cooled moment Hartmann is releasing a brand new PCIe Extension Board that ĄĄ Power Backplanes 3U, 6U can be used to run commercial PCI or Micro PCIe devices on OpenVPX ĄĄ VITA 66 Backplanes for Fiber or RF Backplanes or CompactPCI Serial Backplanes. Systems can be linked together by fiber optic cables. vita.opensystemsmedia.com/p373429

Hartmann Electronic www.hartmann-electronic.com  [email protected]  +49 711 13989 0

OpenVPX

IC-FEP-VPX3c

The IC-FEP-VPX3c expands our Front End Processing family with a solution based on Xilinx Virtex-7 FPGAs to respond to seemingly insatiable bandwidth demand. Designed for applications requiring a FEATURES very high level of computing power in a compact 3U form factor, the ĄĄ Xilinx Virtex-7 XC7VX690T (other versions on demand) IC-FEP-VPX3c board offers the highest bandwidth with the lowest ĄĄ Two banks of DDR3: 64-bit wide, 2GB each power consumption. ĄĄ Optional QDRII+ 450MHz, 36-bit wide/up to 36 Mb The IC-FEP-VPX3c and the other building blocks of our 3U OpenVPX ĄĄ 128 MB of BPI NOR flash (bitstream storage) product ranges (Intel and Freescale SBCs, Ethernet Switches and Routers, I/O boards/FMC) running our Signal Processing Reference ĄĄ VPX interfaces: Four 4-lanes fabric ports on P1, general-purpose I/O on P2 Design (including signal acquisition, Processing, DMA Engine, data storage, signal generation) are the ideal platforms for customers who ĄĄ FMC interfaces: 8 GTX/GTH (FPGA part number dependent), want to streamline development by concentrating their efforts on 80 differential pairs, 4 reference clocks their most critical tasks. vita.opensystemsmedia.com/p371808

Interface Concept   www.interfaceconcept.com [email protected] +33(0) 2 98 57 30 30 or 800-445-6194 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 33 OpenVPX esource Guide

IC-FEP-VPX6a

The IC-FEP-VPX6a is a VPX hybrid processing engine coupling the latest generations of FPGAs and processor, both of them delivering R Technologiess VITA a very high level of performance per watt. With its QorIQ processor FEATURES for system management and a PCIe advanced switch for versatile ĄĄ Processing units: One QorIQ processor P2020, 1 GHz, e500 v2 coupling between the processing nodes, the IC-FEP-VPX6a board core, two Xilinx Virtex-6 SX315T (-1 or -2), SX475T (-1 only), expands the flexibility of the two Virtex-6 FPGAs and the VPX high LX240T or LX550T, one Spartan-6 LX-45T bandwidth serial interfaces. ĄĄ VPX interfaces: 4 PCIe x4 port (from PCIe switch), GTX ports, Two FMC mezzanine sites enlarge the adaptability of the board to 2 GTP connect ADC, DAC, general I/O, video, sFPDP or additional FPGA FMC ĄĄ General-purpose I/O: 2 LVDS (16 from each FPGAs), 2 differential modules. With this combination of high performance CPU, dual FPGAs pairs (16 from each FMC I/O connector), GPIO and FMC sites, the IC-FEP-VPX6a provides the ideal platform for ĄĄ FMC interfaces: 80 LVDS, 4 reference clocks, 1 GTX x4 link radar, sonar, electronic warfare and other very high demanding digital signal processing applications. vita.opensystemsmedia.com/p365111

Interface Concept   www.interfaceconcept.com [email protected] +33(0) 2 98 57 30 30 or 800-445-6194

OpenVPX

Kontron 3U VPX PCI Express and Ethernet hybrid switch VX3905

The Kontron 3U VPX PCI Express and Ethernet hybrid switch VX3905 is the ideal partner for the centralized backplane to efficiently handle a high bandwidth. It provides up to 24 Ports with 32 lane PCI Express Gen 1/Gen 2 switching and additional 9 port gigabit Ethernet switching capabilities for the control plane. By this it offers a tenfold increase in I/O bandwidth between computing boards in High Performance Embedded Computing applications compared to VME, unleashing a new kind of application for data processing platforms used for Radar, Sonar and general image processing. For customers to capitalize on the Kontron VX3905‘s high bandwidth, while FEATURES enjoying optimized time-to-market in centralized VPX/OpenVPX™ architectures, Kontron offers VXFabric™, an efficient software solution for interboard ĄĄ Compliant with OpenVPX VITA65 profile SLT3-SWH-6F6U-14.4.1 communication. With Kontron VXFabric™ on Kontron 3U and 6U VPX proces- ĄĄ Up to 24 Ports/32 Lanes PCIe Switch sor boards, OEMs can use common Linux and TCP or UDP sockets. Kontron VXFabric™ software simplifies and accelerates application development and ĄĄ 9 Port Giga Ethernet Switch helps to extend application lifecycles as it enables migration to hardware communication standards, such as 10G and 40G Ethernet. ĄĄ Air-cooled and Conduction-cooled Builds The Kontron VX3905 is available in an air-cooled version (0°C to +55°C) and in rugged conduction-cooled version (-40°C to + 85°C). vita.opensystemsmedia.com/p373394

  KONTRON [email protected] 888-294-4558 http://www.kontron.com/industries/defense https://www.linkedin.com/company/kontron @Kontron

34 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX

VX3058 Octo Core Intel® Xeon® Processor VPX server blade esource Guide Kontron‘s 3U VPX blade VX3058 is based on the highly integrated 8-core Intel® Xeon® D architecture, supporting Dual 10 Gigabit Ethernet, high bandwidth PCI Express 3.0, and high speed DDR4 memory. It is conse- quently SWaP-C optimized with versatile mezzanine options for XMC, storage, graphics, M.2, and I/O. The M.2 interface can be used for storage or for integration of customized personality modules. Front I/O module options are selectable for DVI/HDMI, Ethernet or other interfaces. The Kontron VxFabric™ provides a unique API that extends the TCP/IP proto- FEATURES col over the PCI Express infrastructure that when combined with Kontron's advanced switch technologies, enables significantly higher I/O bandwidth. ĄĄ Fit for Virtual Machines and HPEC Applications The Kontron VX3058 is pin compatible with the company‘s popular and ĄĄ previous generation VX3044 3U VPX board, which already deploys 10 Extended Life Cycle and 10-year Silicon Reliability gigabit (G) Ethernet and PCIe gen3 on the OpenVPX backplane. Options ĄĄ Dual 10 Gigabit Ethernet, x8 PCI Express Gen3 Bandwidth include a shelf manager for centralized health management, sequenced ® system power-up and Temperature/Power/Performance management as ĄĄ 8 Core Xeon Processor D, 16 GB DDR4 with ECC well as Power-On Built-in Test (PBIT) that give designers a comprehensive package for board and system diagnosis. vita.opensystemsmedia.com/p373395

  KONTRON [email protected] 888-294-4558 http://www.kontron.com/industries/defense https://www.linkedin.com/company/kontron @Kontron

OpenVPX

Schroff High Clamp Force Retainers from Pentair

Pentair is proud to offer the new Schroff Series 260HC High Clamp Conveniently, the Schroff Series 260HC has been designed to be Force Card Lok retainer. The patent-pending design of the Series a drop-in replacement for most applications currently using a 260HC provides on average nearly triple the clamping force of standard 260 Card Lok, with the same profile 6.35 (.250") width similarly sized Card Loks. x 6.86 (.270") height, mounting hole locations, and optional features such as a visual indicator and lock patch. As systems continue to be integrated into rugged environments and face ever increasing shock and vibration, sufficient printed circuit Pentair is also pleased to offer a full range of OpenVPX, VXS, board retention is critical. Additionally, SWaP or reducing size and VME64x and VME Bus based products as well as a full range weight while effectively handling increasing power, continues to be a of power supplies, chassis components, cooling solutions and focus for defense and aerospace designers and manufacturers. racking products to support all your project needs. The Schroff Series 260HC overcomes these challenges, providing on Contact the experts at Pentair today to start your project on average 1,257lbs of clamping force, in a compact form factor. the path to success!

vita.opensystemsmedia.com/p373450

Pentair/Schroff  [email protected]  http://www.pentairprotect.com/schroff-na 1-800-525-4682 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 35 OpenVPX esource Guide

Model 5973-324 FEATURES

The Model 5973-324 is a member of the Flexor® family ĄĄ Supports Xilinx Virtex-7 VXT FPGAs of high-performance 3U VPX boards based on the Xilinx ĄĄ GateXpress supports dynamic FPGA reconfiguration across Virtex-7 FPGA. PCIe

R Technologiess VITA As a FlexorSet™ integrated solution, the Model 3324 FMC ĄĄ Four 500 MHz 16-bit A/Ds & Four digital upconverters is factory-installed on the 5973 FMC carrier. The required ĄĄ Four 2 GHz 16-bit D/As (500 MHz input sample rate, FPGA IP is installed and the board set is delivered ready for 2 GHz output sample rate with interpolation) immediate use. ĄĄ 4 GB of DDR3 SDRAM The delivered FlexorSet is a multichannel, high-speed data ĄĄ Sample clock synchronization to an external system reference converter and is suitable for connection to the HF or IF ports ĄĄ PCI Express (Gen. 1, 2 & 3) interface up to x8 of a communications or radar system. Its built-in data capture ĄĄ User-configurable gigabit serial interface and playback features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA process- ĄĄ Optional optical Interface for gigabit serial interboard ing IP. It includes four 500 MHz, 16-bit A/Ds, four digital up communication converters, four 2 GHz, 16-bit D/As, and four banks of memory. ĄĄ Compatible with several VITA standards including: ™ In addition to supporting PCIe Gen. 3 as a native interface, the VITA 46, VITA 48, VITA 66.4 and VITA 65 (OpenVPX System Specification) Model 5973-324 includes optional copper and optical connections to the Virtex-7 FPGA for custom I/O. ĄĄ Ruggedized and conduction-cooled versions available

RF In RF In RF In RF In RF Out RF Out RF Out RF Out

Sample Clk / RF RF RF RF RF RF RF RF Reference Clk In XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR XFORMR

TIMING BUS Gate /Trigger / A/D GENERATOR Sync/PPS Clock/Sync Bus 500 MHz 500 MHz 500 MHz 500 MHz Clock/Sync / 16-BIT A/D 16-BIT A/D 16-BIT A/D 16-BIT A/D 2 GHz 2 GHz 2 GHz 2 GHz Gate/PPS D/A 16-BIT D/A 16-BIT D/A Clock/Sync 16-BIT D/A 16-BIT D/A Bus DIGITAL DIGITAL DIGITAL DIGITAL UPCONVERT UPCONVERT UPCONVERT UPCONVERT Control & Status

VCXO

FMC CONNECTOR Model 3324 FMC

Model 5973 FMC Carrier FMC CONNECTOR

160 10X

LVDS GTX

VIRTEX-7 FPGA VX330T or VX690T

GTX GTX LVDS GTX

CONFIG FPGA PCIe 32 32 32 32 12X FLASH Config 16 1GB Gen.3x8 4X FPGA Bus pairs DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM Gigabit GATEXPRESS PCIe 1GB 1GB 1GB 1GB Serial I/O CONFIGURATION MANAGER OPTICAL FPGA FPGA TRANSCEIVER PCIe Gigabit LVDS (Optional) Gen.3x8 Serial I/O GPIO

VPX-P2 (½) VPX-P0 VPX-P1 VPX-P2 (½) VITA 66.4 VPX BACKPLANE

vita.opensystemsmedia.com/p373426

Pentek  [email protected]  201-818-5900 http://www.pentek.com/go/vita5973 www.linkedin.com/company/pentek @pentekinc

36 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R OpenVPX esource Guide

OpenVPX Backplanes & Chassis Platforms Are you ready for a better experience for your OpenVPX backplane and chassis platform design? Then it‘s time to try Pixus Technologies. Our knowledgeable team will guide you through the process and help you find a cost-effective solution that FEATURES meets your application‘s specific requirements. Pixus has a ĄĄ OpenVPX backplane expertise with various standard configurations wealth of standard backplanes and modular OpenVPX enclosure ĄĄ Virtually unlimited options of OpenVPX chassis platform designs platforms as a framework to start your tailored design. ĄĄ Integrated system management options Whether it‘s a rugged chassis/ATR that meets MIL-704, 810, or ĄĄ Rugged conduction-cooled or convection-cooled options 461, or a 19" rackmount design, Pixus has an OpenVPX solution ĄĄ Options for full systems with OpenVPX SBCs, FPGAs, & specialty for you. boards ĄĄ 40G backplanes, other high-speed options

Enclosures Cases Subracks Backplanes Chassis Integrated Systems Components vita.opensystemsmedia.com/p373373

Pixus Technologies  [email protected]  www.pixustechnologies.com 519-885-5775 @pixustech

PMC

PMC-CIV-COM-ISO

Summary: • Cyclone IV EP4CE30 484-fbga package • Cyclone IV FPGA allows a wide range of customization options. • 4 Mbyte SRAM • SRAM is dual ported FEATURES • User Reconfigurable I/O ĄĄ • ISOLATED I/O lines, Up to 155Mbps User Programmable Altera Cyclone IV FPGA 484 BGA: • Each GPIO line has independent Interrupt Support programmable ĄĄ Stand alone possibility for Edge trigger ĄĄ Single wide PMC Module • On board Serial configuration device programmable via ĄĄ Opto Isolated 20 LVDS, 2 RS-422,1 RS-232 PMC bus or bit/byte blaster ĄĄ Optional User clock oscillator • Local serial EPROM • Internal/External clock Custom Designs: In addition, Alphi offers complete • PCI +3.3V/+5V Operation and Logic Engineering Design Services. • 32/64 MHz PMC clock support Custom hardware, drivers and application software as well as • Front panel I/O access FPGA development, we are ready to help. • Windows, Linux and VxWorks Drivers vita.opensystemsmedia.com/p373375

ALPHI Technology Corporation www.Alphitech.com  [email protected]  480-838-2428 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 37 Operating Systems and Tools

Annapolis is famous for the high quality of our products esource Guide and for our unparalleled dedication to ensuring that the customer’s applications succeed.

We offer training and exceptional special application development support, as well as more conventional support. R Technologiess VITA FEATURES

Application Development Team ĄĄ Application Types: • Radar Annapolis Micro Systems employs a select team of • ELINT experienced FPGA designers dedicated to helping you • SIGINT solve your real-world processing challenges while • COMINT • Digital Recording minimizing your Time to Market. Our patented Open Project Builder provides high-speed solutions that get ĄĄ Capabilities: • System Architecture the application developed in record time, drastically • Algorithm sizing and implementation reducing program cost and risk. • GUIs

vita.opensystemsmedia.com/p372789

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/services-support/application-development-team/  410-841-2514

38 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R Operating Systems and Tools esource Guide

Open Project Builder FEATURES

The Annapolis Micro Systems, Inc. Open Project Builder pro- ĄĄ Board Support Space vides the efficiency of CoreFire Next development with the ĄĄ Board Support Packages for all WILDSTAR Boards: flexibility of HDL. It integrates the CoreFire environment with Stratix 5, Virtex 7, Arria 10, UltraScale, Stratix 10, etc. Annapolis HDL board support packages. ĄĄ User Space

The user has the capability to use FPGA IP from other sources, ĄĄ Algorithmic: DSP, Math, etc. such as CoreFire Next, HSL, other HDL, etc. Open Project ĄĄ Data Flow Control Builder can also port IP to/from other platforms. It uses ĄĄ Bit and Type Manipulations standard Avalon and AXI IP interfaces. Open Project Builder uses fast portabil- ity of application between Altera and Xilinx and to newer FPGA families.

vita.opensystemsmedia.com/p373350

Annapolis Micro Systems, Inc.  [email protected] https://www.annapmicro.com/product-category/developmenttools/  410-841-2514 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 39 Small Form Factor esource Guide

NanoSWITCH

NanoSWITCH is a SWAP-C optimized rugged multi-layer gigabit Ethernet switch with an embedded x86 PC. The NanoSWITCH brings enterprise level layer 2/3 switching to rugged environments including military ground, air and sea vehicles, and unforgiving industrial environments. Typical applications include vehicle network switching, distributed architecture vehicle controller, VICTORY FEATURES compliant switch, router, timing, and control, WAN/LAN interconnectivity and R Technologiess VITA firewall, and shared processing and peripheral communications. ĄĄ Layer 2/3 Enterprise non-blocking network switch for demanding NanoSWITCH provides 16x or 10x external Gigabit Ethernet ports that operate SWAP-C environments at rates of 10, 100, and 1000 Mbps. A full management suite is included, as ĄĄ 16x GigE Ethernet ports with auto tri-speed 10/100/1000Mbps well as a Command Line Interface (CLI) for controlling switch and routing opera- and MDIX tions. The NanoSWITCH supports sophisticated IPv4 and IPv6 routing, including tunneling and IP Multicast, VLANs, and IETF, IEEE, and DSL Forum standards. ĄĄ MIL-STD-1275E – Ground vehicle power; MIL-STD-704F – The NanoSWITCH includes numerous Quality of Service (QoS) features to ensure Aircraft power (with no hold up); MIL-STD-461F – EMI; that traffic is prioritized to deliver the superior performance for real-time appli- MIL-STD-810G – Environmental cations including system management, voice, video, and bandwidth-intensive ĄĄ 10 or 16 port versions file uploads and downloads. ĄĄ Full featured AMD Fusion APU for VICTORY or user applications NanoSWITCH is available in a VICTORY software configuration. The VICTORY open standard, or “Vehicular Integration for C4ISR/EW Interoperability” stan- ĄĄ 1GB DRAM, 64GB SSD dard (http://victory-standards.org/), provides a common data-bus centric ĄĄ Operating temperature: -40°C to 71°C approach to sharing services and hardware components, eliminating redundancy and reducing SWAP in Army ground vehicles. vita.opensystemsmedia.com/p373404

  Themis Computer [email protected] 408-623-1545 www.themis.com/nanoswitch http://www.linkedin.com/company/17952 @Themis_Computer

VME

Intermas – InterRail Intermas develops electronic enclosure systems: Cabinets, housings, subracks, and an extensive range of accessories for the 19" rack systems used in the fields of PCI, VME/VME64x, cPCI, IEEE, and communication applications with state-of-the-art EMI- and FEATURES RFI-shielded protection. ĄĄ InterRail® products meet tough physical demands and vibration Intermas has an extensive product range of more than 10,000 sepa- proofs used for railway engineering, traffic engineering, and power rate components and more than 30 years’ experience. station engineering ĄĄ 19" subracks and housings with flexible internal layout Go to ĄĄ EMI- and RFI-shielded protection using stable stainless steel www.Intermas-US.com contact springs ensuring permanent and reliable bonding ĄĄ for our new catalog. Connectors and wiring accessories ĄĄ Customization available

vita.opensystemsmedia.com/p372664

Intermas US LLC  [email protected]  www.Intermas-US.com 800-811-0236

40 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R VME

6U VME COTS System - SIU6 Sensor Interface Unit esource Guide Customer-configurable The SIU6 is a highly configurable rugged COTS system or subsystem ideally FEATURES suited for military, industrial, and commercial applications that require ĄĄ 2 x 6U VME slots – allows installation of up to 12 I/O or high-density I/O, communications, Ethernet switching, and processing. The Communications modules • 40+ modules to choose from SIU6 leverages NAI field-proven, 6U VME boards to deliver off-the-shelf, ĄĄ SWaP-optimized COTS solutions that Accelerate Your-Time-to-Mission. SBC-less stand-alone operation supported via Ethernet connection to your mission computer Versatile Architecture ĄĄ ® ® ™ ™ ™ Processor options: NXP PowerPC QorIQ P2041, Intel Core i7, NAI’s Custom-On-Standard Architecture (COSA ) offers a choice of over Intel® Atom™ or ARM Cortex-A9 40 intelligent I/O, communications and Ethernet switch functions, as well ĄĄ MIL-STD-461F, MIL-STD-1275 & 704A as Single Board Computer (SBC) options. Pre-existing, fully tested functions can be quickly and easily combined in an unlimited number of ways to ĄĄ +28 VDC input meet system requirements. Individually dedicated I/O and communications ĄĄ Customer Configurable I/O, Communications and Processing processors allow mission computers to manage, monitor, and control the ĄĄ 11.75" W x 3.35" H x 8.65" D functions via single or dual Ethernet ports. Alternately, select one of NAI’s 6U ĄĄ Wind River® Linux/VxWorks®, Xilinx® PetaLinux, VME SBC options. Windows® Embedded Standard 7 OS Support All products are designed to operate under extreme temperature, shock, ĄĄ COSATM Architecture vibration, and EMI environments. EMI filters and gaskets meet or exceed ĄĄ Operating temperature: -40°C to +71°C Made in the USA MIL-STD-461F and MIL-STD-810G requirements. conduction cooled (air-cooled option) Certiﬁed Small Business Eliminate man-months of integration with a configured, field-proven 6U VME COTS System or Subsystem from NAI. vita.opensystemsmedia.com/p373448

North Atlantic Industries, Inc.  [email protected] http://www.naii.com/6U-VME-COTS-System-Sensor-Interface-Unit/P232  631-567-1100

VME

Schroff Backplanes and Systems Chassis from Pentair Based on VITA Standards

Pentair is proud to offer a full line of Schroff Backplane and Additionally, Pentair offers a full range of power supplies, chassis Systems Chassis products compliant to VITA specifications. Open components, cooling solutions and racking products to support VPX, VXS, VME64x and VME Bus based products are available your projects. Pentair offers board retainer and conduction off-the-shelf from the standard catalog. Custom and modified cooling products, including ejector handles and CCA clamshell products are expertly produced to your specifications using the assemblies. latest processes and materials. Services including design, simulation, testing as well as produc- Pentair offers the expertise to solve any chassis related challenges tion and supply chain logistics are available to support projects your project has to offer. Whether mechanical in nature or related from the initial specification phase through production and to cooling or chassis management and monitoring, Pentair has delivery anywhere in the world. decades of expertise bringing projects to success. Pentair has been Contact the experts at Pentair today to start your project on the a VITA member and active participant in specification and develop- path to success! ment for many years. vita.opensystemsmedia.com/p373449

Pentair/Schroff  [email protected]  http://www.pentairprotect.com/schroff-na 1-800-525-4682 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 41 VME esource Guide

cPCI, PXI, VME, Custom Packaging Solutions

VME and VME64x, CompactPCI, or PXI chassis are available in many configurations from 1U to 12U, 2 to 21 slots, with many power options up to 1,200 watts. Dual hot-swap is available in R Technologiess VITA AC or DC versions. We have in-house design, manufacturing capabilities, and in-process controls. All Vector chassis and backplanes are manufactured in the USA and are available with custom modifications and the shortest lead times in the industry.

Series 2370 chassis offer the lowest profile per slot. Cards are inserted horizontally from the front, and 80mm rear I/O backplane slot configuration is also available. Chassis are available from 1U, 2 slots up to 7U, 12 slots for VME, CompactPCI, or PXI. All chassis are IEEE 1101.10/11 compliant with hot-swap, plug-in AC or DC power options. FEATURES

Our Series 400 enclosures feature side-filtered air intake and rear ĄĄ Made in the USA exhaust for up to 21 vertical cards. Options include hot-swap, plug-in AC or DC power, and system voltage/temperature monitor. ĄĄ Most rack accessories ship from stock Embedded power supplies are available up to 1,200 watts.

Series 790 is MIL-STD-461D/E compliant and certified, economi- ĄĄ Modified ‘standards’ and customization are our specialty cal, and lighter weight than most enclosures available today. It is available in 3U, 4U, and 5U models up to 7 horizontal slots. ĄĄ Card sizes from 3U x 160mm to 9U x 400mm

All Vector chassis are available for custom modification in the ĄĄ System monitoring option (CMM) shortest time frame. Many factory paint colors are available and can be specified with Federal Standard or RAL numbers. ĄĄ AC or DC power input

ĄĄ Power options up to 1,200 watts For more detailed product information, please visit www.vectorelect.com or call 1-800-423-5659 and discuss your application with a Vector representative.

vita.opensystemsmedia.com/p371649

Vector Electronics & Technology, Inc.  [email protected] www.vectorelect.com  800-423-5659

42 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R VPX

VPX6000 Rugged 6U VPX Processor Blade esource Guide

The VPX6000 is a dual-CPU 4th generation Intel® Core™ i7 processor 6U VPX blade (0.85" pitch) with Mobile Intel® QM87 Chipset in a rugged conduction cooled, VPX REDI (VITA 48) form factor. The VPX6000 features two CPU sub-systems, each with up to 16GB DDR3-1600 FEATURES dual channel ECC memory soldered onboard, and onboard soldered ® ™ 32GB SLC SATA solid state drive. Rear I/O per node includes 2x 10GbE, ĄĄ Dual quad-core 4th generation Intel Core i7 processors 2x 1000BASE-BX and 2x 1000BASE-T, 2x PCIe x1, HD audio (Line-in, with ECC Line-out), 3x SATA 6 Gb/s, 2x USB 3.0, 2x USB 2.0, 8x GPIO, HDMI, ĄĄ Dual channel DDR3L ECC memory soldered, 16GB per node DVI and RS-232/422. ĄĄ Supports three independent displays A VPX-R6000 Rear Transition Module (RTM) is available to access ĄĄ Supports storage upgrade via mezzanine card rear I/O signals from the VPX6000, and a tBP-VPX6000 Test Back- plane supporting three payload slots is available for users to validate ĄĄ Offers remote management support VPX6000 functionality. ĄĄ Conduction-cooled and air-cooled versions available The VPX6000 Series is rugged, conduction-cooled with conformal coating, making it ideal for mission critical applications such as military and aerospace platforms. vita.opensystemsmedia.com/p373452

  ADLINK Technology [email protected] 800-966-5200 http://www.adlinktech.com www.linkedin.com/company/adlink-technology @ADLINKTech_usa

VPX

XMC-G745 Rugged XMC Module ADLINK recognizes the trend towards implementing General Purpose computing on Graphics Processing Units (GPGPU) for parallel computing and increased processing performance, and the XMC-G745M targets a variety of high-performance computing applications that can take advantage of this technology. FEATURES The rugged XMC-G745M module is equipped with the CUDA-enabled 384-core NVIDIA GeForce GT 745M GPU, utilizing NVIDIA Kepler ĄĄ NVIDIA GeForce GT 745M GPU (Kepler refresh) architecture and yielding unprecedented levels of graphics processing ĄĄ CUDA compute capability 3.0 for parallel computation and performance for defense and aerospace applications. The GeForce GT graphics processing 745M features 2048MB of GDDR5 memory, ensuring high-capacity and high-bandwidth access to data during massively parallel GPGPU ĄĄ Dual channel GDDR5 soldered memory, 2GB algorithm processing. ĄĄ PCIe x8 Gen3 on P15 The XMC module incorporates the VITA 42.0 XMC switched mezzanine ĄĄ High-resolution, high-performance platform for rugged video card auxiliary standard and the VITA 46.9 PMC/XMC/Ethernet signal I/O and GPGPU applications mapping on 3U/6U VPX module standard and supports both Windows and Linux operating systems. The GPU also supports OpenGL 4.4, ĄĄ Ideal for defense, radar, sonar, UAV and ground vehicles OpenCL 1.2 and DirectX 11, as well as High-bandwith Digital Content Protection (HDCP). vita.opensystemsmedia.com/p373451

  ADLINK Technology [email protected] 800-966-5200 http://www.adlinktech.com www.linkedin.com/company/adlink-technology @ADLINKTech_usa www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 43 VPX esource Guide

TR C4x/msd

TR C4x/msd is a 3U VPX™ board featuring the Intel® Xeon® Processor D-1500 family and up to 32GB of DDR4 ECC DRAM for high performance embedded computing applications. Concurrent Technologies are supporting variants based on 8, 12 and 16-core processors to suit application pro-

R Technologiess VITA files. TR C4x/msd has four SATA600 interfaces for external drives plus two SATA600 connections for on-board solid state disk options. For high speed FEATURES networking applications, two 10 Gigabit Ethernet data plane ports could be ĄĄ Intel® Xeon® processor D-1500 Family used either as a system ingress/egress point or for local data connectivity within the chassis. Two Gigabit Ethernet control plane ports are available on ĄĄ Up to 32 Gbytes of DDR4 DRAM the backplane and two optional Gigabit Ethernet ports are available on the ĄĄ On-board solid state drive (SSD) options front panel of air cooled boards. ĄĄ 2 x 10GBASE-KR Data Plane ® ® TR C4x/msd can also provide up to x16 PCI Express (PCIe ) lanes on the ĄĄ Up to x16 PCI Express® Gen 3 Expansion Plane expansion plane of the backplane with a theoretical bandwidth of 15.6GB/s. ĄĄ Air cooled and rugged conduction cooled variants These PCIe lanes enable point to point and small mesh configurations for ĄĄ high speed applications without the use of an additional switch module. Compliant with VITA 46.11 management

vita.opensystemsmedia.com/p373355

Concurrent Technologies  [email protected] http://www.cct.co.uk/sheets/TR/trc4xmsd.htm  +1 781 933 5900 or +44 1206 752626

VPX

AFT cooled 3U VPX COTS system

In support of the new VITA 48.8 Air Flow Through (AFT) cooling standard, Curtiss-Wright Defense Solutions has produced a range of 3U and 6U modules designed to bring the advanced cooling technology to rugged deployed embedded systems. During a presentation at VITA’s Embedded Tech Trends (ETT) 2016 sym- posium, Curtiss-Wright demonstrated the industry’s first functioning AFT chassis based on commercial-off-the-shelf (COTS) 3U VPX modules. The groundbreaking demo featured a 3D printed plastic chassis integrated FEATURES with Curtiss-Wright’s VPX3-1258 single board computer (SBC) and VPX3-716 graphics modules, both outfitted with AFT frames. ĄĄ Advanced cooling suitable for the highest power Intel CPU The first modules slated for use in VITA 48.8 AFT systems are ĄĄ Small form factor Curtiss-Wright’s VPX3-652, VPX3-1259, and VPX3-1258 SBCs and the VPX3-716 graphics module. The combination of advanced cooling, ĄĄ 3D printed chassis reduces weight small form factor AFT and reduced weight delivered by VITA 48.8 are of ĄĄ Wedgelock-free technology especial benefit for size, weight, power and cost (SWAP-C) constrained ĄĄ Low cost platforms such as rotorcraft and unmanned vehicles.

vita.opensystemsmedia.com/p373339

  Curtiss-Wright Defense Solutions [email protected] +1.703.779.7800 https://www.curtisswrightds.com www.linkedin.com/company/curtiss-wright-defense-solutions @curtisswrightds

44 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R VPX

Find out how we can help with your successful VPX designs. esource Guide

OpenVPX Systems FEATURES

Elma Electronic is the leader in OpenVPX (VITA 65) products and ĄĄ Chassis platforms technologies. Our engineering experts developed the industry‘s ĄĄ 3U & 6U OpenVPX backplanes first VPX backplane, and still actively participate in the VITA standards efforts. Elma has developed a sizable portfolio of ĄĄ Single board computers (SBCs) backplanes, platforms and embedded computing solutions. ĄĄ Ethernet Switches OpenVPX defines an easier way to ensure the interoper- ĄĄ High performance FPGA based I/O ability between VPX Modules from different vendors, and also ĄĄ Solid state storage and arrays compatibility between certain Slot configurations with similar VPX Modules. Elma Electronic‘s comprehensive design approach ĄĄ Modular I/O & imaging enables us to meet almost any application challenge. We ĄĄ Sub-system design & integration become an extension of your team, helping to design and select ĄĄ the elements that are best suited to the task. Rugged and thermal design & testing ĄĄ Lifecycle management Elma stays involved throughout the process for as long as you need us. This includes design, sourcing, testing and materials management. Open standards-based solutions enable us to offer expert solutions at reduced costs.

vita.opensystemsmedia.com/p373455

 [email protected]  510-656-3400 @elma_electronic Elma Electronic Inc. https://www.linkedin.com/company/elma-electronic http://www.elma.com/en/services/us-resources/architecture-overviews/system-solutions-openvpx-overview/ www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 45 VPX esource Guide

6U Universal Development Enclosure The 6U Universal Chassis/Backplane Assembly provides an ideal, customizable solution for open-standards-based application development. R Technologiess VITA Able to support 6U VPX, VME, CompactPCI, or custom backplanes, the enclosure provides between 2 and 21 slots FEATURES depending on the specific standard. ĄĄ Form factor: VPX, VME, CompactPCI, Custom ĄĄ Card size: 6U x 160mm ĄĄ Fabric/Profile: BKP6-CEN16-11.2.2-3 (shown) ĄĄ Cooling: Convection, forced air, bottom to top ĄĄ Input power: 85-264 VAC, 1/3 phase, 47-440 Hz (Optional DC input) ĄĄ Output power: 5/3.3/±12 V

vita.opensystemsmedia.com/p373332

  LCR Embedded Systems [email protected] 610-278-0840 www.lcrembeddedsystems.com www.linkedin.com/company/lcr-embedded-systems-inc- @LCREmbedded

VPX

CeeLok FAS-X Connectors

TE Connectivity’s CeeLok FAS-X connector combines rugged reliability with signal integrity to support current high-speed protocols and new, faster protocols on the horizon. The new FEATURES connector features fast field termination and repair, requiring ĄĄ Supports 10G Ethernet and other high-speed protocols only standard contact insertion/removal and crimping tools. ĄĄ Patented shielding arrangement shields each pair through the connector to provide improved impedance matching and to The CeeLok FAS-X connector meets military and aerospace eliminate crosstalk markets’ 10 GB/s requirements and other high-speed protocols ĄĄ Uses standard crimp AS39029 contacts such as IEEE 1394b I/O, Fibre channel networks and Modular ĄĄ Allows fast field termination and repair D38999 for harsh environment applications. Designed for ĄĄ Available with aluminum or composite shells with a variety of optimal signal integrity, the patented shielding arrangement finishes virtually eliminates crosstalk and completely isolates each pair ĄĄ Range of inserts for Size 25 shell to accommodate other through the connector to provide improved impedance. connectivity needs

vita.opensystemsmedia.com/p373335

 TE Connectivity 1-800-522-6752 www.te.com/highspeed www.linkedin.com/company/te-connectivity @TEConnectivity

46 | VITA Technologies Resource Guide Spring/Summer 2016 www.vita-technologies.com VITA Technologiess R VPX

MULTIGIG RT 2 and MULTIGIG RT 2-R Connectors

TE Connectivity’s (TE) portfolio of VPX systems gives you a complete array esource Guide for high-speed data, optical, RF, power, and mezzanine connectivity. More choice means more flexibility in achieving specific system architectures with standards-based solutions. Get the high-speed signal integrity advanced applications require in rugged, reliable connectors. FEATURES The MULTIGIG RT 2 connector, the standard for VITA 46, represents a huge step forward in the world of rugged computing and C4ISR enabling tech- ĄĄ MULTIGIG RT 2 connectors support speeds up to 10 Gb/s, providing nology. MULTIGIG RT 2-R connectors meet application needs beyond VITA 47 a comfortable performance margin in VPX applications environmental performance, while leveraging all the technical and economic ĄĄ Differential, single-ended, and power contacts benefits of VITA 46 VPX. ĄĄ Backplane connector system with “pinless” interface The modular connector system features a protected backplane connector and ĄĄ Customizable impedance-matched printed circuit wafer interface uses a pinless backplane and wafer-based design in place of pin contacts. ĄĄ Superior crosstalk performance Wafers, available for differential, single-ended, and power needs, can be ĄĄ easily modified to support specific customer needs for characteristic imped- Optimized footprints for signal integrity and ease of board design ance, propagation delay, and other electrical parameters. The connector ĄĄ Ultra-Rugged MULTIGIG RT 2-R Connectors: Quad-Redundant system also offers built in ESD features enabling field serviceability, is Contact System rather than the two points of the existing MULTIGIG extremely light weight and is fully qualified for VITA 47 environments. RT 2 connector. Increasing the points of redundancy increases reliability in a high vibration environment. MULTIGIG RT, TE Connectivity and TE connectivity (logo) are trademarks. VPX (logo) is a trademark of VITA. vita.opensystemsmedia.com/p372976

  TTI & TE Connectivity [email protected] 1-800-CALL-TTI http://www.ttiinc.com/object/te-vpx-clp.html www.linkedin.com/company/7150 @ttiinc.com

XMC/PMC

XU-TX xmc Two 5.1 GSPS 16-bit DACs Xilinx UltraScale

The XU-TX – an XMC module featuring two, AC-coupled, single-ended 16-bit DAC outputs with programmable DC bias. The DAC devices employed support synchronization and interpolation and their unique output circuits allow improved frequency synthesis in the 2nd and 3rd Nyquist zones, to shift of the Nyquist null frequency in the output spectrum by a factor of two. The DAC ICs may be clocked at up to 5.1 GHz via an onboard, ultra-low-jitter PLL. A unique feature of the PLL guarantees multi-board synchronization when supplied a 1/16th-rate external reference and trigger. FEATURES Sixteen high-speed serial links connect to the host (eight via XMC connector J15, ĄĄ Two 16-bit, > 5.1 GSPS DAC channels and eight via J16). 8000 MB/s PCIe gen3 and Aurora protocols, respectively are supported. ĄĄ Enhanced 2nd and 3rd Nyquist modes A Xilinx Kintex UltraScale XCVU060/085 FPGA lies at the heart of the prod- ĄĄ Up to 7800 MB/s streaming via PCIe or Aurora uct, supported with 8 GB DDR4 and 4 MB of QDRAM memory, providing a very ĄĄ Internal or external clocking high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog I/O, memory and host ĄĄ Internal or external triggering interface with the FPGA enables real-time signal processing at rates exceeding ĄĄ 7000 GMAC/s. Xilinx Kintex UltraScale FPGA XCKU060/085: Applications include: High Speed Arbitrary Wave Generation, Wireless MIMO ĄĄ 4 GB DDR4 DRAM in 2 banks each with 64 bit interface & up to transmitter, RADAR Waveforms, and Electronic Warfare. 38.4GB/s total bandwidth Download data sheets now! vita.opensystemsmedia.com/p373376

Innovative Integration  [email protected] www.innovative-dsp.com  805-383-8994 www.vita-technologies.com VITA Technologies Resource Guide Spring/Summer 2016 | 47 Got Tough Software Radio Design Challenges?

Unleash The New Virtex-7 Onyx Boards!

Pentek’s Onyx® Virtex-7 FPGA boards deliver unprece- With more than twice the resources of previous Virtex dented levels of performance in wideband communications, generations plus advanced power reduction techniques, SIGINT, radar and beamforming. These high-speed, the Virtex-7 family delivers the industry’s most advanced multichannel modules include: FPGA technology. • A/D sampling rates from 10 MHz to 3.6 GHz • D/A sampling rates up to 1.25 GHz Call 201-818-5900 or go to • Multi-bandwidth DUCs & DDCs www.pentek.com/go/vitaonyx • Gen3 PCIe with peak speeds to 8 GB/sec for your FREE online Putting • 4 GB SDRAM for capture & delay FPGAs to Work in Software • Intelligent chaining DMA engines Radio Handbook and Onyx • Multichannel, multiboard synchronization product catalog. ® • ReadyFlow Board Support Libraries ® • GateFlow FPGA Design Kit & Installed IP ® • GateXpress FPGA - PCIe configuration manager • OpenVPX, AMC, XMC, PCIe, cPCI, rugged, conduction cooled • Pre-configured development system for PCIe • Complete documentation & lifetime support

Pentek, Inc., One Park Way, Upper Saddle River, NJ 07458 • Phone: 201.818.5900 • Fax: 201.818.5904 • e-mail:[email protected] • www.pentek.com Worldwide Distribution & Support, Copyright © 2013 Pentek, Inc. Pentek, Onyx, ReadyFlow, GateFlow & GateXpress are trademarks of Pentek, Inc. Other trademarks are properties of their respective owners.

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