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Digital Design and Architecture

Teacher: Archit Verma Department :Computer Applications Course: B.Sc Semester: Second Semester Paper-1(Digital Logic Design and ) Units:1,2,3,4

References: Books • M. M. Mano, Digital Logic and Computer Design. • M. M. Mano, Computer System Architecture. UNIT-1 Boolean and Logic Gates Boolean Algebra

 Boolean Algebra is an algebra that deals with binary variables and logic operations. The variables are designated by letters such as A , B, x and y. The three logic operations are AND(.),OR(+) and NOT(‘).  A boolean can be expressed algebraically with binary variables ,that logic symbols , parenthesis and equal sign. For a given value of the variables , the can be either 1 or 0.

eg. F = x+ y’z

‘AND’ Logic Operation  AND is denoted by . Eg. F=x.y

In AND logic operation, the result is 1 if and only if both operands are 1, otherwise the result is 0

x y x.y 0 0 0 0 1 0 1 0 0 1 1 1 ‘OR’ Logic Operation  OR is denoted by . Eg. F=x+y

In OR ; the result is 1 if at least one of the two operands are 1, otherwise the result is 0.

x y x+y 0 0 0 0 1 1 1 0 1 1 1 1 ‘NOT’ Logic Operation  NOT is denoted by ‘ Eg. F=x’

NOT is an unary operator; the result is 1 if the operand is 0 or 0 if the operand is 1.

x x’ 0 1 1 0  The operator precedence for evaluating Boolean expression is  (1)parentheses  (2)NOT  (3)AND  (4)OR Laws in boolean algebra

Identity law x+0=x x.1=x

Idempotent law x+x=x x.x=x Cumulative law x+y=y+x x.y=y.x x+xy=x x(x+y)=x De-Morgan law (x+y)’=x’.y’ (x.y)’=x’+y’ Domination law x+1=1 x.0=0 Associative law (x+y)+z=x+(y+z) (x.y).z=x.(y.z) Distributive law x.(y+z)=x.y+x.z x+y.z=(x+y).(x+z) Involution law (x’)’=x law x + x’=1 x.x’=0

Truth table of function x y Z F=x+y’z 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Simplification of boolean functions to minimum of literals Find the complement of the following functions by applying De-morgan law More Logic Operations  NAND (↑) : x↑y = (x.y)’  NOR(↓): x↓y=(x+y)’  XOR(⊕): x ⊕y=x’.y+x.y’ ( XOR is pronounced as ) is a logic operation that gives HIGH output when the number of HIGH inputs is odd.)  XNOR(⊙): (X⊙Y)=(x⊕y)’=(x’.y+x.y’)’=(x’.y’+x.y) Logic Gates

Universal Gates  A universal gate is a gate which can implement any Boolean function without need to use any other gate type.  The NAND and NOR gates are universal gates.  In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. Implementation using NAND gate

Implementation using NOR gate XNOR Implementation of Expression Using NAND Gate

Implementation of Boolean Expression Using NOR Gate only

Minterm and Maxterm  Definition: a minterm of n variables is a product of the variables in which each appears exactly once in true or complemented form.  Definition: a maxterm of n variables is a sum of the variables in which each appears exactly once in true or complemented form.

Canonical SOP

x y Z F=x+y’z Minterm  Canonical SOP: Canonical s Sum of products , also called as 0 0 0 0 sum of minterms. Any boolean 0 0 1 1 m1=x’y’z function and by expresses as 0 1 0 0 sum of minterms. For the 0 1 1 0 1 0 0 1 m =x.y.’z’ function table, the minterms 4 1 0 1 1 m =x.y’z used are the terms 5 1 1 0 1 m =x.y.z’ corresponding to the 1's. 6 1 1 1 1 m7=x.y.z

Representation : F=x’y’z+x.y.’z’+x.y’z+x.y.z’+x.y.z F=∑(1,4,5,6,7) Canonical POS

 Canonical POS: Canonical x y z F=x+y’z Maxterms

Product of sums, also called as 0 0 0 0 M0=x+y+z Product of maxterms. Any 0 0 1 1

boolean function and by 0 1 0 0 M2=x+y’+z

expresses as Product of 0 1 1 0 M3=x+y’+z’ maxterms. For the function 1 0 0 1 table, the maxterms used are the 1 0 1 1 terms corresponding to the 0's. 1 1 0 1 1 1 1 1

Representation : F=(x+y+z).(x+y’+z).(x+y’+z’) F=∏(0,2,3) Express the following boolean function as (sum of minterms) and (product of maxterms) F=x.y+x’.z x y z F=x.y+x’.z minterms maxterms F=∑(1,3,6,7) F=∏(0,2,4,5) 0 0 0 0 M0=x+y+z

0 0 1 1 m1=x’y’z

0 1 0 0 M2=x+y’+z

0 1 1 1 m3=x’yz

1 0 0 0 M4=x’+y+z

1 0 1 0 M5=x’+y+z’

1 1 0 1 m6=xyz’

1 1 1 1 m7=xyz Algebraic Method of converting to SOP Simplification of Boolean Functions: Two Methods

▪ The algebraic method by using Identities ▪ The graphical method by using Karnaugh method ▪ The K-map method is easy and straightforward. ▪ A K-map for a function of n variables ▪ consists of 2n cells, and, ▪ in every row and column, two adjacent cells should differ in the value of only one of the logic variables. Further, each within a K-map has a definite place-value which is obtained by using an encoding technique known as Gray code. • Examples: Cell are written in the cells. • 2- K-map  3-variables K-map  4-variable K-map Steps to solve expression using K-map 1. Select K-map according to the number of variables. 2. Identify minterms or maxterms as given in problem. 3. For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere). 4. For POS put 0’s in blocks of K-map respective to the maxterms(1’s elsewhere). 5. Make rectangular groups containing total terms in power of two like 2,4,8 ..(except 1) and try to cover as many elements as you can in one . 6. From the groups made in step 5 find the product terms and sum them up for SOP form Or find the sum terms and multiply them up for POS form  F(A,B,)= ∑(1,3,6,7)

From red group we get product term: A’C From green group we get product term: AB So, Final expression: F= A’C+AB  F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)

From red group we get product term: QS From green group we get product term: Q’S’ Final expression: F(P,Q,R,S)= QS+ Q’S’  F(W,X,Y,Z) = ∑(0,1,2,4,5,7,10,15)  F = Σ (0, 4, 6, 8, 10, 15)

F = A’C'D’ + A’BD’ + AB’D’ + ABCD  F(P,Q,R,S) = ∑(0,3,5,7,10,11,12,13,14,15)

F=P’Q’R’S’+RS+PQ+QS+PR  F = Σ (0, 3, 4, 6, 7, 9, 12, 14, 15)

F = BD’ + BC + A’C'D’ + A’CD + AB’C'D

Example:

 F(A,B,C,D)= ∏(3,5,7,8,11,10,12,13)

Green : (C+D’+B’) Red : (C’+D’+A) Blue: (A’+C+D) Brown: (A’+B+C’) F=(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)  F= ∏(4,5,7,13,14,15)

F= (W+X’+Y). (W’+X’+Y’).(X’+Z’) F= ∏(3,4,6,7,11,12,13,14,15) F= ∏(1,3,5,7,8,9,10,11,12,13,14,15))

F=(A’).(D’)

F (A, B, C, D) = Σ (1, 4, 6, 7, 8, 9, 10, 11, 15). Final Answere: F = AB′ + B′C′D + A′BD′ + BCD UNIT-2 Combinational Circuits Sequential Circuits Circuit and Circuits

 Combinational Logic Circuits are memory less digital logic circuits whose output at any instant in time depends only on the combination of its inputs, unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory.

Design of combinational Logic circuit Adders Half  The of 2 is called Half adder the input variables are augend and addend bits and output variables are sum and carry bits. x and y are the two input bits.

x y sum carry Sum = x ⊕ y 0 0 0 0 Carry = x. y 0 1 1 0 1 0 1 0 1 1 0 1 Full Adder

Creating Full Adder Using two Half Adders Half

 A half-subtractor is a combinational circuit that subtract two bits and produces their difference .It also has an output to specify if a 1 had being borrowed. Designate the minuend by x, and the subtrahend bit as y.

x y D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

D = x ⊕ y B = x’ . y Full Subtractor

Decoder  Discrete quantities of information are represented by binary codes. A of n bits is capable of representing up to 2n distinct elements of coded information.  The name “Decoder” means to translate or decode coded information from one format into another, so a digital decoder transforms a of digital input signals into an equivalent decimal code at its output.  A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. table and logic diagram of 3-to-8 decoder Making 4-to-16 decoder using two 3-to-8 decoder Boolean function can be implemented using Decoder and an OR gate Encoder  An Encoder is a combinational circuit that performs the reverse operation of Decoder.  It has maximum of 2n input lines and ‘n’ output lines, hence it encodes the information from 2n inputs into an n-bit code. It will produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes 2n input lines with‘n’ bits

Priority Encoder  A priority encoder provide n bits of binary coded output representing the position of the highest order active input of 2n inputs. If two or more inputs are high at the same time, the input having the highest priority will take precedence.

Multiplexer

 Multiplexing means transmitting a large number of information units over a small number of channels or lines.  A digital (MUX) selects binary information from one of many input lines and directs it to a single output line.

Boolean function can be implemented using multiplexer Quadruple 2 to 1 line multiplexer De-Multiplexer  De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has single input, ‘n’ selection lines and maximum of 2n outputs. The input will be connected to one of these outputs based on the values of selection lines.  Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each combination can select only one output. De-Multiplexer is also called as De- Mux. 1-to-4 De-Mux Magnitude Comparator

Magnitude comparator Code Converter(Binary to Gray) g 0 g1

g3 g2 Binary to Gray and Gray to Binary Code converter Latches and Flip-Flop

A flip flop is an with two stable states that can be used to store . The stored data can be changed by applying varying inputs. RS-latch using Nor Gate

Truth table of RS latch RS-Flip flop RS flip flop using NAND gate only

Excitation table of RS Flip Flop D Flip-Flop

JK Flip Flop

Excitation Table of JK Flip Flop

T-Flip Flop

Race around condition in JK Flip Flop  In JK flip flop as long as clock is high for the input conditions J=1 and K=1. The output changes or complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing or race around condition. 

= propagation delay

Master Slave Flip Flop

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop. In addition to these two flip-flops, the circuit also includes an . The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for slave flip flop. Registers and Counters

Shift right then out

Counters State Diagram of Mod 8 counter Designing three bit counter using T Flop Flop

Ripple Counter A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.

Ripple Up Counter Three bit ripple up counter

Method-1 Method-II Method-III

Analysis of clocked sequential circuit  State table and state diagram UNIT-3 Basic Organization of CPU I/O Organization Block Diagram of digital computer

More block diagram

Examples: Von-Neumann Architecture: Desktop Personal Computer Harvard Architecture: (single-chip microcomputer)-based computer system, And DPS( )-based computer systems

Register transfer and micro-operations

What is bus?

CPU of a Digital Computer General Register organization

Stack Organization

Memory Stack Push

Pop

Design of basic computer Computer Instruction

Program Counter Timing and Control Hardwired and Micro programmed control unit

Instruction cycle  A program residing in the memory unit of a computer consists of a of instructions. These instructions are executed by the processor by going through a cycle for each instruction.  In a basic computer, each instruction cycle consists of the following phases: 1. Fetch instruction from memory. 2. Decode the instruction. 3. Read the effective address from memory. 4. Execute the instruction.  Fetch and Decode

Micro-programmed Control Unit

Micro programmed hardware configuration

 Fetch Routine:

CISC Characteristics RISC Characteristics

Addressing Modes  The operation of an instruction specifies the operation to be performed. This operation will be executed on some data which is stored in computer registers or the main memory. The way any operand is selected during the program execution is dependent on the addressing mode of the instruction. The purpose of using addressing modes is as follows: • To give the programming versatility to the user. • To reduce the number of bits in addressing field of instruction.

 Advantages 1. Shorter instructions and faster instruction fetch. 2. Faster memory access to the operand(s)  Disadvantages 1. Very limited address space 2. Using multiple registers helps performance but it complicates the instructions

Concept of effective address

Question

Question

Question Question

8085  A microprocessor is a computer processor that incorporates the functions of a on a single (IC), or sometimes up to 8 integrated circuits.

 Addition of two 8-bit numbers stored at memory location 2200 & 2201. And store the result at 2202. Basic instructions that we are going to use are LDA, MOV, ADD, STA. List of  The Intel 8008 is an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. It is an 8-bit CPU with an external 14-bit address bus that could address 16 KB of memory.  The Intel 8080 ("eighty-eighty") was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974.  It is an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock rate or frequency limit was 2 MHz, and with common instructions using 4, 5, 7, 10, or 11 cycles this meant that it operated at a typical speed of a few hundred thousand instructions per second. A faster variant 8080A-1 (Sometimes called the 8080B) became available later with clock frequency limit up to 3.125 MHz.  The Z80 is an 8-bit microprocessor introduced by as the startup company's first product.  The first working samples were delivered in March 1976, and it was officially introduced on the market in July 1976.  The is a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at embedded systems. Although used in that role, the Z80 also became one of the most widely used CPUs in desktop and home computers from the 1970s to the mid- 1980s.  8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.  8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and 16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily.  The 6800 is an 8-bit microprocessor designed and first manufactured by Motorola in 1974. The MC6800 microprocessor was part of the M6800 Microcomputer System that also included serial and parallel interface ICs, RAM, ROM and other support chips. A significant design feature was that the M6800 family of ICs required only a single five-volt power supply at a time when most other microprocessors required three voltages. The M6800 Microcomputer System was announced in March 1974 and was in full production by the end of that year.  The 6800 has a 16-bit address bus that can directly access 64 kB of memory and an 8-bit bi-directional data bus. It has 72 instructions with seven addressing modes for a total of 197 opcodes. The original MC6800 could have a clock frequency of up to 1 MHz. Later versions had a maximum clock frequency of 2 MHz. Input Output Organization

Devices:  The Input / output organization of computer depends upon the size of computer and the connected to it. The I/O Subsystem of the computer, provides an efficient mode of communication between the central system and the outside environment  The most common input output devices are: i) Monitor ii) Keyboard iii) Mouse iv) Printer v) Magnetic tapes  The devices that are under the direct control of the computer are said to be connected online. Input - Output Interface  Input Output Interface provides a method for transferring information between internal storage and external I/O devices.  Peripherals connected to a computer need special communication links for interfacing them with the central processing unit.  The purpose of communication link is to resolve the differences that exist between the central computer and each peripheral.  The Major Differences are:- 1. Peripherals are electromechnical and electromagnetic devices and CPU and memory are electronic devices. Therefore, a conversion of signal values may be needed. 2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU and consequently, a synchronization mechanism may be needed. 3. Data codes and formats in the peripherals differ from the word format in the CPU and memory. 4. The operating modes of peripherals are different from each other and must be controlled so as not to disturb the operation of other peripherals connected to the CPU. Connection to I/O bus to input-output devices  To Resolve these differences, computer systems include special hardware components between the CPU and Peripherals to supervises and synchronizes all input and output transfers.  These components are called Interface Units because they interface between the processor bus and the peripheral devices. I/O BUS and Interface Module  It defines the typical link between the processor and several peripherals.  The I/O Bus consists of data lines, address lines and control lines.  The I/O bus from the processor is attached to all peripherals interface.  To communicate with a particular device, the processor places a device address on address lines.  Each Interface decodes the address and control received from the I/O bus, interprets them for peripherals and provides signals for the peripheral controller.  It is also synchronizes the data flow and supervises the transfer between peripheral and processor.  Each peripheral has its own controller.

Isolated I/O  Then we have Isolated I/O in which we have common bus(data and address) for I/O and memory but separate read and write control lines for I/O. So when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read or write control line on due to which data transfer occurs between CPU and I/O. As the address space of memory and I/O is isolated and the name is so. The address for I/O here is called ports. Here we have different read-write instruction for both I/O and memory.

Memory Mapped I/O  In this case every bus in common due to which the same set of instructions work for memory and I/O. Hence we manipulate I/O same as memory and both have same address space, due to which addressing capability of memory become less because some part is occupied by the I/O.

Asynchronous data transfer Source-initiated strobe Destination-initiated strobe Source-initiated Handshaking technique Destination-initiated Handshaking technique Serial Asynchronous Transmission

Modes of transfer  The binary information that is received from an external device is usually stored in the memory unit. The information that is transferred from the CPU to the external device is originated from the memory unit. CPU merely processes the information but the source and target is always the memory unit. Data transfer between CPU and the I/O devices may be done in different modes.  Data transfer to and from the peripherals may be done in any of the three possible ways 1.)Programmed I/O. 2.)Interrupt- initiated I/O. 3.)Direct memory access( DMA).  Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is from a CPU register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices.

 Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be avoided by using an interrupt driven method for data transfer. By using interrupt facility and special commands to inform the interface to issue an interrupt request signal whenever data is available from any device. In the meantime the CPU can proceed for any other program execution. The interface meanwhile keeps monitoring the device. Whenever it is determined that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon detection of an external interrupt signal the CPU stops momentarily the task that it was already performing, branches to the service program to process the I/O transfer, and then return to the task it was originally performing.

 Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit.

 Bus Request : It is used by the DMA controller to request the CPU to relinquish the control of the buses.  Bus Grant : It is activated by the CPU to Inform the external DMA controller that the buses are in high impedance state and the requesting DMA can take control of the buses. Once the DMA has taken the control of the buses it transfers the data.  Types of DMA transfer using DMA controller:  Burst Transfer : DMA returns the bus after complete data transfer. A register is used as a byte count , being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus.  Cycle Stealing : An alternative method in which DMA controller transfers one word at a time after which it must return the control of the buses to the CPU. The CPU delays its operation only for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle. DMA Transfer

Question Question UNIT-4 Memory Organization

Speed Storage

Coincidental decoding

Question

Question Associative memory

 Example:

Locality of reference

Example of cache memory

Question  The access time of cache memory is 100 ns and that of main memory 1000 ns. It is estimated that 80% of the memory requests are for read and the remaining 20% for write. The hit ratio for read access only is 0.9. A write -through procedure is used. a.)what is the average access time of the system considering only memory read cycles? b.)what is the average access time of the system for both read and write requests? c.)what is the hit ratio taking into consideration the write cycles?

Question  A digital computer has a memory of 64k x 16 and a cache memory of 1k words. The cache uses direct mapping with a block size of four words. a. )How many bits are there in the tag, index, block and word fields of the address format? b.) How many bits are there in each word of cache, and how they are divided into functions? Include a valid bit. c.)How many blocks can the cache accommodate? Question  A two-way set-associative cache memory uses blocks of four words. The cache can accommodate a total of 2048 words from the main memory. The main memory size is 128K x 32. 1. Formulate all pertinent information required to construct Cache Memory? 2. What is the size of the cache memory? Virtual Memory

Question An address space is specified by 24bit and the corresponding memory space is 16 bit. a.)How many words are there in address space? b.)How many words are there in memory space? c.)If a page consists of 2K words , how many pages and blocks are there in the system? Question

Segmentation

Question What is Interleaved Memory?  It is a technique for compensating the relatively slow speed of DRAM(Dynamic RAM). In this technique, the main memory is divided into memory banks which can be accessed individually without any dependency on the other.  For example: If we have 4 memory banks(4-way Interleaved memory), with each containing 256 bytes, then, the Block Oriented scheme(no interleaving), will assign virtual address 0 to 255 to the first bank, 256 to 511 to the second bank. But in Interleaved memory, virtual address 0 will be with the first bank, 1 with the second memory bank, 2 with the third bank and 3 with the fourth, and then 4 with the first memory bank again.  Hence, CPU can access alternate sections immediately without waiting for memory to be cached. There are multiple memory banks which take turns for supply of data.  Memory interleaving is a technique for increasing memory speed. It is a process that makes the system more efficient, fast and reliable.  For example: In the above example of 4 memory banks, data with virtual address 0, 1, 2 and 3 can be accessed simultaneously as they reside in separate memory banks, hence we do not have to wait for completion of a data fetch, to begin with the next. Swapping  Swapping is a mechanism in which a process can be swapped temporarily out of main memory (or move) to secondary storage (disk) and make that memory available to other processes. At some later time, the system swaps back the process from the secondary storage to main memory.

Relocation  Relocation is to find a way to map virtual addresses into physical addresses. Depending on when and how the mapping from the virtual address space to the physical address space takes place in a given relocation scheme.  Relocatability - the ability to move process around in memory without it affecting its execution. 1. OS manages memory, not programmer, and processes may be moved around in memory 2. MM must convert program's logical addresses into physical addresses  Static Relocation - Static relocation refers to address transformations being done before execution of a program begins.  Dynamic Relocation - Dynamic relocation refers to address transformations being done during execution of a program.