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Digital Logic Design and Computer Architecture

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Digital Logic Design and Computer Architecture Digital Logic Design and Computer Architecture Teacher: Archit Verma Department :Computer Applications Course: B.Sc Semester: Second Semester Paper-1(Digital Logic Design and Computer Architecture) Units:1,2,3,4 References: Books • M. M. Mano, Digital Logic and Computer Design. • M. M. Mano, Computer System Architecture. UNIT-1 Boolean algebra and Logic Gates Boolean Algebra Boolean Algebra is an algebra that deals with binary variables and logic operations. The variables are designated by letters such as A , B, x and y. The three logic operations are AND(.),OR(+) and NOT(‘). A boolean function can be expressed algebraically with binary variables ,that logic operation symbols , parenthesis and equal sign. For a given value of the variables , the boolean function can be either 1 or 0. eg. F = x+ y’z ‘AND’ Logic Operation AND is denoted by . Eg. F=x.y In AND logic operation, the result is 1 if and only if both operands are 1, otherwise the result is 0 x y x.y 0 0 0 0 1 0 1 0 0 1 1 1 ‘OR’ Logic Operation OR is denoted by . Eg. F=x+y In OR binary operation; the result is 1 if at least one of the two operands are 1, otherwise the result is 0. x y x+y 0 0 0 0 1 1 1 0 1 1 1 1 ‘NOT’ Logic Operation NOT is denoted by ‘ Eg. F=x’ NOT is an unary operator; the result is 1 if the operand is 0 or 0 if the operand is 1. x x’ 0 1 1 0 The operator precedence for evaluating Boolean expression is (1)parentheses (2)NOT (3)AND (4)OR Laws in boolean algebra Identity law x+0=x x.1=x Idempotent law x+x=x x.x=x Cumulative law x+y=y+x x.y=y.x Absorption law x+xy=x x(x+y)=x De-Morgan law (x+y)’=x’.y’ (x.y)’=x’+y’ Domination law x+1=1 x.0=0 Associative law (x+y)+z=x+(y+z) (x.y).z=x.(y.z) Distributive law x.(y+z)=x.y+x.z x+y.z=(x+y).(x+z) Involution law (x’)’=x Complement law x + x’=1 x.x’=0 Truth table of function x y Z F=x+y’z 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Simplification of boolean functions to minimum number of literals Find the complement of the following functions by applying De-morgan law More Logic Operations NAND (↑) : x↑y = (x.y)’ NOR(↓): x↓y=(x+y)’ XOR(⊕): x ⊕y=x’.y+x.y’ ( XOR is pronounced as Exclusive OR) is a logic operation that gives HIGH output when the number of HIGH inputs is odd.) XNOR(⊙): (X⊙Y)=(x⊕y)’=(x’.y+x.y’)’=(x’.y’+x.y) Logic Gates Universal Gates A universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates. In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. Implementation using NAND gate Implementation using NOR gate XNOR Implementation of Expression Using NAND Gate Implementation of Boolean Expression Using NOR Gate only Minterm and Maxterm Definition: a minterm of n variables is a product of the variables in which each appears exactly once in true or complemented form. Definition: a maxterm of n variables is a sum of the variables in which each appears exactly once in true or complemented form. Canonical SOP x y Z F=x+y’z Minterm Canonical SOP: Canonical s Sum of products , also called as 0 0 0 0 sum of minterms. Any boolean 0 0 1 1 m1=x’y’z function and by expresses as 0 1 0 0 sum of minterms. For the 0 1 1 0 1 0 0 1 m =x.y.’z’ function table, the minterms 4 1 0 1 1 m =x.y’z used are the terms 5 1 1 0 1 m =x.y.z’ corresponding to the 1's. 6 1 1 1 1 m7=x.y.z Representation : F=x’y’z+x.y.’z’+x.y’z+x.y.z’+x.y.z F=∑(1,4,5,6,7) Canonical POS Canonical POS: Canonical x y z F=x+y’z Maxterms Product of sums, also called as 0 0 0 0 M0=x+y+z Product of maxterms. Any 0 0 1 1 boolean function and by 0 1 0 0 M2=x+y’+z expresses as Product of 0 1 1 0 M3=x+y’+z’ maxterms. For the function 1 0 0 1 table, the maxterms used are the 1 0 1 1 terms corresponding to the 0's. 1 1 0 1 1 1 1 1 Representation : F=(x+y+z).(x+y’+z).(x+y’+z’) F=∏(0,2,3) Express the following boolean function as (sum of minterms) and (product of maxterms) F=x.y+x’.z x y z F=x.y+x’.z minterms maxterms F=∑(1,3,6,7) F=∏(0,2,4,5) 0 0 0 0 M0=x+y+z 0 0 1 1 m1=x’y’z 0 1 0 0 M2=x+y’+z 0 1 1 1 m3=x’yz 1 0 0 0 M4=x’+y+z 1 0 1 0 M5=x’+y+z’ 1 1 0 1 m6=xyz’ 1 1 1 1 m7=xyz Algebraic Method of converting to SOP Simplification of Boolean Functions: Two Methods ▪ The algebraic method by using Identities ▪ The graphical method by using Karnaugh Map method ▪ The K-map method is easy and straightforward. ▪ A K-map for a function of n variables ▪ consists of 2n cells, and, ▪ in every row and column, two adjacent cells should differ in the value of only one of the logic variables. Further, each cell within a K-map has a definite place-value which is obtained by using an encoding technique known as Gray code. • Examples: Cell numbers are written in the cells. • 2-variable K-map 3-variables K-map 4-variable K-map Steps to solve expression using K-map 1. Select K-map according to the number of variables. 2. Identify minterms or maxterms as given in problem. 3. For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere). 4. For POS put 0’s in blocks of K-map respective to the maxterms(1’s elsewhere). 5. Make rectangular groups containing total terms in power of two like 2,4,8 ..(except 1) and try to cover as many elements as you can in one group. 6. From the groups made in step 5 find the product terms and sum them up for SOP form Or find the sum terms and multiply them up for POS form F(A,B,C)= ∑(1,3,6,7) From red group we get product term: A’C From green group we get product term: AB So, Final expression: F= A’C+AB F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15) From red group we get product term: QS From green group we get product term: Q’S’ Final expression: F(P,Q,R,S)= QS+ Q’S’ F(W,X,Y,Z) = ∑(0,1,2,4,5,7,10,15) F = Σ (0, 4, 6, 8, 10, 15) F = A’C'D’ + A’BD’ + AB’D’ + ABCD F(P,Q,R,S) = ∑(0,3,5,7,10,11,12,13,14,15) F=P’Q’R’S’+RS+PQ+QS+PR F = Σ (0, 3, 4, 6, 7, 9, 12, 14, 15) F = BD’ + BC + A’C'D’ + A’CD + AB’C'D Example: F(A,B,C,D)= ∏(3,5,7,8,11,10,12,13) Green : (C+D’+B’) Red : (C’+D’+A) Blue: (A’+C+D) Brown: (A’+B+C’) F=(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’) F= ∏(4,5,7,13,14,15) F= (W+X’+Y). (W’+X’+Y’).(X’+Z’) F= ∏(3,4,6,7,11,12,13,14,15) F= ∏(1,3,5,7,8,9,10,11,12,13,14,15)) F=(A’).(D’) F (A, B, C, D) = Σ (1, 4, 6, 7, 8, 9, 10, 11, 15). Final Answere: F = AB′ + B′C′D + A′BD′ + BCD UNIT-2 Combinational Circuits Sequential Circuits Combinational Logic Circuit and Sequential Logic Circuits Combinational Logic Circuits are memory less digital logic circuits whose output at any instant in time depends only on the combination of its inputs, unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory. Design of combinational Logic circuit Adders Half Adder The addition of 2 bits is called Half adder the input variables are augend and addend bits and output variables are sum and carry bits. x and y are the two input bits. x y sum carry Sum = x ⊕ y 0 0 0 0 Carry = x. y 0 1 1 0 1 0 1 0 1 1 0 1 Full Adder Creating Full Adder Using two Half Adders Half Subtractor A half-subtractor is a combinational circuit that subtract two bits and produces their difference .It also has an output to specify if a 1 had being borrowed.
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