Eindhoven University of Technology MASTER Embedded Sensing Platform for Smart Urban Spaces Garza Salas, A
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January 1977 I
CALIFORNIA STATE UN:::VERSITY, NORTHRIDGE HICROPROCESSORS / A graduate p~ojc~t report s~~oitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering .. I by Thor,las Carson Hecht ~- .January 1977 i The graduate project report of Thomas Carson Hecht is approved: California State University, Northridge Oitober 1976 ii TABLE OF CONTENTS TITLE PAGE i. 1-.PPROVAL PAGE i.i LIST OF FIGURES i.v ABSTRP.C'I' vii INTRODUCTION 1 INTRODUCTION 1'0 MICROPROCESSORS 3 THE 6800 HINIHAL SYSTEM 7 THE HICROCOMPUTER ... , .. ,~ .. c•<~c•••••••••••••,.tt•••••••.••,•·•••••-~~·•'~••oo 18 }!ICROELECTRONIC P.ESISTOiZS AND RESISTOR TRH'lMING 31 AJ!FL ICATT.O!'·! OF THE HICROCOI'-1PUTER TO LASER TRIH~llNG R),DJIR ERRORS AND THEIR CORRECTION 65 THE ERROR COF,RECI'TON SYSTEM •••••••c••••.,••••••••••••••• .. •-ta•••••·• 69 THE HICROPROCESSOR SYSTEN 34 LIHJ.TATWNS AND ACCURACY 97 SUNNARY 100 APPENDIX A 6800 IN.~)J'RUC.TIO.N S.&T •••••••••••••••••••• 102 APPEND IX E HOTOIWLA 6800 .CI.ROJ LTS -t.~ ...... ~ ... , ............. ~ ............... 105 lJ:'FENDIX C C.ALCJJL.A.TOR .CHIP DATA SH.EET •• , , .•••• , .•••.•••••••••••• llO 'I + .. .;:,. .. t •· II " • • • 115 BIBLlOGR.t,PHY ••••••••• otto'W ...... ll9 Li.i LIST OF FIGURES FIGURE 1: THE 6800 Mli'Hr·L'\L SYSTEH FIGURE 2: OPERATION OF THE ACIA FIGURE 3: OPERATION OF THE PIA FIGURE Lf: BLOCK DIAGRP..H OF THE PIA/CALCULATOR CHIP INTERFACE FIGURE 5: SCHEHATIC AND TRUTH TABLE OF THE PRIOP.ITY ENCODER FIGURE 6: SCHElv!ATIC OF THE QUAD AND FIGURE 7: SCHEHATIC OF 'I'JIE TNTERRUPT PRIORITY CIRCUIT FIGURE 8: LOCATIONS ADDRESSED BY THE MPU FOR DIFFERENT PRIORITY Ii'fTERlWPTS FIGURE 9: .tv1EHORY H1\P OF THE MICROCOl1PUTER FIGURE 10: CALCULATION OF RESISTANCE USING SQUARES AND SHEET RESISTANCE FIGURE 11: DIFFERENT TYPES OF TRIHS FIGURE 12: RESISTANCE AS A FUNCTION OF TRHllviiNG FIGURE 13: PLOT OF % OF INCREASE IN RESISTANCE VS. -
Computer Architectures
Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative .. -
Qorivva MPC5604P Microcontroller Data Sheet
Freescale Semiconductor Document Number: MPC5604P Data Sheet: Technical Data Rev. 8, 07/2012 MPC5604P 144 LQFP 100 LQFP 20 mm x 20 mm 14 mm x 14 mm Qorivva MPC5604P Microcontroller Data Sheet • Up to 64 MHz, single issue, 32-bit CPU core complex — 1 safety port based on FlexCAN with 32 message (e200z0h) objects and up to 7.5 Mbit/s capability; usable as — Compliant with Power Architecture embedded second CAN when not used as safety port category — 1 FlexRay™ module (V2.1) with selectable dual or — Variable Length Encoding (VLE) single channel support, 32 message objects and up to • Memory organization 10 Mbit/s — Up to 512 KB on-chip code flash memory with ECC • Two 10-bit analog-to-digital converters (ADC) and erase/program controller — 2 × 15 input channels, 4 channels shared between the — Optional 64 (4 × 16) KB on-chip data flash memory two ADCs with ECC for EEPROM emulation — Conversion time < 1 µs including sampling time at — Up to 40 KB on-chip SRAM with ECC full precision • Fail safe protection — Programmable Cross Triggering Unit (CTU) — Programmable watchdog timer — 4 analog watchdogs with interrupt capability — Non-maskable interrupt • On-chip CAN/UART bootstrap loader with Boot Assist — Fault collection unit Module (BAM) • Nexus L2+ interface •1 FlexPWM unit • Interrupts — 8 complementary or independent outputs with ADC — 16-channel eDMA controller synchronization signals — 16 priority level controller — Polarity control, reload unit • General purpose I/Os individually programmable as input, — Integrated configurable dead time -
Qoriq: High End Industrial and Networking Processing
TM TechDays 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, trademarks of Freescale Semiconductor, Inc. All other product or service names are the BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, TM property of their respective owners. © 2012 Freescale Semiconductor, Inc. 1 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All . other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. 2013 2011 QorIQ Qonverge QorIQ next-generation platform launch platform based T series 28nm on Layerscape architecture 2008 QorIQ Multicore Platform launch (P series) Accelerating the P series 45nm Network’s IQ 2004 Dual-core -
ED135388.Pdf
DOCUMENT RESUME ED 135 388 IB 004 499 AUTHOR Kirby, Paul J.; Gardner, Edward M. Tin! Microcomputer Controlled, interactive Testing Terminal Development. INSTITUTION Air Force Human Resources lab., Lowry AFB, Colo. Technical Training Div. SPONS AGENCY Air Force Human Resources Lab., Brooks AFB, Texas. REPORT NO AIHEI-TR-76-66 PUB DATE Oct 76 NOTE 27p. EDRS PRICE MF-$0.83 HC-$2.06 Plus Postage. DESCRIPTORS Autcinstructional Aids; Computer Programs; *Computer Science; *Individual Tests; Man Machine Systems; Self Pacing Machines; *Testing; *Test Scoring Machines IDENTIFIERS Microcomputers ABSTRACT The evolution of a self-contained test scoring terminal is presented. The rationale for thedesign is presented along with an evolutionary description ofthe requirements for the system. The sequence of software andhardware tools, which were developed in order to build the device, are alsodescribed in this report. The resulting device,which contains an imbedded microcomputer is functionally described and the testingstrategies which it cur.rently supports axe presented.(Author) *********************************************************************** * Dcraents acquired by ERIC include many informalunpublished * *materls not available from other sources. ERICmakes every effort * *to obtain tbe best copyavailable. Nevertheless, items of marginal * *reproducibility are often encountered andthis affects the quality * *of the microfiche and hardcopyxeproductions ERIC makes available * *via the ERIC Document ReproductionService (EDRS). EDRS is not * *responsible -
Technician's Guide to 68HC11 Microcontroller.Pdf
chapter 1 Introduction to Computer Hardware Objectives I ntr odu ct ion to Com put er H ardw are After completing this chapter, you should be able to: ◗ Describe the fundamental elements of every computer system: proces- sor, memory, and input/output ◗ Compare elements of the HC11 block diagram to the fundamentals of every computer system ◗ Describe the use of busses to connect computer elements ◗ Explain the three major functional units of a processor ◗ Illustrate the typical registers inside the processor ◗ List the HC11 processor registers ◗ Discuss the HC11 processor modes ◗ Compare and contrast various memory types ◗ Describe the on-chip memory of the HC11 ◗ Specify input/output functions present on most computers ◗ Use some basic BUFFALO commands to control the EVBU Outline ◗ 1.1 Elements of Every Computer ◗ 1.2 Elements of Processors ◗ 1.3 Introduction to Memory ◗ 1.4 Memory Types ◗ 1.5 Input/Output 1 ◗ 1.6 EVBU/BUFFALO Technician’s Guide to the 68HC11 Microcontroller Introduction Computer systems have been developed for a variety of functions and purposes. General-application desktop machines are the most common. They run a variety of software applications, such as word processing, financial management and data processing. They have all but replaced the typewriter as a necessary business tool. Computers are also present in automobiles, appliances, airplanes and all types of controllers and electromechanical devices. Despite the differences among these computer systems, they all share fundamental components and design. The purpose of this chapter is to provide an understanding of the fundamental components of a computer system. A conceptual presentation regarding the elements of every computer system is made with sufficient detail to establish a foundation for these concepts. -
When Reliability, Safety and Security Matter, Trust Power Architecture® Technology
When Reliability, Safety and Security Matter, Trust Power Architecture® Technology freescale.com 25 Years of Innovation Power Architecture® technology offers solutions automotive markets. To illustrate this leadership, Power from the smallest MCU used in automobiles to the Architecture technology is found in more than half of all cars highest performance chips for applications like data manufactured worldwide. It processes the vast majority networks and supercomputers. Initially developed by of all email, phone calls and multimedia downloads over IBM, Motorola and Apple over 25 years ago, Power the Internet. Jumbo jets, unmanned defense systems and Architecture technology has become the preferred platform water treatment plants use it for reliable operation under for many mission-critical and long-lived applications the harshest conditions. Banks trust it with your money and within the military, aerospace, networking, industrial and hospitals trust it for life-critical applications. Freescale Applications Built on Power Architecture Technology Healthcare Aerospace and Defense Smart Energy Industrial Automation Automotive and Control Home Automation Networking 2 We offer the largest portfolio of processors built ensure customer processor investments remain Our Power Architecture portfolio is noted for on Power Architecture technology, as well as backward- and forward-compatible, helping its high quality and very low parts per million the broadest scalability of any architecture, with reduce development and support costs. (PPM) defects. Because industrial, healthcare, single-, dual- and multicore performance from networking and automotive applications ship Continuous innovation develops more intelligent 100 to 50,000+ million instructions per second for many years after launch, and need long- and cost-effective solutions. System size and (MIPS). -
ICCAD 2014 TCAD to EDA Workshop November 2, 2014
TM ICCAD 2014 TCAD to EDA Workshop November 2, 2014 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. • Digital and AMS ICs (Si) • RF/mmWave (III/V) • Physically based models • Numerical models (table; ANN) • Flexible for diverse needs • Parameter extraction is easy − scalable over geometry − scalable over temperature § including self-heating − can model global variability § including physical correlations − can model mismatch − retargetable if process shifts Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor , 3rd ed., 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. -
FSL Small Cell Roadmap
Freescale Powering Innovation TM Post-Mobile Era Internet of Thing (IOT) Kwok Wu, PhD Head, Embedded Software and Systems Freescale Semiconductor Mobile Internet Access Post-PC Era Oct 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. • Motivation − Machine-to-Machine (M2M) & Internet of Things (IOT) − Wireless sensor network (WSN) . Zigbee, Wifi PAN . WiDi – WiFi Direct – streams HD1080p & 5.1 Surround sound (Wireless HDMI) • Power Efficiency: Standard based IP platform • IOT & Wireless Smart Gateways Applications • Smart Energy: Smart Grid (NAN) and Smart Connected Home (HAN) • Smart health monitoring, Safety/security • Smart connected cars, transportation/Logistics • Sustainable Living • Summary – Internet of Everything (IOE) Confidential and Proprietary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, TM 2 MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. -
Qorivva MPC5553 Family
Color Indicator Bar/Volume no. Power Architecture® 32-bit Microcontroller Fact Sheet Qorivva MPC5553 Family Targeted at mid-range engine management Qorivva MPC5553 Block Diagram applications and industrial uses cases requiring complex, real-time control, the Qorivva MPC5553 is a 32-bit microcontroller that offers 1.5 MB of flash, 64 KB SRAM, FEC and up to 132 MHz of performance. The Qorivva MPC5553 helps you face the dual pressures of controlling costs while designing for increasingly complex applications. The Qorivva MPC5553 offers a migration path from the market-leading MPC500 family of 32-bit MCUs, facilitating reuse of legacy software architectures. Applications e200z6 Core Built on • Multi-point fuel injection control Power Architecture® Technology • Electronically controlled transmissions • Direct diesel injection (DDI) • Gasoline direct injection (GDI) • Avionics System I/O • High-end motion control • An enhanced time processor unit (eTPU) • 40-ch. dual Enhanced queued analog-to- with 32 I/O channels and 14.5 KB of digital converter (eQADC)—up to 12-bit • Military designated SRAM resolution and up to 1.25 ms conversions, • Heavy industries • 32-ch. enhanced direct memory access six queues with triggering and DMA support (eDMA) controller • Three deserial serial peripheral interface Features • Interrupt controller (INTC) capable of (DSPI) modules—16 bits wide up to six chip Freescale’s e200z6 Core handling 212 selectable-priority selects each • High-performance 132 MHz 32-bit interrupt sources • Two controller area network (CAN) modules Book E-compliant core built on Power • Frequency modulated phase-locked loop with 64 buffers each Architecture® technology (FMPLL) to assist in electromagnetic • Two enhanced serial communication • Memory management unit (MMU) with interference (EMI) management interface (eSCI) modules 32-entry fully associative translation • MPC500 compatible external bus interface • 24-ch. -
Freescale Qoriq P4080 DMA-DDR Performance Analysis
TM Wai Chee Wong Sr.Member of Technical Staff Freescale Semiconductor Raghu Binnamangalam Sr.Technical Marketing Engineer Cadence Design Systems Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. DAC 2013, Austin, TX • Company Overview • Use of emulation at Freescale • Palladium usage for emulation model under test • Performance case studies • Experiences using Palladium system • Summary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. • Global leader in embedded -
Freescale Qoriq Product Family Roadmap
TM April 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • Freescale Differentiation and Roadmap • Power Architecture and ARM® Technology Roadmap • Product Summaries • IP Deep Dive on DDRC, PEX, Ethernet • Application Example TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, 2 Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor,