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• Established in Sept. 2005 Designing • Design Expertise: – Crystal Oscillators OilltOscillators – Phase Locked Loops – General Analog/Mixed Signal Design • Dale Nelson Dale Nelson, Ph.D. – Ph.D. in Electrical Engineering from Purdue Univ. DHN Integrated Circuit Design – Over 27 patents – Worked for ÆLucent Æ AgereAgere,, and Innovative Wireless Technologies – Adjunc t Pro fessor at th e U ni vers ity o f P ennsyl vani a

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DHN Integrated Circuit Design Crystal Oscillators Mandatory Organization Chart • Found in almost all electronic devices: Owner – Disk drives Dale Nelson – mother boards – Telephones – Cell phones – , Design Team – , Chief Scientist Business Manager – CffCoffee M Mkakers Dale Nelson Dale Nelson Dale Nelson Dale Nelson – Uninteruptible Power Supplies (UPS) Dale Nelson – Electric Toothbrushes

30-Nov-2009 DHN Integrated Circuit Design 3 30-Nov-2009 DHN Integrated Circuit Design 4 U.P.S. Board in UPS Crystal on other side of board in this area

Crystal

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Electric Toothbrush Electric Toothbrush Crystal

30-Nov-2009 DHN Integrated Circuit Design 7 30-Nov-2009 DHN Integrated Circuit Design 8 Why use a crystal? Crystal “Q” “Q” Value Ranges • Accuracy with respect to: – Temperature RC passive circuit 00--0.50.5 – Supply IC Ind uc tors 4-25 – Time (Aging) Golf ball 10 • Qualit y F act or “Q” Discrete 2020--10001000 Energy stored during a cycle Q=2Q = 2 π Church B ell 5000 Energy lost during a cycle 10k10k--3M3M

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Basic Gate Start Up BiGBasic Gate CCystarystal Oscillator

30-Nov-2009 DHN Integrated Circuit Design 11 30-Nov-2009 DHN Integrated Circuit Design 12 Crystal Oscillator Transient Basic Gate Oscillator Steady State Simulations • Good for: – Determining signal amplitude, duty cycle – Crystal Drive Level (power dissi pation of cr ystal ) – Start up characteristics (start up time???) – Chewing up lots of computer simulation time • Does NOT tell much about: – Margins over PVT (Process, Volt age, T emperat ure) – Useful range of design – Why your ci rcu it does no t wor k

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Crystal Oscillator Transient Crystal Oscillator Transient Simulation Suggestions Simulation Suggestions (cont) • Select “Options” in AnalysisÆChoose ““trantran”” • I like to use the “Enable” input to start the – Use “traponly“traponly”” simulation with the oscillator “off”, and then ––SetSet “maxstep“maxstep”” to ~1% of target period turn it “on” . • For fast starting, you may need to set an “initial • Some have used a pulsed current source condition” on the “1LC” node in the crystal modldel. across the crystal to start. – In ADE window: SimulationÆConvergence Aids… • Turning on “transient ” for the ““trantran”” opens “Select Initial Condition Set” simulation can be useful if you want to – Set so some current flows through the start at DC “on” equilibrium, high Q. .

30-Nov-2009 DHN Integrated Circuit Design 15 30-Nov-2009 DHN Integrated Circuit Design 16 Cryypstal Specifications Crystal Information • Typically, Crystal Manufacturers provide: – Fundamental or Overtone () • Typical Data Sheets do NOT include: – Target Frequency at a specified CLOAD – All Crystal Equivalent Circuit Parameters – Target Frequency accuracy (in ppm)ppm) – Q value or range – Maximum ESR (Effective Series Resistance) – Maximum C – Any information about overtones for SHUNT fundamental mode crystals – Maximum Drive Level – Temperature Range, ∆ppm over temperature, or a – Any information about fundamental mode for plot of frequency versus temperature overtone crystals – Mechanical information for mounting to PWB • Sometimes you can get more information – Other information ppgertinent to manufacturing such as by contacting the manufacturer. soldering temperature information

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Fundamental and 3rd Harmonic Typical Crystal Model Crystal Model

Parameters: cshunt, fs1, esr1, and q1 Parameters: cshunt, fs1, esr1, q1, fs3, esr3, and q3

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Third Fundamental Harmonic

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Crystal Reactance Crystal Tuning

• Crystals are “Tuned” to a particular frequency tolerance for a specified CloadCload..

)) – Can be “Series” tuned or “Parallel” Tuned Ω – Since a Gate oscillator works in the “Parallel ance (k tt ” region, you normally want

Reac “Parallel Tuned” crystals

30-Nov-2009 DHN Integrated Circuit Design 23 30-Nov-2009 DHN Integrated Circuit Design 24 Crystal C LOAD Reactance Plot with C LOAD

• CLOAD specification: – Represents tuning fixture plus

added parallel capacitance across crystal. ) Ω – Larger CLOAD provides better immunity (less nce (k

frequency pulling) due to your board and aa package parasitic React – Smaller CLOAD provides: • Lower power dissipation inside crystal • Better ability to tweak frequency with cap. • More tuning range with a tuning varactorvaractor..

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Reactance Plot with C LOAD Crystal Equations

⎡ C1 ⎤ FL = FS ⎢ + 1⎥ 2(C0 + CLOAD)

) ⎣ ⎦ Ω FL = Parallel Load Resonant Frequency (MHz) nce (k aa FS = Series Resonant Frequency (MHz)

React C1 = Motional Capacitance (pF) C0 = Shun t Capac itance (p F) (i.e. cshthunt)

CLOAD = Load Capacitance (pF)

30-Nov-2009 DHN Integrated Circuit Design 27 30-Nov-2009 DHN Integrated Circuit Design 28 CLOAD in Oscillator Circuit Crystal ESR C C LOAD1 LOAD2 • ESR = Effective Series Resistance CLOAD = CPAR + CLOAD1 + CLOAD2 – Can be different at different “Drive Levels” – Can change if crystal is over driven CPAR is the effective capacitance due to your – Often 1/5th the Max. specified PWB and IC package. You can also – For very low drive levels, the ESR can be separate your parasitic capacitance into much higher Æ Start up margin required between the two paths and from each path • Crystal RLC Model is a MODEL, to ground. – there are no such components hidden inside For CLOAD1 =C= CLOAD2, CLOAD2 ≈ 22C CLOAD the package.

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GM Cell Oscillator (()Ideal) ADE Window for GM Cell Oscillator

30-Nov-2009 DHN Integrated Circuit Design 31 30-Nov-2009 DHN Integrated Circuit Design 32 GM Cell Oscillator (Ideal) Setting up stability analysis Select Desired Narrow Range iprobe

Lots of Points

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GM Cell loopGain Output Set Up Using Calculator set up dB and phase of loopGain

30-Nov-2009 DHN Integrated Circuit Design 35 30-Nov-2009 DHN Integrated Circuit Design 36 GM Cell LoopGain Plot Getting dB and phase of loopGain

GainMargin

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Getting dB and phase of loopGain (In ADE Win dow: TlToolsÆRlResults B)Browser)

30-Nov-2009 DHN Integrated Circuit Design 39 30-Nov-2009 DHN Integrated Circuit Design 40 Test Bench Right C1 C2 Half Left v1 v2 Half Plane -gm Plane

it i s C1 v + i =0 Æ v = - t 1 t 1 sCs C1 -gm v + i – s C2 v = 0 1 t 2 gm ( 1 + ) gm s C1 ( + 1) it = s C2 v2 Æ v2 = it s C1 s C2

v –v s (C1 + C2) + gm gm + j ω (C1 + C2) Zin == 2 1 = ─ s2 C1 C2 ω2 C1 C2 Only +j region shown, -j region is reflection about real axis at j0 it

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Negative Resistance Test Bench GM Cell Negative Resistance with feedback added

C1 C2 v1 v2 -gm

Rf

it

v2 – v1 s (C1 + C2) + gm Zin = = 2 it s C1 C2 + s (C1 + C2)/(C2 Rf) + gm/Rf

30-Nov-2009 DHN Integrated Circuit Design 30-Nov-2009 DHN Integrated Circuit Design 44 GM Cell Negative Resistance Gate Oscillator Negative Resistance

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Gate Oscillator Negative Resistance Gate Oscillator Negative Resistanc e ) Ω ) Ω (k ms (k ss Kilooh iloohm KK

30-Nov-2009 DHN Integrated Circuit Design 47 30-Nov-2009 DHN Integrated Circuit Design 48 Gate Oscillator Negative Gate Oscillator Negative Resistance Resistance Rules of Thumb: Why???? • Desirable: The absolute value of the • Potential for low amplitude negative resistance should be 10X the – No “dig ita l” ou tpu t from ce ll maximum ESR. – An “inverter” will always be near max. current • EtilThbltlfthEssential: The absolute value of the – Insufficient drive level negative resistance must be 5X the – Poor duty cycle if there is a “digital” output maximum ESR. • Potential for not oscillating at all – Applies to your worst PVT corner

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Negative Resistance versus Transient Simulations needed for Stability Analysis

Negative Resistance Stability Analysis • Determining or verifying your output duty cycle • Covers a broad range of • Gives margin for specific to core specification crystal models • Averaggppe Power draw from the supplies • Can infer start • Must run all PVT for each • Signal Amplitude at terminals up/oscillation from crystal model • Crystal Drive level – MMCax. CLOAD – LtLots more si mu ltilations – Max. ESR I usually use a reduced Q (400 to 1000) to lessen simulation time required. The lowered Q Strategy: Do a significant amount of your design work provides accurate information for the above using Negative Resistance first, run Stability and Transient simulations after your design is stable. parameters.

30-Nov-2009 DHN Integrated Circuit Design 51 30-Nov-2009 DHN Integrated Circuit Design 52 Crystal Oscillator Cell General Gate Oscillator Internals Requirements 1) Basic CMOS Inverter Although the primary function is to provide a digital output signal based on a crystal based oscillator, two other functions are highly desirable: • Power Down to a near zero power drain condition • The a bility t o d ri ve a si gnal in to the IC core using an ATE source instead of a crystal Advantage: Transconductance is sum of P1 and N1 Drawback: Transconductance and Power varyyy widely over PVT

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Gate Oscillator Internals Many Other Options 2) NMOS Inverter • In pp,ublished literature, GM cell based approaches have been used. • Amppglitude limiting or a form of AGC can be added to control amplitude of oscillation and drive level – AGC dynamics are tricky due to high Q of crystal • Getting a low power design requires a more effecti ve way t o get l arge tdttransconductance than Advantage: Transconductance and Power more controlled over PVT the two circuits shown in the previous slides. Drawback: Must design low power Bias Generator that reduces PVT sensitivity.

30-Nov-2009 DHN Integrated Circuit Design 55 30-Nov-2009 DHN Integrated Circuit Design 56 Special Situations Overtone Oscillator Overtone Oscillators • Require a “trap” to prevent oscillating at the fundamental. – An extra inductor is needed outside IC – Helps by improving negative resistance at the higher frequency

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Overtone Oscillator Negative Resistance Overtone Oscillator ) Ω nce (k aa Resist

30-Nov-2009 DHN Integrated Circuit Design 59 30-Nov-2009 DHN Integrated Circuit Design 60 Special Situations The Oscillator that wouldn ’ ttstop stop “32kHz” O scill ators • Sub 100kHz oscillators • The external crystal and two load – Need a much larger effective feedback are where the high current resistor resonance is. – Perhaps open loop biasing – When the oscillator bias is turned of, XOUT dc – Tend to be much larggpyyer cells physically than drops to VSS level , but the oscillation (ringing) MHz range designs signal goes below VSS • Area is small – NTUB were used for ESD protection • Resistors take the most area – The two NTUB resistors ((output,inputoutput,input)) created • Capacitors the next most. a lateral NPN transistor. • Low PowerÆLow CurrentÆLarge value bias resistors. 30-Nov-2009 DHN Integrated Circuit Design 61 30-Nov-2009 DHN Integrated Circuit Design 62

The Oscillator that wouldn’t stop The Oscillator that wouldn’t stop (continued) (continued)

• Think of the lateral NPN as having its • Using an external resistor RDAMP in the XOUT Emitter at XOUT, its collector at XIN, and path limited the emitter current for the parasitic its base at VSS: lateral NPN transistor. – Now the oscillator stopped as intended. – Pulling the XOUT below ground turns on the – Layout of cell was modified to separate and guard transistor riNTUBitfftdiing NTUB resistors for future designs ithtin that – The pullpull--upup PMOS on XIN is not strong technology. enough to dominate, so XIN voltage is pulled – My preference is to use wide poly resistors instead of to a near normal value, putting the Inverter in NWELL/NTUB resistors if possible for the ESD an active gain situation, sustaining the resistors. oscillation.

30-Nov-2009 DHN Integrated Circuit Design 63 30-Nov-2009 DHN Integrated Circuit Design 64 The Oscillator that ran at The Oscillator that wouldn ’ t start 240MHz • The PWB design was very concerned about • Initially, looking at the crystal signals, appeared skew of his digital bus signals to be just low level noise – Gave those signals top routing priority • Further investigation revealed about a 900MHz – Resulted in crystal being placed about 3” from IC oscillation. • The of the paths created an LC tank • Layyp,out was much better than previous case, but that oscillated instead of the intended crystal vias in the PWB paths to the crystal added oscillation capacitance and inductance – Fixed b y cutti ng path an d br idg ing cut w it h a res istor • A resistor to kill the Q of the parasitic inductance to kill the Q of the unwanted tank solved the problem

Moral: Always provide space for RDAMP on PWB.

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My Post-Post-layoutlayout simulation doesn’t Board Level Methods show any negative resistance • Outppgut buffer had several inverter stages • At one point, there was a minimal cross over of the output of the third inversion stage to the XIN signal as I recall – In this design, the output buffer picked from the XIN to idtlimprove duty cycle – The inverters were scaled exactly as the one for the core oscillator – Caused a Miller multiplication of the capacitance, perhaps a factor ~1000 – Shielded cross over to eliminate

30-Nov-2009 DHN Integrated Circuit Design 67 30-Nov-2009 DHN Integrated Circuit Design 68 Measuring Drive Level Determining Design Margin

Using a small resistor (RMEASURE) ~1Ω or • Increase RMEASURE until the oscillator a current probe in that path measure the won’t start up any more.

ac current (rms))I IM – If the value is >>Max. ESR for your crystals , • The internal current through the ESR you have adequate margin. Cshunt Notes: resitistor sh ou ldbld be (1+ /Cload)l) larger. • Drive Level = ESR (1+Cshunt/ )2 I 2 1. Don’t use a wirewound with lots Cload M of inductance 2. Be sure you don’t add lots of inductance. Cload2 Cload is ~ /2 • Perhap use a surface mount resistor 2X Max . ESR

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Board Level Considerations Conclusion • Designing a robust crystal oscillator requires 1. Always layout your PWB to make provision for care and attention to details. RdampRdamp.. • Board Level components and layout are critical 2. The two cappgacitors to ground and the cr ystal tfldito successful design are the primary resonant circuit – Keep very close together • I write OCEAN scripts to: – Keep ground contact for capacitors together if – RthhthNtiRitRun through the Negative Resistance Curves an d possible extract tables for Data Sheets 3. KththfKeep the paths from pack ktage to cryst tlhtal short – Run stability analysis over corners and crystal models (<1’’ if possible with minimum of viasvias.. – Run transient simulations as batch jobs • SubSub--divideddivided by process corner to get parallel effort

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