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Understanding the Basics of the Pierce Oscillator the Designer’S Challenge Is to Optimize Performance with the Quartz Crystal

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Understanding the Basics of the Pierce Oscillator the Designer’S Challenge Is to Optimize Performance with the Quartz Crystal PRODUCT Crystals & Oscillators UPDATE Understanding the basics of the Pierce oscillator The designer’s challenge is to optimize performance with the quartz crystal BY SYED RAZA oday, the majority of elec- the design. This boundary condition, commonly referred to Director of Engineering tronic circuits (including as the safety factor (SF), is an important parameter to ensure Abracon microprocessors, micro- that the product design has sufficient margin to accommo- www.abracon.com T controllers, FPGAs, and CPLDs) date part-to-part and lot-to-lot variations; as well as, eliminat- are based on clocked logic, requiring a timing source. De- ing product performance uncertainty in production volume. pending on the frequency accuracy requirements, some Historically, design engineers have optimized their cir- employ oscillators while others use off-the-shelf quartz cuit performance via trial and error, at the expense of sig- crystals in conjunction with the built- in oscillator circuit embedded in most microcontrollers and microprocessors. Fig. 1: The oscillator block and the key components that Most if not all embedded solutions influence the overall performance of the timing loop. use the Pierce oscillator configuration, integrated as part of the SoC (system- on-chip). The obvious advantages in- clude cost, size, and power compared to a standalone oscillator. The key lim- itation is the proper matching of the quartz crystal with the on-board Pierce nificant investment in time. Further, to prop- oscillator. erly determine the oscillator loop dynamics, Figure 1 outlines the oscillator block the most accurate determination is made by and the key components that influence breaking the oscillator loop and conducting the overall performance of the timing loop. Let the effective key measurements using specialized equipment such as a load capacitance, as seen by the crystal, be CL. Then current probe. Lastly, these measurements become increasingly sensi- tive if the timing loop is driven by a tuning-fork (32.768- kHz) crystal. These crystals are extremely sensitive to load- For example, let C1 = C2 = 27 pF; CIN = 5.0 pF and COUT ing effects and to accurately determine the in-circuit = 10.0 pF and Board Strays = 0.50 pF. Then behavior of these components, extreme care and accuracy is essential. For instance, Automotive, medical and con- sumer electronics solutions typically use tuning fork crys- tals for their real-time-clocking (RTC) needs. If the select- Therefore specifying a crystal with 18.0 pF plating load ed SOP has limited gain margin, there is a high capacitance would be the closest match for frequency ac- probability that some percentage of these crystals will not curacy. The selected capacitors primarily influence the properly start under adverse conditions, such as cold op- overall oscillator loop capacitance, as seen by the crystal. erating temperature (–40°C). This effective loop capacitance (CL from Eq. 1) determines Another example would be a product designed to ad- how far the oscillator loop is resonating, relative to the dress the ZigBee related solutions, which typically has a desired resonant frequency. However, the overall long- hard boundary condition of ±40 ppm relative to the car- term performance of the oscillator loop is influenced by rier, for proper operation. This ±40-ppm operational win- the following factors: dow actually needs to account for • The reactive impedance (Xc) of these loop capacitors. • Quartz crystal set tolerance. • The inverter amplifier’s transconductance (gm). • Shift through reflow. • The presence or absence of the current limiting resistor • Stability over temperature. (Rs). • Aging during product-life-cycle (such as 5 years). • The presence or absence of the automatic gain control • Frequency pushing and pulling. (AGC) or automatic level control (ALC); with-in the If the oscillator loop is not optimized, most of the ±40 integrated oscillator circuit. ppm can be potentially consumed by the set tolerance of the These factors collectively set the boundary condition of quartz crystal alone, thereby causing potential field failures. ELECTRONIC PRODUCTS http://electronicproducts.com JULY 2011 1 PRODUCT Understanding the basics of the Pierce oscillator UPDATE These frequency do- The Pierce Analyzer main failures could be System primarily attributed to To overcome these challenges the oscillator frequency and provide an accurate assess- drifting over tempera- ment of the oscillator loop dy- ture or long-term aging, namics, Abracon’s Advanced En- to the point that the os- gineering Team has developed a cillator loop is no longer Fig. 2: Advanced Pierce proprietary Pierce Analyzer Sys- within the allocated ±40-ppm Analyzer System. tem (PAS), designed to analyze operational window. both the standalone crystal, as Besides the issues related to well as the performance of that particular crystal in the oscillator-loop accuracy in the final circuit. frequency domain, the oscil- Key PAS features lator-loop drive level must also • Circuit characterization; provides best possible match be properly quantified to ensure acceptable product perfor- between Quartz Crystal, oscillator loop and associated mance over temperature and time. For instance, a typical components. 24-MHz SMT quartz crystal has a drive level specification of • Eliminates probability of oscillator startup issues relat- 100 µW max. If the quartz crystal is consistently being driv- ed to inadequate design or marginal component per- en at some multiple of this limit, such as 200 µW; it is pos- formance. sible that, over temperature or time, the oscillator circuit • Eliminates production launch issues related to crystal might start to resonate permanently or intermittently — at oscillator based timing circuit. a spurious or overtone mode of the quartz crystal. • Solves for design margin uncertainty. Although relatively low on the checklist of design engi- • Provides customer’s oscillator circuit overview in the neers, the Pierce oscillator driven by an external resonator form of a detailed report, which could be an ideal 3rd — such as a quartz crystal — can present a significant chal- party assessment for the design history file or PPAP lenge during a typical product launch. Characterizing the documentation. This report encompasses both the oscillator loop during the design phase should be a priority stand-alone crystal performance, as well as in-circuit to mitigate the risk during product launch as well as field behavior outlining safety factor as a function of crys- returns down the road. tal’s ESR, etc. ■ 2 ELECTRONIC PRODUCTS http://electronicproducts.com JULY 2011.
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