MOSFET ZTC Condition Analysis for a Self-Biased Current Reference Design

POLITECNICO DI TORINO Repository ISTITUZIONALE MOSFET ZTC condition analysis for a self-biased current reference design Original MOSFET ZTC condition analysis for a self-biased current reference design / Toledo, P.; Klimach, H.; Cordova, D.; Bampi, S.; Fabris, E.. - In: JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 1807-1953. - 10:2(2015), pp. 103-112. Availability: This version is available at: 11583/2743197 since: 2019-07-23T11:38:05Z Publisher: Brazilian Microelectronics Society Published DOI: Terms of use: openAccess This article is made available under terms and conditions as specified in the corresponding bibliographic description in the repository Publisher copyright (Article begins on next page) 16 August 2019 MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design Pedro Toledo1,2, Hamilton Klimach2, David Cordova1,2, Sergio Bampi2 and Eric Fabris1,2 1NSCAD Microeletrônica, UFRGS, Porto Alegre, RS, Brazil 2PGMicro, UFRGS, Porto Alegre, RS, Brazil e-mail: [email protected], [email protected], [email protected], [email protected], [email protected] ABSTRACT In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple- mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro- vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show- ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V. Index Terms: MOSFET ZTC Condition, Current Reference Source and Low Temperature Coefficient. I. INTRODUCTION temperature and process variations. This condition defines a biasing point where the drain current pres- Current references are essential building blocks ents small temperature sensitivity, as can be seen in for analog, mixed-signal and RF designs, often be- Fig. 1. The ZTC current condition occurs for every ing used for biasing of analog subsystems inside the MOSFET in any technology, for N-Channel Metal- chip. The usual way to generate a current reference Oxide-Semiconductor (NMOS) and P-Channel Metal- is through the implementation of a voltage reference Oxide-Semiconductor (PMOS) transistors, and it is [1], [7], [10], [16] and applying this voltage over a the effect of mutual cancellation of the channel carrier resistive device [2]. Another approach is using a de- mobility and the threshold voltage dependencies on vice where a physical property or condition naturally temperature [4]. Remembering that the drain current establishes an operating current, which can be used as increases when mobility increases and when threshold a reference [3]– [6], [8], [9], [14], [18]. voltage decreases, and that mobility and threshold volt- Any kind of Direct Current (DC) reference, ei- age both decrease when temperature increases, it can ther a voltage or a current one, must offer apprecia- ble thermal stability and power supply rejection, as its main characteristics. In addition, adequate fabrication repeatability ensures that the biasing operation point of the analog blocks is almost the same in every fabricated chip, and reveals how sensitive the current generator is with respect to fabrication process variations [19]. The main idea of this paper is to use the physical condition of MOSFETs called “zero temperature coefficient” (ZTC) to implement a circuit topology Figure 1. NMOS ZTC point for (a) 180 and (b) 350nm bulk-CMOS where the resulting current offers low sensitivity to processes. Journal of Integrated Circuits and Systems 2015; v.10 / n.2:103-112 103 MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design Toledo, Klimach, Cordova, Bampi & Fabris be proved that both effects can cancel each other at a tures ranging from -45 to +85oC, for a 180 nm pro- certain bias point. Fig. 1 presents the drain current vs cess. ZTC operation point can be seen around VGB ≈ gate-source voltage of NMOS transistors under three 760mV for a transistor with VT0 = 430mV, resulting temperatures for two different fabrication process, and that ZTC point occurs for an overdrive voltage around in both figures a convergence point can be seen for the 330mV, meaning the transistor operates in strong in- three I-V curves drawn. version. Fig. 1 (b) shows the same for an NMOS tran- The traditional analysis of this effect presented sistor in a 350 nm CMOS process. in literature is based on the strong inversion quadratic In a more general analysis, we can suppose that MOSFET model [4]. In this work we use a different the ZTC condition can also happen in moderate inver- analytical approach, based on a continuous MOSFET sion and a more complete MOSFET model must be model that can predict its behavior from weak to strong used, such as one presented in [11], which describes inversion [11][21]. Based on this analysis, we verify continuously transistor behavior at any inversion level. that the ZTC point occurs from moderate to strong The well-known Advanced Compact Model (ACM) inversion for any CMOS process. is a design-oriented MOSFET model suitable for an- This paper is organized as follows. In Section II, alog integrated-circuit design. From this model, Eqs an analytical formulation and the discussion about the (3) and (4) give the drain current of a long channel ZTC operating point using an all-region CMOS com- NMOSFET. pact model are presented. In Section III, simulation results from three fabrication processes are presented, (3) regarding the ZTC operating point. After selecting a fabrication process for our design, in Section IV a (4) self-biased CMOS current reference topology is proposed and described. The simulation results are presented in section V, followed by comparisons to other where IF(R) is the forward (reverse) current, if(r) references proposed in literature. Finally, in section VI, is the forward (reverse) inversion coefficient, IS is the the concluding remarks are drawn. normalization current, and ϕt is the thermal voltage. Also from this model, Eqs. (5), (6) and (7) re- late source and drain inversion coefficients (forward II. MOSFET ZTC CONDITION and reverse), if and ir, with the three external voltages applied to transistor terminals, VGB, VSB and VDB, us- MOSFET ZTC condition derives from mutual ing bulk terminal as reference. cancellation of mobility and threshold voltage dependencies on temperature [4]-[5], at a particular gate- to-bulk voltage bias. The drain current ZTC operating (5) bias point was firstly defined in [4] and after in other correlated publications, always based on strong inversion quadratic MOSFET model. From [4], ZTC operating point is given by Eqs. (1) and (2). (6) (1) (7) (2) where VP is called the pinch-off voltage, ϒ is the body effect coefficient, VFB is the flat band voltage and ϕF is the Fermi potential at the bulk of semiconductor where T0 is the room temperature, VT0(T0) is the threshold voltage at room temperature, n is the under transistor channel. First order temperature dependence of VT0 can slope factor, VSB is the source-bulk voltage, αVT0 is the thermal coefficient of the threshold voltage (a nega- be given by Eqs. (8) and (9) [11]. tive parameter, since VT0 decreases with temperature), (8) μ(T0) is the low field mobility at room temperature, C’ox is the oxide capacitance per unit of area and (W/L) is the transistor aspect ratio. and are defined as gate- (9) bulk and drain current ZTC bias point, respectively. Fig. 1 (a) shows the drain current (in a log scale) V ) as a function of gate-bulk voltage ( GB of a saturated where q is the electron charge and EG is the sil- long-channel NMOSFET, simulated under tempera- icon band-gap energy. Fig. 2 presents expected values 104 Journal of Integrated Circuits and Systems 2015; v.10 / n.2:103-112 MOSFET ZTC Condition Analysis for a Self-biased Current Reference Design Toledo, Klimach, Cordova, Bampi & Fabris (13) Assuming that and putting (8) in (13) (14) Noting that the second term of the right branch Figure 2. α vs N for different t [13]. VT0 A ox of the Eq. (14) is equal to for αVT0 for wide ranges of doping concentration (NA) and oxide thickness (t ) [13]. The target-technologies ox (15) for this study are below 350 nm, which corresponds to o αVT0 values between -3.5 and -0.5 mV/ C [13], that is the range used in the following analysis. In addition, Eq. (10) gives the thermal mobility dependence [13]. And putting Eq. (15) in (14), (10) (16) where αμ is the temperature dependence power for mobility model. Since the carriers in inversion layer of transistors undergo several scattering mechanisms, αμ is negative, and its value depends on prevalent scat- Isolating the term from Eq. (16), we get tering mechanisms (such as Coulombic, phonon, or interface scatterings - all of them interfering on carrier transport). Related to electron mobility and under room temperature this parameter varies in a range (17) from -1.5 for high doping concentrations to – 2.4 for light doping concentrations [13]. If one derives the drain current expression for The derivative of normalization current regard- temperature in saturation region (i << i ), the con- r f ing the absolute temperature can be found from Eq.

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