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System-On-Chip Design and Test with Embedded Debug Capabilities

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System-On-Chip Design and Test with Embedded Debug Capabilities University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2006 System-on-Chip Design and Test with Embedded Debug Capabilities Tushti Marwah University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Marwah, Tushti, "System-on-Chip Design and Test with Embedded Debug Capabilities. " Master's Thesis, University of Tennessee, 2006. https://trace.tennessee.edu/utk_gradthes/1734 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Tushti Marwah entitled "System-on-Chip Design and Test with Embedded Debug Capabilities." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the requirements for the degree of Master of Science, with a major in Electrical Engineering. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Syed Islam, Mohammed Ferdjallah Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Tushti Marwah entitled “System-on- Chip Design and Test with Embedded Debug Capabilities.” I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the requirement for the degree of Master of Science, with a major in Electrical Engineering. __Donald W. Bouldin______ Major Professor We have read this thesis and recommend its acceptance: Syed Islam Mohammed Ferdjallah Accepted for the Council: _____Anne Mayhew__________ Vice Chancellor and Dean of Graduate Studies (Original signatures are on file with official student records.) System-on-Chip Design and Test with Embedded Debug Capabilities A Thesis Presented for the Master of Science Degree The University of Tennessee, Knoxville Tushti Marwah August 2006 Acknowledgement First of all, I would like to thank my thesis advisor, Dr. Don Bouldin for his guidance, advice and support throughout my research. It was he who suggested me to pursue my research on the concept of using reconfigurable logic for debugging an SoC and I have greatly enjoyed my work. He was a constant source of encouragement for me throughout my research. I am also very grateful to Dr.Syed K.Islam and Dr.M. Ferdjallah for serving on my thesis committee. I would like to thank Wei Jiang, for his teamwork in this project and instrumentation of the LEON design with the pre-silicon tools that gave me a platform to start from. I would also like to thank DAFCA Inc., where I interned from June 2005-August 2005 for providing me with the pre and post-silicon tools and teaching me their usage. I am thankful to Paul Bradley, Rich Lundblad, Tat Ng and Daniel Hoggar at DAFCA for guiding me during the timing analysis and layout generation of the design. Last but not the least I would like to thank my parents, Dr. Narinder Singh and Mrs. Kamla Marwah and my brother Joban for their unrelenting support and encouragement throughout my education. ii Abstract In this project, I started with a System-on-Chip platform with embedded test structures. The baseline platform consisted of a Leon2 CPU, AMBA on-chip bus, and an Advanced Encryption Standard decryption module. The basic objective of this thesis was to use the embedded reconfigurable logic blocks for post-silicon debug and verification. The System-on-Chip platform was designed at the register transistor level and implemented in a 180-nm IBM process. Test logic instrumentation was done with DAFCA (Design Automation for Flexible Chip Architecture) Inc. pre-silicon tools. The design was then synthesized using the Synopsys Design Compiler and placed and routed using Cadence SOC Encounter. Total transistor count is about 3 million, including 1400K transistors for the debug module serving as on chip logic analyzer. Core size of the design is about 4.8mm x 4.8mm and the system is working at 151MHz. Design verification was done with Cadence NCSim. The controllability and observability of internal signals of the design is greatly increased with the help of pre-silicon tools which helps locate bugs and later fix them with the help of post-silicon tools. This helps prevent re-spins on several occasions thus saving millions of dollars. Post-silicon tools have been used to program assertions and triggers and inject numerous personalities into the reconfigurable fabric which has greatly increased the versatility of the circuit. iii Table of Contents Chapter 1 Overview ............................................................................................ 1 1.1 System-on-Chip (SoC).............................................................................. 1 1.2 Design Testing and Verification .............................................................. 1 1.3 Motivation .................................................................................................. 2 1.4 Thesis Goals.............................................................................................. 3 1.5 Thesis Outline ........................................................................................... 3 Chapter 2 Background ....................................................................................... 4 2.1 Challenges in System-on-Chip Design ................................................... 4 2.2 Types of Testing and their Problems ...................................................... 4 2.3 The DAFCA Solution................................................................................. 5 2.4 Debug Methods Supported by DAFCA.................................................... 6 Chapter 3 Volunteer SoC ................................................................................... 9 3.1 Overview .................................................................................................... 9 3.2 LEON CPU ................................................................................................. 9 3.3 AMBA Buses ........................................................................................... 11 3.4 AES Module ............................................................................................. 13 3.5 Artisan RAM ............................................................................................ 13 Chapter 4 Volunteer SoC Debug using DAFCA Tools................................... 16 4.1 Introduction to the DAFCA Tools .......................................................... 16 4.2 Pre - silicon Tools ................................................................................... 16 4.3 Instrumentation of the Volunteer SoC Using Pre-Silicon Tools ......... 19 4.4 Post-Silicon Tools................................................................................... 20 4.4.1 Personality Editor............................................................................. 22 Chapter 5 Implementation................................................................................ 27 5.1 Customizing the LEON2 Processor....................................................... 27 5.1.1 Configuration.................................................................................... 27 5.1.2 Artisan RAM...................................................................................... 28 5.2 The Integrated SoC ................................................................................. 29 5.3 Insertion of rMatrix to the Design.......................................................... 30 5.4 Synthesis................................................................................................. 31 5.5 Physical Place and Route....................................................................... 32 iv 5.5.1 Floorplanning, Powerplanning and Placement.............................. 32 5.5.2 Clock Tree Synthesis ....................................................................... 34 5.5.3 Routing.............................................................................................. 35 5.6 Simulation Result.................................................................................... 35 5.7 Sending the Design to MOSIS................................................................ 37 Chapter 6 Testing with Post-Silicon tools...................................................... 45 6.1 Tests Performed...................................................................................... 45 6.2 Discussion............................................................................................... 55 6.2.1 Area Comparison.............................................................................. 55 6.2.2 Timing Overhead .............................................................................. 55 6.2.3 General Discussion.......................................................................... 55 Chapter 7 Future Work and Conclusion ......................................................... 57 7.1 Future Work............................................................................................
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