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ARM Processor Architecture Embedded Systems with ARM Cortext-M Updated: Monday, February 5, 2018 a Little About ARM – the Company

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Chapters 1 and 3 ARM Processor Architecture Embedded Systems with ARM Cortext-M Updated: Monday, February 5, 2018 A Little about ARM – The company • Originally Acorn RISC Machine (ARM) • Later Advanced RISC Machine • Then it became ARM Ltd owned by ARM Holdings (parent company) • In 2016 SoftBank bought ARM for $31 billion • ARM: • Develops the architecture and licenses it to other companies • Other companies design their own products that implement one of those architectures— including systems- on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. • It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products. • ARM Processors • RISC based processors • In 2010 alone, 6.1 billion ARM-based processor, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers • over 100 billion ARM processors produced as of 2017 • The most widely used instruction set architecture in terms of quantity produced https://en.wikipedia.org/wiki/ARM_architecture M R https://en.wikipedia.org/wiki/ARM_architecture ARM Family and Architecture CPU ARM FAMILY TREE CORTEX- CORTEX- CORTEX- ARM Cortex Processors • ARM Cortex-A family: • Applications processors • Support OS and high- performance applications • Such as Smartphones, Smart TV • ARM Cortex-R family: • Real-time processors with high performance and high reliability • Support real-time processing and mission-critical control • ARM Cortex-M family: • Microcontroller • Cost-sensitive, support SoC 6 CORTEX- • Cortex-M is a great trade-off between performance, cost, efficiency; used for IoT, various applications. • Has on-chip peripherals • Core is licensed by ARM Harvard Architecture CORTEX-M: CORE + Peripherals • Core • Peripherals • Memory • ADC • FLASH: Non-Volatile / Instruction memory • LCD Controller SRAM/DRAM: Volatile / data memory • SPI • Processor • I2C • ALU • Processor Control Unit (CPU) • Etc. • Registers • Special Purpose Registers • General Purpose Registers • Buses • Data Bus • Instruction Bus • Bus bridge to connect diff. buses • Advanced High-performance Bus (AHB) • Advanced Peripheral Bus (APB) • GPIO Core Architecture Von-Neumann Harvard Instructions and data are stored in Data and instructions are stored into the same memory. separate memories. • Simple and inexpensive • Faster • Access to data or instruction, one at a time • More energy efficient • Different bus sizes 9 Core Architecture Von-Neumann Harvard Instructions and data are stored in Data and instructions are stored into the same memory. separate memories. 10 ARM Simplified Block Diagram System on Chip (SoC) http://www.microdigitaled.com/ARM/ASM_ARM/PowerPoints/ARM_ASM_ppts.htm ARM Cortex-M4 Organization (STM32L4) LCD SPI2 Harvard Based TIM2 SPI3 TIM3 I2C1/SMBUS SW/JTAG Architecture TIM4 I2C2/SMBUS TIM6 I2C3/SMBUS TIM7 USB 2.0 FS bxCAN Cortex-M4 Processor Core Instructions Flash USART2 USART3 SWPMI1 t Memory i Instruction Bus r ) LPTIM1 l r USART4 n e n P e o U l e d r ) y o l S g USART5 LPTIM2 l Data t r c i o h t o u a a D o Memory n x c r f ( i c c SRAM OpAmp b n t LPUART1 r r o e t e m ` t u e ) e a o n c Protection e e r C t D i t a t t D t a o U i C F n a r M f I I s n M Advanced High- p L n Unit (MPU) r C Interrupts o n D & V n o o e s t I A U i s ( o t N t performance Bus e e i u p s ( l t e n c APB1 c l I B U e u p c Advanced u a r (AHB) i Data Bus g c AHB to APB Bridge 1 P r t r r u B l t n o r F e T i Peripheral Bus t r u s H t s S P n n A AHB to APB Bridge 2 M I I (APB) n I ABP2 System Bus GPIO Port A GPIO Port B EXTI GPIO Port C SPI1 Direction Memory GPIO Port D WKUP SAI1 Access (DMA) GPIO Port E TIM1/PWM SAI2 Controllers GPIO Port F TIM8/PWM DFSDM GPIO Port G TIM15 COMP1 GPIO Port H TIM16 COMP2 TIM17 Firewall General USART1 Note that the Kit we are using System-on-a-chip Purpose IO Has an STM32F401 12 Memory Data Address 8 bits 32 bits • Memory is arranged as a series of “locations” 0xFFFFFFFF • Each location has a unique “address” • Each location holds a byte (byte-addressable) • e.g. the memory location at address 0x080001B0 contains the byte value 0x70, i.e., 112 • The number of locations in memory is limited • e.g. 4 GB of RAM 70 0x080001B0 • 1 Gigabyte (GB) = 230 bytes BC 0x080001AF • 232 locations è 4,294,967,296 locations! 18 0x080001AE 01 0x080001AD • Values stored at each location can represent A0 0x080001AC either program data or program instructions • e.g. the value 0x70 might be the code used to tell the processor to add two values together 0x00000000 13 Memory Memory Mapping • Answer the following questions: • What is the size of the EEPROM? • What is the size of the Flash? • Which Memory portion is non-volatile? • What does SRAM generally used for in an ARM core processor? • Where is 0x743 address? • Where is 0x1000AB address? 16 Processor Registers 13 for general purpose ARM Register and ALU 3 for specific purpose Processor Registers } 32 bits Fastest way to read and write } Registers are within the processor chip R0 } A register stores 32-bit value R1 } Cortex M (STM32L) has R2 } R0-R12: 13 general-purpose registers Low R3 } Registers R4 R13: Stack pointer (Shadow of MSP or PSP) R5 } R14: Link register (LR) General R6 Purpose } R15: Program counter (PC) Register R7 } Special registers (xPSR, BASEPRI, PRIMASK, etc.)- R8 more later R9 32 bits High Registers R10 R11 xPSR R12 BASEPRI Special R13 (SP) R13 (MSP) R13 (PSP) PRIMASK Purpose Register R14 (LR) FAULTMASK R15 (PC) CONTROL 16 Program Execution • Program Counter (PC) is a register that holds the memory address of the next instruction to be fetched from the memory. Memory Content àNext Instruction Memory Address 4770 0x080001B4 2000 0x080001B2 188B 0x080001B0 PC 2201 0x080001AE 2100 0x080001AC PC = 0x080001B0 Instruction = 188B or 2000188B or 8B180020 17 Three-state pipeline: Fetch, Decode, Execution • Pipelining allows hardware resources to be fully utilized • One 32-bit instruction or two 16-bit instructions can be fetched. 1. Fetch instruction at PC address 3. Execute 2. Decode the the instruction instruction Pipeline of 32-bit instructions 18 Loading Code and Data into Memory SRAM 19 ARM Register and ALU Machine codes are stored in memory Data Address pc r15 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 r2 r1 r0 0x00000000 Registers CPU Memory 21 Fetch Instruction: pc = 0x08001AC Decode Instruction: 2100 = MOVS r1, #0x00 Data Address pc r15 0x080001AC 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 r2 r1 r0 0x00000000 Registers CPU Memory 22 Execute Instruction: MOVS r1, #0x00 Data Address pc r15 0x080001AC 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 r2 r1 0x00000000 r0 0x00000000 Registers CPU Memory 23 Fetch Next Instruction: pc = pc + 2 Decode & Execute: 2201 = MOVS r2, #0x01 Data Address pc r15 0x080001AE 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 r2 0x00000001 r1 0x00000000 r0 0x00000000 Registers CPU Memory 24 Fetch Next Instruction: pc = pc + 2 Decode & Execute: 188B = ADDS r3, r1, r2 Data Address pc r15 0x080001B0 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 0x00000001 r2 0x00000001 r1 0x00000000 r0 0x00000000 Registers CPU Memory 25 Fetch Next Instruction: pc = pc + 2 Decode & Execute: 2000 = MOVS r0, #0x00 Data Address pc r15 0x080001B2 0xFFFFFFFF r14 lr r13 sp r12 r11 r10 r9 4770 0x080001B4 r8 ALU 2000 0x080001B2 r7 188B 0x080001B0 r6 2201 0x080001AE r5 2100 0x080001AC r4 r3 r2 0x00000001 r1 0x00000000 r0 0x00000000 0x00000000 Registers CPU Memory 26 ARM Applications…. iPhone 5 Teardown The A6 processor is the first Apple System-on-Chip (SoC) to use a custom design, based off the ARMv7 instruction set. http://www.ifixit.com 28 iPhone 6 Teardown The A8 processor is the first 64- bit ARM based SoC. It supports ARM A64, A32, and T32 instruction set. http://www.ifixit.com 29 iPhone 7 Teardown A10 processor: • 64-bit system on chip (SoC) • ARMv8-A core 30 Apple Watch • Apple S1 Processor • 32-bit ARMv7-A compatible • # of Cores: 1 • CMOS Technology: 28 nm • L1 cache 32 KB data • L2 cache 256 KB • GPU PowerVR SGX543 31 Kindle HD Fire Texas Instruments OMAP 4460 dual- core processor http://www.ifixit.com 32 Fitbit Flex Teardown STMicroelectronics 32L151C6 Ultra Low Power ARM Cortex M3 Microcontroller Nordic Semiconductor nRF8001 Bluetooth Low Energy Connectivity IC 33 www.ifixit.com Samsung Galaxy Gear • STMicroelectronics STM32F401B ARM- Cortex M4 MCU with 128KB Flash source: ifixit.com 34 Pebble Smartwatch source: ifixit.com • STMicroelectronics STM32F205RE ARM Cortex-M3 MCU, with a maximum speed of 120 MHz 35 Oculus VR • Facebook’s $2 Billion Acquisition Of Oculus in 2014 source: ifixit.com • ST Microelectronics STM32F072VB ARM Cortex-M0 32-bit RISC Core Microcontroller 36 HTC Vive STMicroelectronics 32F072R8 ARM Cortex-M0 Microcontroller source: ifixit.com 37 Nest Learning Thermostat source: ifixit.com • ST Microelectronics STM32L151VB ultra-low-power 32 MHz ARM Cortex-M3 MCU 38 Samsung Gear Fit Fitness Tracker source: ifixit.com • STMicroelectronics STM32F439ZI 180 MHz, 32 bit ARM Cortex-M4 CPU 39 A Little About STM32 • STM32 is a family of 32-bit microcontroller integrated circuits by STMicroelectronics • The STM32 chips are grouped into related series that are based around the same 32-bit ARM processor core, such as the Cortex-M7F, Cortex-M4F, Cortex-M3, Cortex-M0+, or Cortex-M0.
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