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System-On-Chip Design with Virtual Components

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System-On-Chip Design with Virtual Components past designs can a huge chip be com- pleted within a reasonable time. This FEATURE solution usually entails reusing designs from previous generations of products ARTICLE and often leverages design work done by other groups in the same company. Various forms of intercompany cross licensing and technology sharing Thomas Anderson can provide access to design technol- ogy that may be reused in new ways. Many large companies have estab- lished central organizations to pro- mote design reuse and sharing, and to System-on-Chip Design look for external IP sources. One challenge faced by IP acquisi- tion teams is that many designs aren’t well suited for reuse. Designing with with Virtual Components reuse in mind requires extra time and effort, and often more logic as well— requirements likely to be at odds with the time-to-market goals of a product design team. Therefore, a merchant semiconduc- tor IP industry has arisen to provide designs that were developed specifically for reuse in a wide range of applications. These designs are backed by documen- esign reuse for tation and support similar to that d semiconductor provided by a semiconductor supplier. Here in the Recycling projects has evolved The terms “virtual component” from an interesting con- and “core” commonly denote reusable Age, designing for cept to a requirement. Today’s huge semiconductor IP that is offered for system-on-a-chip (SOC) designs rou- license as a product. The latter term is reuse may sound like tinely require millions of transistors. promoted extensively by the Virtual Silicon geometry continues to shrink Socket Interface (VSI) Alliance, a joint a great idea. But with and ever-larger chips are possible. effort of several hundred companies to But, the enormous capacity potential set standards for VC design, verification, increasing require- of silicon presents several challenges and use. In this article, I describe the for designers. Design methodology and major virtual component (VC) types ments and chip sizes, EDA tools are being severely stressed and discuss their use in SOC designs. by SOC projects at the same time that it’s no easy task. narrowing time-to-market requirements FORMS OF VC demand more rapid and frequent in- VCs are commonly divided into Thomas explains how troduction of new products. three categories—hard, soft, and firm. SOC projects present another A hard VC or hard macro is a design virtual components problem—how to design enough logic that is locked to a particular silicon to fill up these devices. Few compa- technology. Such macros are fully help suppliers get nies have the expertise to design all placed and routed and are available in the intellectual property (IP) needed a fixed size and format. more mileage out of for a true SOC, and few have enough They can be easily dropped into the engineering resources to complete floorplan for a chip in the same target their SOC designs. such a massive project. Even those with technology, because the silicon tech- the required knowledge and plentiful nology is known, and they usually have resources may still be unable to finish predictable timing. However, they a complete chip design in time to can’t easily be mapped to another meet accelerated market demands. silicon vendor (e.g., a second source) The net result: SOC projects require or even to a different technology from design reuse. Only by leveraging off the same vendor. The VC user also 12 Issue 109 August 1999 CIRCUIT CELLAR® www.circuitcellar.com has little or no choice in terms of fea- Figure 1—A soft VC intercon- ture set modification or customization. nect fits between the applica- Application tion logic and the I/O signals. interface Hard macros are most often pro- Standard Implementation instructions Interconnect Application vided by ASIC and FPGA vendors as I/O I/O generally include guidelines for bus VC logic part of their library. Such macros are a connecting the interconnect to SOC natural extension to the basic cell the external chip pins. library used to implement the VC user’s design. Because the silicon vendor sells chips, there’s no incentive to layout-level implementation, although Perhaps the highest leverage is provide a VC in a more portable form some people refer to a VC as firm provided by a VC that implements a that makes it easier for the customer whenever it comes with layout guide- formal or de facto standard. Because to switch to another supplier. lines. The term also refers to a netlist- many types of chips and end products Some IP vendors, especially those level VC that has been mapped by must meet a standard, a VC that supplying microprocessor and DSP synthesis to a target technology but is implements this standard is ideal as a designs, also provide a VC in hard not yet placed and routed. commercial IP product. It’s rare that form. This option shows that the key It is possible, although difficult, to an end user can add enough value elements of processors, especially make customizations to a VC in with an in-house design to offset the data paths for arithmetic computa- netlist form. Synthesis tools can also time savings and standards expertise tion, are often designed at the transis- provide some degree of portability to embodied in a well-designed VC. tor level for maximum performance. new technologies, but the range of The standards provided by VCs range Some processors, as well as many optimizations available when synthe- from formal IEEE, ANSI, and IEC other kinds of VC products, are avail- sizing from the netlist level is more specifications to new technologies. able from IP vendors in soft (or syn- limited than from Verilog or VHDL. Examples include communications thesizable) form. A VC described in protocols like Ethernet and ATM, Verilog RTL or VHDL code gives the VC FUNCTIONS computational functions such as user maximum flexibility. It can be Numerous factors can lead to a MPEG and JPEG, parallel intercon- mapped to virtually any target ASIC decision to license a commercial VC nect standards such as PCI and AGP, or FPGA technology using commer- for inclusion in an SOC design. The and serial interconnects like USB and cial logic synthesis tools. expertise and resources available and IEEE 1394. These examples have wide The user may also be able to con- the time-to-market requirements for applicability to many different types of trol the VC feature set, for example, the end product must be balanced SOC-based products, and the standards by setting variables in the code or by against the expense of the VC license. themselves are well enough defined to running a utility that modifies the Even a company with vast, expert allow implementation as a VC. code under user control. Of course, resources may be able to produce a A VC implementing an interconnect because the user licenses the actual better product faster by leveraging technology probably has the widest Verilog or VHDL source code, it can external IP. range of application. For example, PCI always be modified directly. This is especially true if the VC is used in diverse types of electronic One issue with a synthesizable VC implements a common function be- products. Although it was developed is that the precise timing is not known cause little is gained by designing and as a personal computer peripheral bus, until the VC is mapped to a target optimizing such a function rather PCI has now been adopted for work- technology. Accordingly, soft VC than focusing on product-differentiat- stations, mainframe computers, mili- suppliers must synthesize to a range ing features. For example, the VC may tary applications, and networking/ of representative target libraries and duplicate the function of existing telecommunications systems. USB is ensure that timing is satisfied. stand-alone chips (e.g., a UART or a following a similar expansion of scope The supplier may also have to floppy disk controller) or implement a beyond the PC, as it is used to con- supply guidelines to assist the user in common arithmetic function such as nect peripherals to gaming systems, laying out the chip containing the VC a multiplier. set-top boxes, and PDAs. so that the postroute timing is The widest penetration of all still correct. Such guidelines may may occur with 1394, which is SOC include recommendations for SystemOnChip VC B VC C designed to interconnect both target technology, pin assign- bus computers and diverse consumer Memory Embedded ments for external I/O, floor- controller processor electronics devices. Products PeripheralOnChip planning for key modules, and bus available today with 1394 sup- routing of critical paths. VC A VC D port include video cameras, digi- The definition of a firm VC tal televisions, digital VCRs and varies widely. The term is used professional audio equipment. Figure 2—System-on-chip designs may contain both a system bus most commonly to refer to a soft connect and a peripheral bus connect. Custom I/O blocks that provide Although it is not yet supported VC accompanied by an example functions not commercially available may also be included. in mainstream PC chipsets, www.circuitcellar.com CIRCUIT CELLAR® Issue 109 August 1999 13 such as a fully embedded processor, is also possible for the SOC designer to SOC wired into the chip design like any create custom I/O blocks that connect VC A VC B other module. An interface VC, how- to an OCB to support functions not PCI-to-PCI ever, generally has some I/O signals available from commercial VC sources. bridge External On-chip that need to connect to external chip It would be nice if widely adopted PCI bus PCI bus VC C VC D pins.
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