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A Area VLSI Design (SCL)

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A Area VLSI Design (SCL) A Area VLSI Design (SCL) A1 Sub Area ASIC Design (SCL) A1.1 Design of Instrumentation Amplifier A High-Precision Instrumentation Amplifier with large CMRR is required for the Sensor Signal conditioning applications. Instrumentation amplifier is a versatile device used for amplification of small differential mode signals while rejecting large common mode signal at the same time. In a typical signal conditioning chain, the output of the sensor goes to the instrumentation amplifier. The instrumentation amplifier amplifies the small output signal of the sensor and gives it to the ADC for digitization. Target Specification: • Supply Voltage: 3.3V • Temperature Range: -40 degC to 125 degC • Programmable Gain: 1 to 1000 • Low noise < 0.3µV p-p at 0.1 Hz to 10 Hz • Low non linearity < 20ppm (Gain = 1) • High CMRR (Common Mode Rejection Ratio) > 90dB (Gain=1) • Low offset voltage < 100µV • 3 dB Bandwidth: 1MHz (at Gain = 1) The design of the proposed Instrumentation Amplifier is to be carried out in SCL 180 nm process. A1.2 Design of a Current Feedback Amplifier (CFA) Opamps come in two types: the voltage-feedback amplifier (VFA), for which the input error is a voltage; and the current-feedback amplifier (CFA), for which the input error is a current. The CFA noninverting amplifier is relatively free from a gain-bandwidth trade-off. Additional advantage of CFAs compared to VFAs is the absence of slew-rate limiting. CFA is primarily used where both high speed and low distortion signal processing is required. CFAs are mainly used in broadcast video systems, radar systems , IF and RF stages and other high speed circuits. Although CFAs are harder to design as compared to VFAs but they offer more bandwidth and DC precision. Target Specification: High speed: 1650 MHz (G = +1) Low voltage offset: 0.7 mV Low input bias current: 7µA High O/p drive : 100 mA A1.3 Design of Low Noise Amplifier (LNA) In wireless applications, a low-noise amplifier (LNA) is an active network that increases the amplitude of weak RF signals to allow processing by a receiver. In a receiver chain, the first amplifier after the antenna contributes the most to the system noise figure. Although amplifiers are known to add noise and distortion to the desired signal, RF low-noise amplifiers (RF LNAs) are designed to increase the desired RF signal amplitude without adding distortion or noise. A typical LNA may supply a power gain of 100 (20 dB) while decreasing the signal-to-noise ratio by less than a factor of two i.e. 3dB noise figure. Target Specification: Power Supply = 1.8V Flat gain of 25dB from 1 to 3 GHz Noise figure less then 2dB Input and output return losses less then -15dB A1.4 Design of 12 bit 1 GSPS DAC in SCL’s 180nm Technology Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal. The digital data may be produced from a microprocessor, Application Specific Integrated Circuit (ASIC), or Field Programmable Gate Array (FPGA), but ultimately the data requires the conversion to an analog signal in order to interact with the real world. This DAC should cater test and Measurement, Imaging and high-Precision, high-Speed data acquisition applications with these features in Junction temperature range -40 °C to +125 °C Target Specifications: Resolution 12 bits Speed 1 GSPS FSR Current 2 mA-20 mA SFDR >74 dBFS at 70 Msps DNL < ±0.5LSB INL < ±1LSB Gain DAC Monotonicity Guaranteed Offset Error < ±0.01 % of FSR Gain Error < ±2 % of FSR Output Compliance range -1 to +1 V Offset Error < ±0.01 % of FSR @ Mid Code Power supply 1.8/3.3 V Technology SCL 180 nm A1.5 Design of 14 bit 500 MSPS DAC in SCL’s 180nm Technology Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal. The digital data may be produced from a microprocessor, Application Specific Integrated Circuit (ASIC), or Field Programmable Gate Array (FPGA), but ultimately the data requires the conversion to an analog signal in order to interact with the real world. This DAC should cater test and Measurement, Imaging and high-Precision, high-Speed data acquisition applications with these features in Junction temperature range -40 °C to +125 °C Target Specifications: Resolution 14 bits Speed 500 MSPS FSR Current 2 mA-20 mA SFDR >74 dBFS at 70 Msps DNL < ±0.5LSB INL < ±2LSB Gain Error < ±2 % of FSR Output Compliance range -0.5 to +1 V @ Full Scale Current = 20 mA Offset Error < ±0.01 % of FSR @ Mid Code Power Dissipation < 600 mW Power supply 1.8/3.3 V Technology SCL 180 nm A1.6 Design of 8-Bit 1GSPS Flash ADC The flash analog-to-digital converter (ADC) architecture is the most popular topology for video processing, telecommunications, digital imaging etc. designs because its gives highest speed. This design of ADC should cater imaging as well as communication applications with these features in Junction temperature range -40 °C to +125 °C Target Specifications: SNDR >46 dBFS at 1000 Msps SFDR >60 dBc at 1000 Msps DNL <±0.5LSB INL <±0.5LSB No missing Code Gain Error<±0.5LSB Offset Error<±0.5LSB Output data format in LVDS or CMOS Deliverables: i. Design Details along with all schematics and layout ii. GDSII file of Design iii. Test results and evaluation board A1.7 Design of PLL with VCO A PLL is a circuit that causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized-often called locked-state the phase error between the oscillator's output signal and the reference signal is zero, or remains constant. If a phase error builds up, a control mechanism acts on the oscillator in such a way that the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal. This is why it is referred to as a phase- locked loop. The project requires a square-wave output frequency generator with primary application of PLL as Frequency multiplier by multiplying the frequency of the reference oscillator. Target Specifications: Output clock frequency range 40Mhz to 1800Mhz Mhz Output Jitter (RMS) : 1.2% UI Output Jitter (Total) : 8% UI Supply voltage : 1.8V Multiple output frequency rations : 2,4,8 Inverter output frequencies : YES A1.8 Design of Adjustable high performance Radhard Negative Voltage Regulator This is adjustable high performance Radhard negative voltage regulator. It is specifically intended for space and harsh radiation environments. It should provide exceptional electrical performances, high speed and low dropout voltage. Input supply ranges from - 3 V to - 12 V. It also provide logical control / monitor functions (inhibit, output monitor, short-circuit control) from/to external positive voltage signals, while the entire device adjustable analog functions are biased at negative voltages with respect of ground pin. Target Specifications: • The device should operate in Junction temperature range -40°C to +125°C. • 3 A low dropout voltage • Over temperature and over current protection • Adjustable over current limitation • Load short circuit monitoring • Adjustable output voltage • Inhibit (ON/OFF) TTL-compatible control • Programmable output short-circuit current limitation Deliverables: i. Design Details along with all schematics and layout ii. GDSII file of Design iii. Test results and evaluation board A1.9 Design of Controller area network (CAN) serial communication physical layer The CAN Controller is block providing Controller Area Network (CAN) functionality compliant with the CAN Specification. The CAN Controller features a programmable bit rate to support applications that require a high- speed (up to 1 Mbit/s) or a low-speed CAN interface. Fifteen message buffers, each configurable for transmit or receive, and programmable acceptance filtering provide support for both Full-CAN and Basic-CAN operation. Host-accessible control registers provide CPU control of bit rate, diagnostic functions, enabling/disabling the CAN Controller, CAN pin logic level, CAN bit time partitioning, incoming message filtering, transmit message prioritization, and enabling/disabling interrupts. Status registers provide CAN node, interrupt, and error/diagnostic status. The CAN bus interface consists of serial transmit and receive signals that connect to an external transceiver through chip-level I/O pads. To reduce chip-level pin count, the transmit and receive signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller. Key Features • Programmable bit rate—up to 1 Mbit/sec • Standard or extended frames • 15 message buffers—each configurable for transmit or receive • Remote frame support • Automatic transmission after reception of a Remote Transmission Request (RTR) • Automatic receive after transmission of an RTR • Programmable acceptance filtering • Global mask for message buffers 0–13 • Individual mask for message buffer 14 Programmable transmit priority • Time stamp counter—programmable for automatic reset on transmit/receive • Interrupt capabilities • Interrupts available for message buffer transmit/receive and CAN error conditions • Interrupts can be individually enabled/disabled • Diagnostic functions • Error identification • Loopback (internal or external) • Listen-only mode for initialization Applications • Passenger vehicles, trucks, buses (gasoline vehicles and electric vehicles) • Agricultural equipment • Electronic equipment for aviation and navigation • Industrial automation and mechanical control • Elevators, escalators • Building automation • Medical instruments and equipment • Pedelecs • Model Railways/Railroads A1.10 Design of ultra-low-noise, high-precision voltage reference < 1 ppm/°C Drift with 1.8V VDD in SCL’s 180nm Technology Band gap references are widely used in CMOS integrated circuits such as A/D convertors, DRAMS, flash memory circuits for their high precision and temperature independence.
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