Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

sensors

Article Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

Maria Malits * and Yael Nemirovsky

Department of Electrical Engineering, Technion—Israel Institute of Technology, Haifa 3200003, Israel; [email protected] * Correspondence: [email protected]; Tel.: +972-4-8294683

Received: 6 July 2017; Accepted: 27 July 2017; Published: 29 July 2017

Abstract: This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

Keywords: CMOS–SOI; lateral diodes; temperature sensors; thermal sensors; semiconductor devices

1. Introduction Nanometric partially-depleted CMOS-SOI technology, is now an established technology in a wide range of low-cost, low power and high temperature applications including sensors, high-performance RF, mobile, and mixed-signal chips [1–8]. In spite the enhanced performance of SOI (Silicon on Insulator) devices offered by the buried oxide (BOX) layer, this layer severely impedes heat conduction to the substrate due to the low thermal conductivity of silicon dioxide. Furthermore, the thickness of BOX plays a role in the heat transfer to the substrate since a thinner BOX will allow better cooling of the device from the substrate contact [9]. Therefore, compared to bulk MOS devices, all SOI transistors are more prone to self-heating effects, especially ones with a thick BOX layer. A rise in chip temperature may degrade the chip performance and decrease its reliability [10,11], hence, thermal design is a critical issue. Continuous thermal monitoring is necessary to reduce thermal damage, increase reliability, and optimize performance. In order to implement effective thermal management, multiple temperature sensors should be placed in strategic chip areas. The desired number of sensors, their exact location, and accuracy depend greatly on system-level requirements, IC packaging, and the cooling system. An ideal on-chip temperature sensor should be accurate, compatible with the target process, and have reasonable silicon area so that it can be placed non-invasively across the chip without drastically changing the chip design plan. In addition, the power consumption of the sensor should be very low to reduce the power budget overhead of the thermal monitoring system, and to minimize

Sensors 2017, 17, 1739; doi:10.3390/s17081739 www.mdpi.com/journal/sensors Sensors 2017, 17, 1739 2 of 12 measurement inaccuracies due to self-heating. However, usually there is a distinct tradeoff between the sensor’s accuracy and its area and power consumption, as well as the need for calibration. Calibration requirements significantly affect the cost of the products. Furthermore, a highly accurate sensor consumes more silicon area and power compared to a less accurate one. Hence, it is challenging to generalize the criterions for an optimal temperature sensor, but it is widely known that the design tradeoffs are largely driven by the exact application and system-level considerations. A number of silicon physical properties are temperature dependent, hence there are a number of CMOS-SOI devices that may be used as integrated temperature sensors. In addition, by adding MEMS or NEMS to CMOS-SOI devices, the temperature sensors may be thermally isolated, thus providing thermal sensors and thermal imaging systems. Since CMOS and its derivative CMOS-SOI are the most mature and prevalent microelectronics technologies and the key to a significant cost reduction, uncooled thermal sensors based on standard CMOS or CMOS-SOI technology have been extensively pursued [5–8]. This paper reviews the concepts, advantages and limitations of the leading temperature sensors and thermal sensors fabricated using nanometric CMOS-SOI technology. We compare these sensors in terms of sensitivity, linearity, accuracy, calibration needs, area, and the possibility to measure temperature during the chip operation (on-line) in the temperature range of 300–550 K. In addition, the noise characteristics of the sensors are investigated and compared in order to evaluate their performance as the main component of thermal sensors. This study is performed on standard CMOS-SOI MOSFETs and lateral diodes commercially available today and fabricated using CMOS-SOI 180 nm and 130 nm processes [12,13]. The specific dimensions, determined by W/L, were designed by the authors.

2. Temperature and Thermal Sensors An integrated temperature sensor produces an output current or voltage that is proportional to the local area absolute temperature. These sensors are usually small, accurate, and have a fast response time. Unlike temperature sensors, thermal sensors measure the physical quantities by transducing their signals into thermal quantities ﬁrst and then transducing the thermal quantities into electrical quantities. A thermal sensor operates in three steps:

1. A non-thermal signal is transduced into a heat ﬂow. 2. The heat ﬂow is converted, within the thermal signal domain, into a temperature difference. 3. The temperature difference is transduced into an electric signal with a temperature sensor.

Hence, the basic building block of each thermal sensor is an integrated temperature sensor. There are various ways to realize a temperature sensor using CMOS technology. The vertical forward biased diode which, in practice, is a part of a parasitic PNP transistor, is probably one of the most commonly used sensors in the semiconductor industry to monitor temperature [14,15] (see [14], p. 294). Its advantage over other types of temperature sensors includes its compatibility with IC technology, low manufacturing cost, accuracy, and reasonable sensitivity over a wide temperature range [14–16]. When the diode is forward-biased at a given current and the junction temperature varies, the voltage across the diode shows a linear variation with temperature [16,17]. In [18], a temperature sensor, which consists of three transistors and has quite good linearity for 1.0 and 0.8 µm processes, has been introduced. However, in nanometric technologies and very low-power applications, with 1.8 V or 1 V supply voltage, the sensor’s linearity is degraded. Some research groups have realized temperature sensors using a time-to-digital-converter, or a ring-oscillator, in a 0.35 µm process or below. However, such temperature sensors occupy a large area and consume excessive power at the required sampling rate [19]. In addition, most of these temperature sensors are not compatible with CMOS-SOI technology. Sensors 2017,, 17,, 1739 3 of 1213

The two most commonly used elements for temperature sensing available in CMOS-SOI technologyThe two are: most standard commonly MOSFET used elements transistors for temperature operating sensing at subthreshold available in CMOS-SOI levels and technology lateral are:diodes standard [20–23 MOSFET]. In advanced transistors CMOS operating-SOI technology at subthreshold it is impossible levels and lateral to manufacture diodes [20– 23a ]vertical. In advanced diode CMOS-SOIdue to the thin technology body layer; it is hence, impossible a forward to manufacture-biased diode a vertical is built diodewith a due lateral to the structure thin body based layer; on hence,the device a forward-biased layer, forming diode a source/drain is built with PN a lateral junction structure under the based gate on of the a device MOSFET layer, transistor, forming as a source/drainshown in Figure PN 1a junction. under the gate of a MOSFET transistor, as shown in Figure1a.

(a) (b)

(c)

Figure 1. Schematic presentation of a lateral CMOS-SOI diode; (a) cross-section; (b) overview; and (c) Figure 1. Schematic presentation of a lateral CMOS-SOI diode; (a) cross-section; (b) overview; and cathode cross-section to demonstrate the area and perimeter of the current flow. (c) cathode cross-section to demonstrate the area and perimeter of the current ﬂow.

Although the SOI lateral diode is modeled as an ideal diode, it should be noted that the saturationAlthough current the SOIexhibits lateral perimeter diode is modeleddependence as an rather ideal than diode, area it should dependence, be noted as that in regular the saturation planar currentbulk diodes, exhibits due perimeter to the thin dependence body layer. rather Contrary than areato CMOS dependence, bulk diodes, as in regularwhere surface planar bulkeffects diodes, may duebe neglected, to the thin the body thin layer.device Contrary layer in SOI to CMOS technology bulk diodes,requires where a model surface where effects the current may be is neglected,primarily thedep thinendent device on surface layer in effects. SOI technology As a result, requires the saturation a model where current the is current strongly is primarilyaffected by dependent the surface, on surfacedetermined effects. by As the a result,device periphery the saturation as shown current in isFigure strongly 1c. affected It will by be the shown surface, thatdetermined this significantly by the deviceaffects periphery its performanceas shown in as Figure a temperature1c. It will be sensor shown and that requi this signiﬁcantlyres a careful affects calibration its performance process for as aeach temperature technology. sensor and requires a careful calibration process for each technology. 3. Thermal Characterization 3. Thermal Characterization 3.1. MOSFET Transistor 3.1. MOSFET Transistor In our previous work, we proposed to use the transistor’s threshold voltage (Vt) to determine the In our previous work, we proposed to use the transistor’s threshold voltage (Vt) to determine local temperature of each chip area [24]. This requires a careful characterization of Vt(T) and dVt/dT ofthe the local process temperature under study. of each This chip part area is performed [24]. This byrequ measuringires a careful the current-voltage characterization characteristics of VTt () and of singledVt/dT transistors of the process with relatively under study. small W This/L dimensions part is performed in order toby avoid measuring self-heating the current effects,-voltage as well ascharacteristics thermal cross-talk of single between transistors different with devices, relatively due to the small low W power/L dimensions consumption in during order operation. to avoid Inself addition,-heating theeffects technologies, as well as used thermal to fabricate cross-talk these between test devices different have devices, a BOX layer,due to 0.5 theµm low and power 1 µm forconsumption the 130 nm during and 180operation. nm processes, In addition, respectively, the technologies preventing used cooling to fabricate through these the test substrate devices have and maintaininga BOX layer, a0.5 constant µm and temperature 1 µm for the applied 130 nm by and an 180 external nm proc temperatureesses, respectively, controller preventing during the thermalcooling characterizationthrough the substrate process. and maintaining a constant temperature applied by an external temperature controller during the thermal characterization process.

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Subsequently, by monitoring the changes in Vt under actual operation, the true local temperatureSubsequently, of larger by monitoring devices can the changesbe determined. in Vt under We actualrefer to operation, this method the trueas “Threshold-Voltage local temperature ofThermometry”. larger devices can It beis determined.worthwhile mentioning We refer to thisthat method this method as “Threshold-Voltage can be implemented Thermometry”. in CMOS Ittechnology is worthwhile as mentioningwell, though that the this chip method temperature can be rise implemented will be much in CMOS smaller technology due to heat as well,conduction though to thethe chip substrate. temperature rise will be much smaller due to heat conduction to the substrate. AimingAiming to to evaluate evaluate the the behavior behavior of of MOSFET’s MOSFET’s as as temperature temperature sensors, sensors, commercially-available commercially-available MOSFETsMOSFETs with with different differentW W/L/Lratios ratios were were designed designed by by the the authors authors and and measured measured in in temperatures temperatures rangingranging from from 300 300 K K to to 550 550 K. K. The The fabrication fabrication was was performed performed in in two two different different SOI SOI partially-depleted partially-depleted technologiestechnologies [12 [12,13].,13]. TheThe experimental experimental current-voltage current-voltage curves curves as as a a function function of of the the applied applied temperature temperature have have been been obtainedobtained with with an an Agilent Agilent Technologies Technologies (Santa (Santa Clara, Clara, CA, CA, USA) USA) B1500A B1500A semiconductor semiconductor parameter parameter analyzeranalyzer and and the the temperature temperature has beenhas been controlled controlle by usingd by ausing variable a variable temperature temperature micro probe micro system probe fromsystem MMR from Technologies MMR Technologies (San Jose, (San CA, Jose, USA), CA, whichUSA), which features features a temperature a temperature control control accuracy accuracy of ±of0.01 ±0.01 K. K. AnAn example example of current-voltageof current-voltage characteristics characteristics as a function as a function of temperature of temperature for an NMOS for transistoran NMOS fabricatedtransistor using fabricated 130 nm using CMOS-SOI 130 nm processCMOS-SOI is shown process in Figureis shown2. in Figure 2.

1.4 -2 550K 10

1.2 525K

500K -4 10 1 475K 450K 0.8 425K -6

(A) 10 (mA)

0.6 400K DS DS

I ZTC I 375K point 0.4 -8 350K 10 0.2 325K 300K -10 10 0 0.5 1 1.5 0 0.5 1 1.5 V (V) V (V) GS GS (a) (b)

FigureFigure 2. 2.Current-voltage Current-voltage characteristics characteristics vs. vs. temperature temperature of anof an NMOS NMOS transistor transistor with withW/ WL =/L43.2/2.4 = 43.2/2.4 fabricatedfabricated using using 130 130 nm nm CMOS-SOI CMOS-SOI process: process: (a )(a on) on a lineara linear scale; scale; and and (b )(b on) on a semi-loga semi-log scale. scale.

These measurements show the process ZTC (zero temperature coefficient) bias point (VGS = 0.75 These measurements show the process ZTC (zero temperature coefﬁcient) bias point (V = 0.75 V) V) which is used to extrapolate the threshold voltage for each temperature. From theGS results of which is used to extrapolate the threshold voltage for each temperature. From the results of Figure2 Figure 2 the Vt vs. T curves of several NMOS transistors with different W/L ratio have been extracted the Vt vs. T curves of several NMOS transistors with different W/L ratio have been extracted for both for both technologies and are presented in Figure 3. These results are compared to Vt vs. T curves technologies and are presented in Figure3. These results are compared to V vs. T curves obtained obtained from BSIM4 MOSFET models [25] and electrical simulations in thet SPICE simulator. from BSIM4 MOSFET models [25] and electrical simulations in the SPICE simulator. This calibration curves can be used to convert the extracted Vt into the chip local temperature. This calibration curves can be used to convert the extracted Vt into the chip local temperature. As can be seen in Figure3, the proposed measurement technique is highly linear over a wide temperature range and its accuracy is determined by the precision of the threshold voltage extraction technique. In order to reduce the temperature dependence of the Vt extraction methodology and increase accuracy, the threshold voltage is extrapolated at the ZTC bias point which is exhibited in Figure2a,b [24]. The voltage and current at the ZTC bias point are given by [24]:

dVt Vgs,ZTC = Vt(T0) − T0( dT ) 2 (1) 1 2 W dVt IZTC = 2 CoxµoTo ( L )( dT ) where Vgs,ZTC and IZTC are the voltage and current at the ZTC bias point, respectively, Vt(T0) is the process nominal threshold voltage, T0 is the ambient temperature, dVt/dT is the threshold voltage sensitivity to temperature variations, Cox is the gate oxide capacitance, µo is the charge carrier’s mobility in the MOSFET channel, and W and L are the transistor’s width and channel length, respectively.

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As can be seen from Equation (1), measuring the ZTC bias points allow to easily obtain the process Sensors 2017, 17, 1739 5 of 13 thermal parameters, i.e., Vt(T0) and dVt/dT, and calculate the process thermal characterization curves.

0.4

0.35

0.3 130 nm process 0.25

0.2

0.15 Simulated V , dV /dT=-1.029(mV/K) t t 180 nm NMOS W/L=4.9/237.5, dV/dT=-1.043(mV/K) 0.1 t NMOS W/L=100/10, dV/dT=-0.998(mV/K) process

Threshold Voltage (V) t

0.05 NMOS W/L=43.2/2.4, dVt/dT=-1.011(mV/K)

Simulated Vt, dVt/dT=-1.237(mV/K) 0 NMOS W/L=5/1, dV/dT=-1.232(mV/K) t NMOS W/L=5/0.5, dV/dT=-1.246(mV/K) t -0.05 300 350 400 450 500 550 Chuck Temperature (K)

Figure 3. Vt vs. temperature for several NMOS transistors with different W/L ratios at a temperature Figure 3. Vt vs. temperature for several NMOS transistors with different W/L ratios at a temperature range of 300–550 K, which are used to calibrate the processes under study. Dots: experimental data; range of 300–550 K, which are used to calibrate the processes under study. Dots: experimental data; dashed lines: linear interpolation of the experimental data point; solid: threshold voltage extracted dashed lines: linear interpolation of the experimental data point; solid: threshold voltage extracted from I-V-T simulation obtained using the SPICE circuit simulator and BSIM4 MOSFET models. from I-V-T simulation obtained using the SPICE circuit simulator and BSIM4 MOSFET models.

FigureAs can3 alsobe seen presents in Figure the threshold3, the proposed voltage meas sensitivityurement to technique temperature is highly variations, linear i.e., over d V at /dwideT oftemperature both technologies. range Sensitivitiesand its accuracy of −1.2 is mV/Kdetermin anded− 1by mV/K the precision were calculated of the for threshold the 180 nmvoltage and 130extraction nm processes, technique. respectively. In order This to difference reduce inthe the temperature two process sensitivitiesdependence andof thresholdthe Vt extraction voltage valuesmethodology are caused and by increase different accuracy, device layer the doping threshold concentrations voltage is andextrapolated different gateat the oxide ZTC thicknesses bias point ofwhich the processes is exhibited under in study. Figure These 2a,b results [24]. The are involtage agreement and withcurrent the simulationat the ZTC results, bias point also presentedare given inby Figure [24]: 3. It is worthwhile mentioning that this thermal characterization is independent of device dimensions, as can be seen in Figure3, so it is not easily affected by process variations. dV The error in the temperature extraction=− (∆T) has been obtainedt by calculating the difference, ∆Vt, VVTTgs,00 ZTC t () ( ) between the measured and simulated V vs. T, which isdT then converted in temperature using the t (1) sensitivity presented in Figure3. Accordingly, the accuracy isdV estimated by: = 1 μ 22W t ICTZTC ox o o ()() 2 L dT V − V ∆T = t,measured t,simulated (2) where VgsZTC, and I ZTC are the voltage and currentdVt/dT at the ZTC bias point, respectively, VTt ()0 is

the Errorsprocess of nominal 3 K and 1threshold K have been voltage, calculated T0 is forthe the ambient 180 nm temperature, and 130 nm processes,dVt dT is respectively. the threshold Although careful thermal characterization is needed, i.e., Vt vs. T needs to be measuredμ once for voltage sensitivity to temperature variations, Cox is the gate oxide capacitance, o is the charge each process, the accuracy, linearity and low power consumption required for this method allow it carrier’s mobility in the MOSFET channel, and W and L are the transistor’s width and channel to be used for “on-line” temperature sensing using a “V extractor circuit” [26]. Since the significant length, respectively. As can be seen from Equation (1), measuringt the ZTC bias points allow to easily temperature rise of transistors is induced by thermoelectric effects, and since the thermal time constant obtain the process thermal parameters, i.e., VT() and dV dT , and calculate the process thermal of the channel electrons path is very short, heatingt 0 is almostt instantaneous, enabling the on-line measurementcharacterization of the curves. true temperature of transistors. In addition, due to the small dependence of this methodFigure to process 3 also variations,presents the no threshold specific sensor voltage calibration sensitivity process to temperature is needed. variations, i.e., dVt/dT of both technologies. Sensitivities of −1.2 mV/K and −1 mV/K were calculated for the 180 nm and 130 nm 3.2.processes, Lateral Dioderespectively. This difference in the two process sensitivities and threshold voltage values are caused by different device layer doping concentrations and different gate oxide thicknesses of The current flowing through an SOI lateral diode can be modeled as a forward-biased diode with the processes under study. These results are in agreement with the simulation results, also presented perimeter dependence [23]: in Figure 3. It is worthwhile mentioning that this thermal! characterization is independent of device qVpn dimensions, as can be seen in FigureI 3,= soI ·it[ expis not easily affected− 1] by process variations. (3) pn 0 n k T The error in the temperature extraction (ΔT) fhasB been obtained by calculating the difference, ΔVt, between the measured and simulated Vt vs. T, which is then converted in temperature using the sensitivity presented in Figure 3. Accordingly, the accuracy is estimated by:

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where Ipn is the diode current, q is the electron charge, kB is Boltzmann’s constant, Vpn is the voltage across the diode, T is the absolute temperature, I0 is the saturation current and nf is the ideality factor. As emphasized in the introduction, and as shown in Figure1b, the saturation current I0 is expressed in terms of the diode perimeter [12]: I0 = JSW (T) · Perimeter (4) where JSW is measured by A/µm and it is temperature dependent. The temperature dependence of the diode voltage can be derived by rearranging Equation (3):

n f kBT Ipn Vpn = [ln ( + 1 )] (5) q I0

As seen from Equation (5) there are two temperature-dependent effects changing the diode’s voltage: the increase in the saturation current I0 and the linear increase of the voltage with temperature. The ﬁrst effect is much more pronounced; hence, the diode voltage is expected to decrease with temperature when operating at constant current conditions, just like in standard CMOS diodes. The diode sensitivity under forward voltage bias conditions is calculated by differentiating Equation (3) with respect to temperature and assuming Ipn >> I0:

dVpn kBn f Ipn T dI = [ln( ) − 0 ] (6) dT q I0 I0 dT

According to Equation (6) the sensor’s expected sensitivity is negative, constant as a function of temperature, and decreases when increasing the bias current. The current-voltage characteristic of standard and commercially-available lateral diodes with different perimeters fabricated using CMOS-SOI 180 nm [12] and 130 nm [13] processes were measured as a function of temperature in the range of 300 K to 550 K. From these measurements the diode forward voltage was extracted at a constant current point by using Equation (3) for each temperature. Figure4 presents an example of the measured I-V curves as a function of applied temperature for a lateral diode with W/L = 80 µm/0.6 µm fabricated using CMOS-SOI 130 nm process [13]. Figure5 presentsSensors 2017 the, forward17, 1739 voltage extrapolated from the I-V cures shown in Figure4 as a function of applied7 of 13 temperature. Figure5a shows different devices fabricated in both technologies at a constant sensing currenta constant of 1 µsensingA. Figure current5b shows of 1 theµA. forward Figure voltage5b shows of the a diode forward fabricated voltage using of a thediode 180 fabricated nm process using at athe different 180 nm sensing process current. at a different sensing current.

-3 10

(A) -4 10 pn

-5 10

-6 10

DiodeCurrent, log I -7 10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Junction Voltage, V (V) pn (a) (b)

Figure 4. Measured current-voltage characteristics of a lateral CMOS-SOI diode with W/L ratio of Figure 4. Measured current-voltage characteristics of a lateral CMOS-SOI diode with W/L ratio of 2 8080µ m/0.6µm/0.6µ µmm fabricated fabricated using using the the 130 130 nm nm process process and and an an area area of of approximately approximately 48 48µ mµm2 for for different different temperatures:temperatures: (a ()a on) on a lineara linear scale; scale; and and (b ()b on) on a semi-loga semi-log scale. scale.

0.9

0.8

0.7

0.6 (V)

pn 0.5 V

N+P W/L = 80/0.6, dVpn/dT=-1.89 (mV/K) P+N W/L = 80/0.4, dV /dT=-1.85 (mV/K) 0.4 pn P+N W/L = 80/0.39, dVpn/dT=-1.88 (mV/K) P+N W/L = 80/0.55, dV /dT=-1.78 (mV/K) 0.3 pn P+N W/L=4.9/0.56, dVpn/dT=-1.30 (mV/K)

Simulated 180nm, dVpn/dT=-1.33 (mV/K) 0.2 Simulated 130nm, dVpn/dT=-1.92 (mV/K)

300 350 400 450 500 550 Temperature (K)

(a)

Figure 5. Cont.

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a constant sensing current of 1 µA. Figure 5b shows the forward voltage of a diode fabricated using the 180 nm process at a different sensing current.

-3 10

(A) -4 10 pn

-5 10

-6 10

DiodeCurrent, log I -7 10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Junction Voltage, V (V) pn (a) (b)

Figure 4. Measured current-voltage characteristics of a lateral CMOS-SOI diode with W/L ratio of 80 µm/0.6 µm fabricated using the 130 nm process and an area of approximately 48 µm2 for different Sensorstemperatures:2017, 17, 1739 (a) on a linear scale; and (b) on a semi-log scale. 7 of 12

0.9

0.8

0.7

0.6 (V)

pn 0.5 V

Simulated 180nm, dVpn/dT=-1.33 (mV/K) 0.2 Simulated 130nm, dVpn/dT=-1.92 (mV/K)

300 350 400 450 500 550 Temperature (K) Sensors 2017, 17, 1739 8 of 13 (a)

Figure 5. Cont. 0.9

0.8

0.7

0.6 (V) 0.5 pn V

0.4 Ipn=5 (nA), dVpn/dT= -2.1 (mV/K) I =10 (nA), dV /dT= -1.9 (mV/K) 0.3 pn pn I =100 (nA), dV /dT= -1.6 (mV/K) pn pn μ 0.2 Ipn=1 ( A), dVpn/dT= -1.2 (mV/K) Simulation results

350 400 450 500 550 Temperature T (K)

(b)

FigureFigure 5. 5.The The diode’s diode’s forward forward voltage voltage as as a functiona function of of temperature temperature (a )(a for) for different different devices devices at aat constant a constant biasbias current current of of 1 µ1A; µA; (b )(b at) differentat different bias bias currents currents for for a laterala lateral diode diode with withW /WL/L= 4.9= 4.9µm/0.56 µm/0.56µ mµm fabricatedfabricated using using the the 180 180 nm nm CMOS-SOI CMOS-SOI process. process. Dots: Dots: experimental experimental data; data Dashed; Dashed lines: lines: linear linear interpolationinterpolation of of the the experimental experimental data data point; point; Solid: Solid: simulation simulation results. results.

As shown in Figure 5, the lateral diode exhibits the same temperature dependence as the As shown in Figure5, the lateral diode exhibits the same temperature dependence as the standard standard PN diode implemented in bulk technology in the sense that the voltage decreases as PN diode implemented in bulk technology in the sense that the voltage decreases as temperature temperature increases. However, since I0 is dependent on the perimeter of the lateral diodes, the increases. However, since I0 is dependent on the perimeter of the lateral diodes, the process variations process variations limit the linearity of this method, i.e., the linear behavior of the Vpn vs. T curves, to limit the linearity of this method, i.e., the linear behavior of the V vs. T curves, to currents above currents above 5 nA, which limits the minimal power consumptionpn needed to preserve the linearity 5 nA, which limits the minimal power consumption needed to preserve the linearity of this method. of this method. For example, in the 180 nm process, for the temperature sensitivity of the transistors For example, in the 180 nm process, for the temperature sensitivity of the transistors (ca. −1.2 mV/K), (ca. −1.2 mV/K), the diode power consumption is at least 95 µW (Ipn = 1 µA and Vpn, T = 300 K = 0.95 V) the diode power consumption is at least 95 µW(Ipn = 1 µA and Vpn, T = 300 K = 0.95 V) while, if using while, if using a “Vt extractor circuit” [26] to measure the threshold voltage, the circuit power a “V extractor circuit” [26] to measure the threshold voltage, the circuit power consumption is only consumptiont is only ~50 µW. Furthermore, since the diode extracted voltage is highly dependent on ~50 µW. Furthermore, since the diode extracted voltage is highly dependent on device dimensions, device dimensions, a carful calibration process is needed in order to improve the sensor’s accuracy. a carful calibration process is needed in order to improve the sensor’s accuracy. Figure 6 presents the sensitivity, i.e., |dVpn/dT|, of the lateral diode at different temperatures and different bias currents. These curves show that the sensitivity of the diode increases when decreasing the forward current, as the voltage drop across the neutral regions of the device is less pronounced and the diode’s current is governed by recombination in the space charge region, which is of the order of the leakage current. Citing [23], it should be emphasized that the driving current needs to be low enough to avoid any self-heating while simultaneously providing a high ratio with respect to the reverse saturation (i.e., leakage) current. It can also be observed that the diode sensitivity is negative, constant over the entire temperature range (ca. −2.1 mV/K at IDS = 5 nA) and higher than the transistor’s sensitivity (~−1.2 mV/K). However, the sensitivity of the diode in CMOS-SOI technology is highly dependent on the diode perimeter and leakage currents; hence, a careful sensor calibration is needed.

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Figure6 presents the sensitivity, i.e., |d Vpn/dT|, of the lateral diode at different temperatures and different bias currents. These curves show that the sensitivity of the diode increases when decreasing the forward current, as the voltage drop across the neutral regions of the device is less pronounced and the diode’s current is governed by recombination in the space charge region, which is of the order of the leakage current. Citing [23], it should be emphasized that the driving current needs to be low enough to avoid any self-heating while simultaneously providing a high ratio with respect to the reverse saturation (i.e., leakage) current. It can also be observed that the diode sensitivity is negative, constant over the entire temperature range (ca. −2.1 mV/K at IDS = 5 nA) and higher than the transistor’s sensitivity (~−1.2 mV/K). However, the sensitivity of the diode in CMOS-SOI technology is highlySensors 2017 dependent, 17, 1739 on the diode perimeter and leakage currents; hence, a careful sensor calibration9 of 13 is needed.

-1 Ipn=5 (nA) I =10 (nA) pn -1.2 Ipn=100 (nA) μ Ipn=1 ( A) -1.4

-1.6 /dT (mV/K) /dT

pn -1.8 dV

-2

-2.2 350 400 450 500 550 Temperature (K)

Figure 6. The diode’s sensitivity (dVpn/dT) as a function of temperature extracted from the measured Figure 6. The diode’s sensitivity (dVpn/dT) as a function of temperature extracted from the measured diodediode presented presented in Figure in Figure5b. 5b.

The error in the temperature extraction (ΔT) has been obtained by calculating the difference, The error in the temperature extraction (∆T) has been obtained by calculating the difference, ∆Vpn, ΔVpn, between the measured and simulated Vpn vs. T, which is then converted into temperature using between the measured and simulated Vpn vs. T, which is then converted into temperature using the the sensitivity presented in Figure 6. Accordingly, the accuracy is estimated by: sensitivity presented in Figure6. Accordingly, the accuracy is estimated by: pn, measured − pn,si mul at ed VV Δ=T Vpn,measured − Vpn,simulated (7) ∆T = dVpn dT (7) dVpn/dT At a constant current of 1 µA, accuracies of 6 K and 4 K have been calculated for the 180 nm and 130At nm a constant processes, current respectively. of 1 µA, accuraciesIt is possible of 6 to K andachieve 4 K havehigher been accuracy calculated by increasing for the 180 the nm sensing and 130current; nm processes, however, respectively. it will increase It is the possible power to consumption achieve higher during accuracy the measurement. by increasing the sensing current; however, it will increase the power consumption during the measurement. 4. Noise Characterization 4. Noise Characterization The noise characteristics of both sensors were measured in a common source configuration as The noise characteristics of both sensors were measured in a common source configuration as presented in Figure 7. The measurement setup consists of 35670A dynamic signal analyzer (DSA), presented in Figure7. The measurement setup consists of 35670A dynamic signal analyzer (DSA), low noise current preamplifier (SR570) (including both built-in DC current source (Ioff), and a DC low noise current preamplifier (SR570) (including both built-in DC current source (Ioff), and a DC voltage source (Vb)), low-pass filter (LPF), ADC, DAC, and a personal computer (PC). The gate of the voltage source (Vb)), low-pass filter (LPF), ADC, DAC, and a personal computer (PC). The gate of device is biased by means of DAC, while the drain is supplied by voltage Vb through the current the device is biased by means of DAC, while the drain is supplied by voltage V through the current preamplifier virtual ground. The built-in DC current source provides the DUTb with the accurate DC current corresponding to the operating voltages so that only current noise is amplified by the current preamplifier and is converted to the voltage noise. DSA measures the voltage noise PSD at the current preamplifier output. The function of ADC is to control the DC voltage at the output of the current preamplifier in order to keep it in a linear regime.

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preamplifierSensors 2017, 17 virtual, 1739 ground. The built-in DC current source provides the DUT with the accurate10 DC of 13 current corresponding to the operating voltages so that only current noise is amplified by the current preamplifier and is converted to the voltage noise. DSA measures the voltage noise PSD at the current preamplifier output. The function of ADC is to control the DC voltage at the output of the current preamplifierSensors 2017 in, 17 order, 1739 to keep it in a linear regime. 10 of 13

Figure 7. Current noise measurement setup based on a common-source configuration. Figure 7. Current noise measurement setup based on a common-source conﬁguration. Figure 7. Current noise measurement setup based on a common-source configuration. The noise density spectrum was measured in the range of 1 Hz to 14 kHz for different device currents.The noiseThe The noise density input-referred density spectrum spectrum current was was measured measurednoise power in the sp range rangeectral of ofdensity 1 1Hz Hz to to(PSD)14 14kHz kHz is for shown fordifferent different in deviceFigure device 8 for currents.devicescurrents. Thefabricated The input-referred input using-referred the current current180 nmnoise noise process powerpower at spectral spectralcurrent density densitylevel (PSD)of (PSD)1 µA. is shown is In shown both in Figurecases in Figure 8the for 8 PSD for is devicesinverselydevices fabricated proportional fabricated using using the to the 180the device nm180 process nm area; process athence, current at currenta transistor level level of 1 and ofµA. 1 a InµA. lateral both In both casesdiode c theases of approximately PSD the PSDis inversely is the proportionalsameinversely area (2 to proportional µm the2 deviceand 3 µmto area; the2, respectively)device hence, area; a transistor hence were, a measured andtransistor a lateral and and diodea lateralcompared of diode approximately in of Figures approximately 8 the and same 9. the Figure area 9 same area (2 µm2 and 3 µm2, respectively) were measured and compared in Figures 8 and 9. Figure 9 (2 showsµm2 and the 3 µdependencem2, respectively) of the were noise measured current andpower compared spectral in density Figures 8on and the9. Figuredrain 9current shows for the the shows the dependence of the noise current power spectral density on the drain current for the dependenceNMOS transistor of the noise and lateral current diode. power spectral density on the drain current for the NMOS transistor NMOS transistor and lateral diode. and lateral diode.

-16 10 -16 10 Diode 4.9/0.56, Vg=1 (V), Id=1 (uA) Diode 4.9/0.56, Vg=1 (V), Id=1 (uA) TransistorTransistor 4/0.4, 4/0.4, Vg=0.6 Vg=0.6 (V), Id=1 (V), (uA) Id=1 (uA) -17-17 /Hz)

/Hz) 2

2 1010 a((a) -18-18 1010

-19 10-19 b( 10 (b)

-20 10 -20

OUTPUT Current Density,(ASpectral 10 OUTPUT Current Spectral Density,(A Density,(A Spectral Current OUTPUT -21 10 0 1 -2110 10 10 0 Frequency, (Hz) 1 10 10 Frequency, (Hz) Figure 8. Measured input-referred drain current noise PSD as a function of frequency for a (a) lateral 2 2 FigureFigurediode 8. Measured8. withMeasured area input-referred of input-referred ~3 µm ; and drain (drainb) NMOS current current transistor noise nois PSDe PSD with as as a area functiona functionof ~2 of µm of frequency fabricatedfrequency for withfor a (a the)( laterala) lateral 180 nm process. diodediode with with area area of of ~3 ~3µm µm2;2 and; and (b )(b NMOS) NMOS transistor transistor with with area area of of ~2 ~2µm µm2 fabricated2 fabricated with with the the 180180 nm nm process. process.

SensorsSensors2017 2017, 17, ,17 1739, 1739 1011 of of 12 13

-16 10 P+N Lateral Diode W/L=4.9/0.56 μ[ m/μm] Nmos Transistor W/L = 4/0.4 μ[m/μm]

-18 /Hz)

2 10

-20 10

-22 10

Cur rent Noise PSD at 1 Hz ( A -24 10

-9 -8 -7 -6 10 10 10 10 Id, (A)

2 FigureFigure 9. Current9. Current noise noise power power spectral spectral density density of an of NMOS an NMOS transistor transistor with area with of ~2areaµm of2 and~2 µm a lateral and a SOIlateral diode SOI with diode area with of ~3 areaµm 2of. ~3 µm2.

The low-frequency noise of a MOSFET in saturation is calculated using [27]: The low-frequency noise of a MOSFET in saturation is calculated using [27]: KF⋅ I ()=⋅sat DS 1 SfKFsat · I 1 (8) If,1/( ) = DS2· f SI,1/ f f CL2 (8) COXOXL f and in subthreshold: and in subthreshold: 2 KFsub · IDS 21 S ( f ) = KF⋅ I · 1 (9) I,1/ f ()=⋅C subA DSf (9) SfIf,1/ ox CAox f where KFsat and KFsub are the technological noise coefficients in saturation and subthreshold, respectively,where KFsatC oxandis the KF oxidesub are capacitance, the technologicalL is the channelnoise coefficients effective length, in saturationA is the transistor and subthreshold, area, and IDSrespectively,is the transistor Cox is DC the current. oxide capacitance, L is the channel effective length, A is the transistor area, andThe IDS PSDis the of transistor a lateral diodeDC current. is modeled according to the SPICE model as follows: The PSD of a lateral diode is modeled according to the SPICE model as follows: β KFdiode · I β 1 ( ) = KFDS⋅ I · SI,1/ f f diode DS α 1 (10) Sf()=⋅Adiode f α (10) If,1/ A f diode where α is extracted from Figure8 and is equal to 1 since we always observed a nearly 1/ f dependence ofwhereSI in the α loweris extracted frequency from range Figure of the 8 spectra.and is KFequaland toβ represent1 since we the always SPICE parameters. observed a The nearly study 1/f ofdependence the device current of SI spectral in the densitylower frequency evolution range at 1 Hz of versus the spectra. device currentKF and I DSβ allowsrepresent us tothe extract SPICE theparameters. value of β. The Figure study9 shows of the a device quadratic current relation spectral of S Idensityat 1 Hz evolution versus IDS at; thus,1 Hz βversusequals device 2. current Figure9 compares the current noise PSD of the transistor and lateral diode. As seen, between IDS allows us to extract the value of β. Figure 9 shows a quadratic relation of SI at 1 Hz versus IDS; currents of 1 nA to 0.1 µA which correspond to voltages of 0 to 0.25 V at the transistor gate thus, β equals 2. (subthreshold), the lateral diode contributes higher low frequency noise by one order of magnitude. Figure 9 compares the current noise PSD of the transistor and lateral diode. As seen, between For currents of 0.1 nA to 1 µA which correspond to voltages of 0.25 to 0.5 V at the transistor gate currents of 1 nA to 0.1 µA which correspond to voltages of 0 to 0.25 V at the transistor gate (saturation), the lateral diode contributes higher low-frequency noise by two orders of magnitude. (subthreshold), the lateral diode contributes higher low frequency noise by one order of magnitude. The noise coefficients (KF) of each device were calculated from Figure9 at different operation For currents of 0.1 nA to 1 µA which correspond−29 to voltages of 0.25− to21 0.5 V at the transistor gate regimes. Noise coefficients of KFsat = 6.3 · 10 A · F, KF = 1.2 · 10 F were calculated for the (saturation), the lateral diode contributes higher low-frequencysub noise by two orders of magnitude. transistor at saturation and subthreshold, respectively, and KF = 9.5 · 10−21 µm2 was calculated The noise coefficients (KF) of each device were calculateddiode from Figure 9 at different operation for the lateral diode. The noise measurements indicate− that the diode’s− small perimeter contributes KF =⋅6.3 1029 A ⋅ F KF =⋅1.2 1021 F highregimes. 1/f noise Noise in allcoefficients measured biasof currents,sat which is a severe, sub drawback for awere thermal calculated sensor. for the =⋅−21 2 transistor at saturation and subthreshold, respectively, and KFdiode 9.5 10 μm was calculated for

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5. Conclusions In this work the performance of SOI diodes and transistors as temperature and thermal sensors has been presented and compared. Experimental and simulation results of diodes and transistors from two different technologies showed that both sensors exhibit high linearity and sensitivity in a wide temperature range (from 300 K to 550 K). However, SOI transistors provide much more accurate and reliable temperature sensor due to a smaller dependence upon process variations without any additional calibration. In addition, the noise characterization indicates that the current of the lateral diode ﬂows at a small area of diode’s perimeter, resulting in a high 1/f noise. The higher noise is a severe drawback when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. In Table1, the main properties of both sensors are summarized and compared.

Table 1. The temperature/thermal sensors’ main properties.

Technology Area Maximum Accuracy Device S (A2/Hz) Calibration (nm) (µm2) Sensitivity (mV/K) (K) I Transistor 2 −1.2 3 1.6 × 10−19 Not needed 180 Diode 3 −2.1 6 3 × 10−17 Needed Transistor 50 −1 1 1.2 × 10−21 Not needed 130 Diode 45 −2 4 1.4 × 10−19 Needed

Acknowledgments: This work was supported by the Sarah and Moshe Zisapel nano-electronics Center at the Technion—Israel Institute of Technology. Author Contributions: The work presented in this paper was a collaboration of both authors. Maria Malits designed/performed the experiments and wrote the paper. Yael Nemirovsky revised the paper. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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