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3D Integration for Novel Pixel Detectors: Current Status and Future Promise

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3D Integration for Novel Pixel Detectors: Current Status and Future Promise 3D integration for novel pixel detectors: current status and future promise Valerio Re Università di Bergamo Sezione di Pavia Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 Outline • What is 3D integration? Why did it trigger a wide interest in our community? • Evolution from 2D devices to 3D integration for advanced pixel sensors and readout electronics in high energy physics experiments • Expectations, experience, plans: current status and future promise (a personal view) Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 2 Advancing the state of the art of pixel sensors for a next generation of HEP experiments New demanding specifications for experiments at new machines (HL-LHC, International Linear Collider,…): • Improve resolution shrink pixel size and pitch, down to 20 mm or even less • Preserve or even increase pixel-level electronic functions handling of high data rates (hit rates > 10 MHz/mm2), analog-to digital conversion, sparsification, intelligent data processing…: presently this also contributes to limiting the minimum size of pixel readout cells • Decrease amount of material thin sensor and electronics chips, “zero mass” cooling Necessary to reduce errors in track reconstruction due to multiple scatterings of particles in the detector system 50 -100 mm total thickness Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 3 New ideas for 3D integration in photon science Potential benefits of new microelectronic technologies to future detector systems for X-ray imaging at free electron laser facilities: . Reduction of pixel size (100x100 mm2 or even less), presently limited by the need of complex electronic functions in the pixel cell . Larger memory capacity to store more images . Advanced pixel-level processing (1 – 10000 photons dynamic range, 10-bit ADC, 5 MHz operation) . 4-side buttable tiles for a large area detector with minimum or no dead area Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 4 What is 3D integration? • 3D electronics: “the vertical integration of thinned and bonded silicon integrated circuits with vertical interconnects between the IC layers.”1 • 3D electronics has the potential of being: – Denser (smaller form factor) – Faster (reduced delay because of shorter interconnects) – Lower power (smaller interconnect capacitance) – Lower cost (sizably less expensive than aggressive CMOS scaling) – Integration of dissimilar technologies (sensor, analog, 1) Philip Garrou, Christopher Bower, Peter Ramm, digital, optical) Handbook of 3D Integration Technology and Applications of 3D Integrated Circuits,Wiley-VCH, 2008. Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 5 The diversity of 3D integration 3D-IC: TSVs approaches: “via first” vs “via last” – dry etching (RIE or Bosch) for “drilling” Material Thermal Thermal conductivit coefficient Different approaches to 3D integration differ in termsTSVs ’ ofcav theities; tyminimumpically 1:5 -1:10 /d; y (ppm/K) (laser drilling used too) allowed pitch of bonding pads between different layers and of vertical (W/m/K) – could be extensions of STI process in ICs Through-Silicon Vias (TSVs) across the silicon substrate. Si 149 2.6 – cylindrical vias, >3 µm filled with electro- Via first, Via middle: Vias are part of wafer plated Cu; W doesn’t work well for >2 m SiO2 1.4 0.5 processing at the CMOS foundry, and are inserted– Cu serious issues with thermal stress Al 235 23.1 before or right after the fabrication of transistorsin Si inter face; W used in high density TSVs W 170 4.5 – Annular TSV geometries are popular, Cu 410 16.5 High density TSVs (few mm pitch) through especially with W filling thinned wafers, allow multiple connections at the contrary to popular belief, TSVs low density TSV: cell (pixel) level between transistor layers are not effective in assisting the transport of heat – Through unthinned or partially thinned Via last: Vias are fabricated on fully processedw afers to bring connectivity at the pad high density TSV: CMOS wafers, at a facility outside the CMOS level (3D-SOC), • Large cavity diameter >50 m foundry – Through thinned wafers to bring connectivity to • Cavity completely filled or cavity walls local connections between transistor layers plated (poly-Si, Copper) (groups of transistors in 3D-IC) or individual Low density TSVs (tens of mm pitch) devices (3D-SIC) through unthinned wafers or partially thinned • Ultra small cavity diameter ~1 m • Cavity completely filled with W wafers, allow connectivity at the pad level in • Liner obtained with SiO2 the chip periphery 10 532. WE-Heraeus Seminar, May 23-25, 2013 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 6 Tezzaron “via middle” 3D process (Fermilab 3D-IC Consortium with INFN and IN2P3) Through-Silicon Vias (TSV) are etched at early stages of a 130nm CMOS process (after transistor fabrication) at GlobalFoundries. High-density, low-mass bonding of CMOS wafers is achieved by a Cu- Cu thermocompression process. Tezzaron vias are very small: Fvia=1.2 mm, Flanding_pad=1.7 mm, dmin=2.5 mm Wafer bonding pads are nominally on a 4 mm pitch Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 7 An INFN 3D CMOS active pixel sensor in the 3D-IC run 337 0.95 ms ns Pixel-level functionalities: charge sensing 0.2 s and amplification in the analog layer, double- Digital readout hit detection capability (two flip-flops), 5- x282 0 bit time stamp and zero suppression logic in the digital layer bunch train intervalintertrain interval Pixel pitch: 20 mm, 256x256 matrix designed according to ILC specifications Pixel “fill factor”: MIP-generated charge is collected by a large deep N-well (DNW) electrode; area of PMOS N-wells in the sensor layer is very small so that detection efficiency is not degraded t X Y u t t e e O shaperless FE (SFE) discriminator p G G t e m AVDD AVDD DVDD s a e t R S r k e Token e l t m C i l s l h passing core T a e e c I nter- t ier l t C M I FB b a a N L bond pads n N E 5 S NQ HI T D Q ST RO_EN 5 FFSRK CP T_I N T_O FFD t ime stamp regist er R Q NHI T NQ 5 K NRO_EN Vt n e k KillMaskI n o n I DGND T D Q D NQ HI T D Q ST RO_EN 5 5 CP CP CP T_I N T_O CF t ime stamp KillMaskClk FFD FFDR FFD NQ Q NQ regist er AGND R NHI T NRO_EN 5 p TIER 1 TIER 2 e m a TokenOut m i t n T I (BOTTOM) (TOP) KillMaskOut Token S passing core Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 8 Layout of the 2-tier 20 mm x 20 mm pixel cell SDR1 prototype elementary cell: bottom and top t iers Inter-tier Discriminator Inter-tier Discriminator connections NMOS connections PMOS m m 0 2 DNW sensor 20 mm 20 mm DNW sensor and Digital front-end Competitive preamplifier NMOS N-well 13th Vienna Conf erence on I nst rument at ion, 11- 15 February 2013, Vienna, Aust ria Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 9 The first 3D DNW CMOS sensors: experimental results The processing of 3D devices started about 4 years ago at Tezzaron/GlobalFoundries and, after many technical problems, only in summer 2012 fully functional chips were delivered. This is a signature that advanced 3D technologies have not yet reached a full maturity. Logic blocks An example of what can go wrong: misalignment in inter-tier connection pads However, eventually very good test results on fully working 3D chips provide a demonstration of the potential of 3D integration, and stimulate further work. Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 10 3D processing and MOSFET performance Processing steps associated to 3D integration involve TSV etching and filling (with mechanical stress on surrounding regions of the silicon bulk), wafer bonding at relatively high temperatures, wafer thinning (12 mm), … These steps do not degrade performance of transistors in the thinned layer, with respect to standard CMOS devices in the same 130nm technology node 30 100 ] 2 / NMOSFET 1 z 25 W=1000 mm H / L=0.35 mm V n [ 3D process 20 ] V =0.6 V m DS planar 130 nm process u V r / t c A 15 e 10 p m [ S m e g 10 g a NMOS 600/0.35 t 3D process l o V = 0.6 V planar process V DS 5 e s I = 50 mA i D o 0 N 1 0 0.2 0.4 0.6 0.8 1 103 104 105 106 107 I [mA] Frequency [Hz] D Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 11 Tests on digital and analog section 7 SDR1 chip of(S p3Dars iDNWf ied Di gsensorsit al Read out 1) FI RST HI T- FF o Tests on SDR1 digital circuits show the full functionality of vertically integrated chips DETECTOR CELL ENABLE (when it is low, it enables t he FI RST- HI T FF) 1 2nd latch 11sstt FFlatch MASTER RESET 2nd FF (when it is low, it reset t he FF) 0.8 Pixel (2,5) y y c c of a 8x8 n n 0.6 e i e c i i matrix f c f VTH i e PA OUTPUT f f g n 0.4 e i r i F g n i r i 0.2 Hit Reset F OUTPUT SI GNAL 0 of t he FI RST- HI T FF 368 372 376 380 384 388 392 396 400 ThrVesoltahgeo ldThr esvoholdltage [mV] [mV] A.
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