3D Integration for Novel Pixel Detectors: Current Status and Future Promise

3D integration for novel pixel detectors: current status and future promise

Valerio Re

Università di Bergamo Sezione di Pavia

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 Outline

• What is 3D integration? Why did it trigger a wide interest in our community?

• Evolution from 2D devices to 3D integration for advanced pixel sensors and readout electronics in high energy physics experiments

• Expectations, experience, plans: current status and future promise (a personal view)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 2 Advancing the state of the art of pixel sensors for a next generation of HEP experiments New demanding specifications for experiments at new machines (HL-LHC, International Linear Collider,…):

• Improve resolution  shrink pixel size and pitch, down to 20 mm or even less • Preserve or even increase pixel-level electronic functions handling of high data rates (hit rates > 10 MHz/mm2), analog-to digital conversion, sparsification, intelligent data processing…: presently this also contributes to limiting the minimum size of pixel readout cells • Decrease amount of material  thin sensor and electronics chips, “zero mass” cooling Necessary to reduce errors in track reconstruction due to multiple scatterings of particles in the detector system 50 -100 mm total thickness

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 3 New ideas for 3D integration in photon science

Potential benefits of new microelectronic technologies to future detector systems for X-ray imaging at free electron laser facilities:

. Reduction of pixel size (100x100 mm2 or even less), presently limited by the need of complex electronic functions in the pixel cell

. Larger memory capacity to store more images

. Advanced pixel-level processing (1 – 10000 photons dynamic range, 10-bit ADC, 5 MHz operation)

. 4-side buttable tiles for a large area detector with minimum or no dead area

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 4 What is 3D integration? • 3D electronics: “the vertical integration of thinned and bonded silicon integrated circuits with vertical interconnects between the IC layers.”1

• 3D electronics has the potential of being: – Denser (smaller form factor) – Faster (reduced delay because of shorter interconnects) – Lower power (smaller interconnect capacitance) – Lower cost (sizably less expensive than aggressive CMOS scaling) – Integration of dissimilar technologies (sensor, analog, 1) Philip Garrou, Christopher Bower, Peter Ramm, digital, optical) Handbook of 3D Integration Technology and Applications of 3D Integrated Circuits,Wiley-VCH, 2008.

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 5

The diversity of 3D integration 3D-IC: TSVs approaches: “via first” vs “via last” – dry etching (RIE or Bosch) for “drilling” Material Thermal Thermal conductivit coefficient Different approaches to 3D integration differ in termsTSVs ’ ofcav theities; tyminimumpically 1:5 -1:10 /d; y (ppm/K) (laser drilling used too) allowed pitch of bonding pads between different layers and of vertical (W/m/K) – could be extensions of STI process in ICs Through-Silicon Vias (TSVs) across the silicon substrate. Si 149 2.6 – cylindrical vias, >3 µm filled with electro- Via first, Via middle: Vias are part of wafer plated Cu; W doesn’t work well for >2 m SiO2 1.4 0.5 processing at the CMOS foundry, and are inserted– Cu serious issues with thermal stress Al 235 23.1 before or right after the fabrication of transistorsin Si inter face; W used in high density TSVs W 170 4.5 – Annular TSV geometries are popular, Cu 410 16.5  High density TSVs (few mm pitch) through especially with W filling thinned wafers, allow multiple connections at the contrary to popular belief, TSVs low density TSV: cell (pixel) level between transistor layers are not effective in assisting the transport of heat – Through unthinned or partially thinned Via last: Vias are fabricated on fully processedw afers to bring connectivity at the pad high density TSV: CMOS wafers, at a facility outside the CMOS level (3D-SOC), • Large cavity diameter >50 m foundry – Through thinned wafers to bring connectivity to • Cavity completely filled or cavity walls local connections between transistor layers plated (poly-Si, Copper) (groups of transistors in 3D-IC) or individual  Low density TSVs (tens of mm pitch) devices (3D-SIC) through unthinned wafers or partially thinned • Ultra small cavity diameter ~1 m • Cavity completely filled with W wafers, allow connectivity at the pad level in • Liner obtained with SiO2 the chip periphery 10 532. WE-Heraeus Seminar, May 23-25, 2013 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 6 Tezzaron “via middle” 3D process (Fermilab 3D-IC Consortium with INFN and IN2P3)

Through-Silicon Vias (TSV) are etched at early stages of a 130nm CMOS process (after transistor fabrication) at GlobalFoundries. High-density, low-mass bonding of CMOS wafers is achieved by a Cu- Cu thermocompression process.

Tezzaron vias are very

small: Fvia=1.2 mm,

Flanding_pad=1.7 mm,

dmin=2.5 mm

Wafer bonding pads are nominally on a 4 mm pitch

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 7 An INFN 3D CMOS active pixel sensor in the 3D-IC run 337 0.95 ms ns Pixel-level functionalities: charge sensing 0.2 s and amplification in the analog layer, double- Digital readout hit detection capability (two flip-flops), 5- x282 0 bit time stamp and zero suppression logic in the digital layer bunch train intervalintertrain interval Pixel pitch: 20 mm, 256x256 matrix designed according to ILC specifications Pixel “fill factor”: MIP-generated charge is collected by a large deep N-well (DNW) electrode; area of PMOS N-wells in the sensor layer is

very small so that detection efficiency is not degraded

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T I (BOTTOM) (TOP) KillMaskOut Token S passing core

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 8 Layout of the 2-tier 20 mm x 20 mm pixel cell SDR1 prototype elementary cell: bottom and top t iers

Inter-tier Discriminator Inter-tier Discriminator

connections NMOS connections PMOS

0 2 DNW sensor

20 mm 20 mm DNW sensor and Digital front-end Competitive preamplifier NMOS N-well 13th Vienna Conf erence on I nst rument at ion, 11- 15 February 2013, Vienna, Aust ria

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 9 The first 3D DNW CMOS sensors: experimental results The processing of 3D devices started about 4 years ago at Tezzaron/GlobalFoundries and, after many technical problems, only in summer 2012 fully functional chips were delivered. This is a signature that advanced 3D technologies have not yet reached a full maturity.

Logic blocks

An example of what can go wrong: misalignment in inter-tier connection pads

However, eventually very good test results on fully working 3D chips provide a demonstration of the potential of 3D integration, and stimulate further work.

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 10 3D processing and MOSFET performance Processing steps associated to 3D integration involve TSV etching and filling (with mechanical stress on surrounding regions of the silicon bulk), wafer bonding at relatively high temperatures, wafer thinning (12 mm), … These steps do not degrade performance of transistors in the thinned layer, with respect to standard CMOS devices in the same 130nm technology node

30 100

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i D o 0 N 1 0 0.2 0.4 0.6 0.8 1 103 104 105 106 107 I [mA] Frequency [Hz] D

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 11 Tests on digital and analog section 7 SDR1 chip of(S p3Dars iDNWf ied Di gsensorsit al Read out 1)

FI RST HI T- FF

o Tests on SDR1 digital circuits show the full functionality of vertically integrated chips DETECTOR

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A. Manazza, “CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking”, NSS2012, Oct.29 – Nov. 3, 2012

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 12 3D DNW MAPS: analog front-end characterization

• Charge sensitivity: 550 mV/fC • Input linear dynamic range: 1500 electrons • ENC: 40 electrons rms • Power dissipation: 5 mW/pixel (with power cycling capability)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 13 3D integration improves efficiency of DNW CMOS sensors

In the first 3D-IC run, besides “ILC-like” devices, we had also DNW CMOS sensors with continuous sparsified readout (originally developed for SuperB, which was then cancelled), called APSEL. Beam test results on these 3D APSEL prototypes confirm the advantage in charge collection efficiency with respect to previous 2D versions, because Apsel3Dof _theT reductionC – ofa then areaal ofo competitiveg-tie PMOSr o N-nwells.ly S. Bettarini, G. Casarosa, F. Morsani, A. Perez, G. 2D 3D Rizzo, VIPIX meeting, March 2013

tested on beam (2011): ‣ 3x3 cluster signal MPV ≃ 1000 e– 7xENC ‣ S/N ≃ 23 ‣ efficiency ≃ 98% at thresholds up to 7xENC differential spectrum of the 3x3 pixels (55Fe): PH seed cut (e–)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 14 tested with a 55Fe source: ‣ 5.9 keV , 1640 e– ≃ 2xMIP

‣ measured gain ≃ 320 mV/fC (half the expected value) and quite dispersed

๏ feedback capacitance of the preamplifier realized exploiting parasitic capacitance of two tracks ๏ value estimated from post-layout simulations: not reliable (→ low gain) and quite dispersed (→ dispersed gain)

March 27th 2013 Giulia Casarosa 14 3D integration reduces digital-to-analog interferences

In the APSEL chips, the digital readout is always up and running (50 MHz clock), sending out data from hit pixels. In 2D versions, coupling of digital signals to the analog front-end was not negligible.

No significInant theindu 3Dctio nversion,s visible athankst the an atolo gthe out pseparationut of pixel (3 of1,7 )the: analog and digital tested at vsubstratesery high clk r, adigitaltes: -to-analog interferences are drowned in the electronic noise and do not give spurious hits. ๏ rdclk = 50 MHz (20ns) ๏ BC ≃ 2.5 µs readout running: S. Bettarini, G. Casarosa, ๏ checked that pixels F. Morsani, A. Perez, G. beloning to the same data valid Rizzo, VIPIX meeting, MP as pixel 31,7 are March 2013 fired MLE analog output ‣ small induction, order of the noise (2 mV) due to the clk, on chip? testboard? BC ‣ 1/4 MIP (10mV) ≃ 5 x noise ‣ safe operations 2µs

5mV

MIP ≃ 40 mV March 27th 2013 Valerio Re – XCIXGiulia Congresso Casarosa Nazionale SIF – Trieste – September 24, 201317 15 A new generation of 3D chips The yield, reliability and turnaround time of the aggressive 3D process we used so far still seem to be an issue.

Since an experimental proof of 3D-related performance advantages was provided by the first 3D-IC run, there are plans for submitting two new 3D chips, whenever a viable access is provided to the technology.

1) Large-scale 3D deep N- well MAPS (3D APSEL)

1) 3D readout chip for high resistivity pixel sensors (SUPERPIX1) Both chips share a new flexible readout architecture (data push & triggered Front-end electronics integrated in the 50 mm x 50 mm version) to handle a hit cell of Superpix1 (2 layers of 130 nm CMOS) rate of 100 MHz/cm2

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 16 Layout and electronic functions in a 2-tier pixel readout cell (50 x 50 mm2)

Analog tier

Digital tier (includes a pulser for an accurate calibration of the pixel cell)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 Perspectives and support to 3D integration in the semiconductor detector community 3D integrated circuits based on homogeneous layers (same CMOS technology) and high density TSVs and interconnections are a very promising approach to advanced pixel detector readout and other applications. The AIDA WP3 project is supporting the less aggressive “via last” variant of 3D integration, where low-density TSVs are etched in fully processed CMOS wafers. It is a mature technology, presently available at various vendors. This technique makes it possible to use heterogeneous layers ( different technologies) for sensors and front-end electronics and to fabricate four-side buttable devices with minimal dead area. A high-resistivity, fully depleted sensor can be combined in a low-mass assembly with a readout chip designed in an aggressively scaled CMOS generation (usually not available in the typical MAPS “Opto”processes), both with excellent radiation hardness (among other properties). Low-density peripheral TSVs can be used to reach backside bonding pads for external connection. The interconnection technology can be chosen according to the pixel pitch. Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 18 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 19 The AIDA WP3 task: establish a network for the investigation and qualification of 3D interconnection technologies • Explore 3D integration of heterogeneous layers: interconnection of layers fabricated in different technologies, “via last” technique for Through- Silicon Vias.

• Different options for the pixel sensors (high resistivity fully-depleted detectors and CMOS sensors) and for the readout electronics (130 nm and 65 nm CMOS, 3D integrated circuits)

• Different specifications for the interconnection technologies: relatively mature 3D processes for peripheral TSVs and for interconnection: high confidence level for the fabrication of demonstrators in the AIDA time span.

more aggressive 3D processes for a low pitch (< 50 mm) for TSVs and interconnection as required to fully exploit 3D potential: higher level of risk but clear added value in view of future designs of advanced pixels (high resolution and high integration density for an intelligent pixel-level processing)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 20 The diversity of 3D in the WP3 subprojects

• LHC (ATLAS) pixel upgrades and high resistivity pixel sensors Four-side buttable pixel modules with ATLAS FE-I4 readout chip and via last TSV processing, low-density (Bonn/CPPM)) and potentially high- density (MPI and others) New 65 nm pixel readout chips in a 3D assembly with pixel sensors (LAL/LAPP/LPNHE))

• Pixels for linear colliders, B-factories,… with CMOS sensors, APDs,… Designs of 3D CMOS chips based on the 3D integration of two 130nm layers (INFN, Barcelona), evaluating alternatives for CMOS (IPHC- Strasbourg) and “via last” TSVs (INFN-IPHC)

• Photon science with silicon and High-Z detectors 4-side buttable imaging sensor tiles (CERN-MEDIPIX3), 3D mixed-signal integrated circuits (RAL/Uppsala) Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 21

Bonn/CPPM: via last TSV process on ATLAS pixel chips

• The goal of the project is to develop modules for ATLAS pixel detector at the HL-LHC using a via last TSV process – Post-processing technology applicable on existing FE electronics – Dead area at the chip periphery can be reduced

 Compact, low mass hybrid pixel modules with minimal modification to the FE layout and using standard CMOS technology  Potential for 4 side buttable modules using dedicated sensor layout

• Modules with TSV can be used for the outermost detector layers at the HL-LHC to provide full detector coverage over the large area

ATLAS IBL module Example of TSV module

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 22

! m m

MPP/GLA/LAL/LIV/LPNHE: ICV-SLID process on FE-I4 Goal: demonstrator ! module for SLID and TSV technologies based on ATLAS FE-I4 2  Project in collaboration with Fraunhofer EMFT, to develop Similar to Bonn/CPPM Inter Chip Vias (Via Last approach) to show the feasibility project, but more to transport signals and services on the backside using the ‘aggressive technology existing FE-I4 chip SLID ok for smaller  Inter-Chip-Vias to be etched on each wire bonding pad, cross section ~ 10x30 mm2 pitch  Chip and sensor connected using SLID technology  potentially, 3µm 1:10  Active edge sensors to remove inactive area associated vias with Guard Ring structure  Small pitch possible (~ 20 mm, depending on pick & place precision).  Stacking possible (next bonding process does not affect previous bond).  Wafer to wafer and chip to wafer possible.

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 23 Goal of t he project INFN-IPHC: 3D integration of a readout chip with a sensing Goal oflayer t he (highproje-crest CMOS sensor or active edge) Goal of t he projeDcetsi gn and f abricat ion of a mult i- t ier pixel sensor result ing f rom t he • vMerultit ica-ltier int e pixelrconn esensorct ion o fresulting a readou fromt chip the and 3D of integrationa sensing la yofer a readout Design and f abricat ion of a mult i- t ier pixel sensor result ing f rom t he Tezzarochipn vert icandal int eofgra taio nsensing (3D) t echn olayerlogy vert ical int erconnect ion of a readout chip and of a sensing layer TSV WB/ BB pad Design and f abricat ion of a multIni -wafteir-elevrel , tphriexe-deimle nssionealn prsocoesrse s, result ing f rom t he CmMultOipleS st rratea oaf dplaonaur tde vciches iapre, stbacakesde andd on a 130 nm vertically vert ical int erconnect ion of a reaindteorcounntec tecd husinpg t hraounghd sil icon fvia s a(T SVs) ensing layer in3tD eprgocresasets eredly uporn tohec feolslowsin g( eTnaeblzingz aron/GlobalSfuopeurpnixd1 raniaelosg )f ront - end technoloCgiMes OS readout chip, based on a 130 nm vertically I nt er- t ier bond pads Fabrication of electrically isolated connections Successfulthrougihn tttestshee silgicorn asutb setonradte ( pTMAPSSrV oforcmeatisons) chips(Tezz afromron/G lobalfoundries)

CMOS reado1 ut chip, bSaubssteratde t hoinnin ga (b e1low3 50 μ mn) m vertically

the first MPW run (but very long w Inter-layer alignment and mechanical/electrical

integrated pa rocess (Tezzaron/Globalfoundries)

f bonding e turnaround time, low yield); new pixel r Tezzaron Semiconductor technology (via middle vertical interconnection process ( -bumps by T-Micro) approach, vias are made between CMOS and readoutBEO Lchip) can be uatsed t oan vert icadvancedally integrate two design stage, 1submit30 nvme CMrOtSi cla ayifelr s isprocessnpetcieficralcly oprnocne seissecd tbavailableyi on proces s ( -bumps by T-Micro) Globalfoundries

Vert icaGllylo binatlfeogurnadtreides lapryoevrisd e s a 130 nm CMOS process with several different options; chosen voener fteaitcuraesl 1 ipnolyt, e6 mrectaol lnayneres, c2 toipo mnet apls,r douacl geatse (sco r(e an-db thuicmk opxidse dbevyic esT, -Micro) Preliminary test of the T-Micro integration process performed on pre-existing 3.3 V), N- and PMOS with different Vth readout chips (SupCerpMix0) Oand Shigh rseseistnivitsy in-nong-n p ilxeal syenesorrs ( V(PixX1) FAB, edgeless (or 3D slim edge)

“I nt erconnect ion of a 3D chip t o edgeless and CMOS sensors wit h advanced t echniques”, 2 nd AI DA Annual Meet ing, 10- 12 April 2013 5 Very high interconnect densitySensors in the red box (15 or 5 mm pitch) 350 nm, or an alternhave nto meitalv layeers fully depleted, planar silicon “I nt erconnect ion of a 3D chip t o edCgeleMss andO CMOSS s enssores wnit h sadviancegd t e culhndnaeirq uthyees m”a,er k2ernsrd A I D(AX AnnFual AMeetBing, , 1 0- 12 April 2013 3 process in 180 nm) detecetdogre (lfersosm (o FrB 3KD, Tslriemn teod)g e) PreliminarySuperpix0 chip layout tests on 2D 130nm 128x32 readout 350 nm, or an alternative fully depleted, planar silicon CMOS senschipiFnrognt- enlda candhyipes arnd a (planarpiXxel FsenAsor Bwaf,e r n-on-n pixel sensors shipped to T-Micro in Dec. 201p2 rocess in 180 nm) edgeless (or 3D slim edgdee) tector (from FBK, Trento) 350 nm, or an altTehrnea tpivreo ject is t o be regarded fmullayi ndleyp laetse duR-bu,&mp pDla,n aarl tshiliocuogn h t he proposed pixel 6 vseenrtsoicrally integrated Alternative: CMOS sensing process in 180 nmde) vice is aimed chfipso harve beaen sphipppedl icat iondse t eoc teoxrp (efrriomme FnBtwKsire ,b o naTd tr etnhtoe) next generat ion The projectba cki tso I talty, otes ts baree regarded mainly as R&D, layeralt h,o withugh hight he -presistivityroposed infro pnrto-egnredss colliders – SuperBchip, HL- LHC device is aimed f or applicat ions t o experiment sepi a tor t substratehe next generat ion The project“I nt ercoinnesct ion of ta 3D ochip t o edbgelesse and CMOrS seensors gwit h advancred tdechniqeues”, d2 nd AI DA mAnnual Maeet inig, n10- 1l2 Aypril 2 013a 1s4 R&D, alt hough t he proposed In the fourc otestedllider ssamples, – Supe respectivelyrB, HL- LH 1%,C 2%, 8% andPCB 24% of the device is aim“eI ndt e rcfononrec t iaonp opf lai c3Da tchiiop ntos e dtgeole sse axndp CeMrOiSm seennsotrss w iatht a dtvahnceed nt eechxnitqu esg”,e 2nnde ArI aDAt iAonnu al Meet ing, 10- 12 April 2013 2 colliders – SinterconnectionsuperB, HL- LH Cwere found not to work properly. – would use some improvement“I nt erconne calsot ion o Valeriofin a the3D c Reh iotherp t–o XCIXedg ecasesle sCongressos and CMOS Nazionalesensors wit h SIFadva –nc eTriested t echn iq–u eSeptembers”, 2 nd AI DA 24,Annu 2013al Mee t ing, 10- 12 April 202413 2

“I nt erconnect ion of a 3D chip t o edgeless and CMOS sensors with advanced t echniques”, 2nd AI DA Annual Meeting, 10- 12 April 2013 2 IPHC: 3D integration of 2 layers in the 180 nm Tower/Jazz process (with thick high-res epi)

TOWERjazz® CIS 0.18 µm CMOS, 18 µm thick, > 1 kΩ cm epi layer, quadruple well process (both NMOS and PMOS allowed on pixel array) NMOS PMOS Depletion of high-resistivity Pwell Nwell Pwell Nwell Pwell Deep (Buried) Pwell active layer for higher radiation hardness and thicker sensitive region possible with P- epitaxy AC coupling between small

P++ substrate pixel diode and front-end amplifier Wafer Cross Section

Alternatives for thick high-resistivity substrate are available (ESPROS: detector grade, n-type,fully depleted 50 µm thick bulk silicon) Proposal for the 3D face-to-face interconnection of 2 CMOS layers (sensor/analog front-end + digital readout) from the 180nm TowerJazz process with SLID bonding by Fraunhofer IMS in Duisburg (submission: end of 2013) Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 25 LAL/LPNHE: 3D integration of pixel sensors with 65 nm readout chip

Combine major technology advances and evaluate potential benefits of 3D interconnections  OmegaPix with Tezzaron/Globafoundries  65 nm : work in coordination with CERN, goal to design a new pixel readout chip  Collaborative work with « open » TSV providers in Europe to demonstrate TSVs on functional chips (IPDIA, CEA LETI).

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 26 Towards the conclusions: future applications of 3D vertically integrated pixels The first 3D-IC run provided demonstrators of 3D CMOS chips, and confirmed potential advantages of 3D integration. The problems associated with this run do not seem to prevent the AIDA community to continue pursuing 3D as a way of devising advanced pixel detectors.

The “via last” approach is being tested with encouraging results by AIDA groups, both for HEP and imaging applications, and may open the way to new design ideas.

A few of these new concepts (inside and outside the WP3 network) exploiting 3D integration for particle tracking and vertexing and for X-ray imaging at FELs will be discussed in the following slides: they may combine the key AIDA technologies (3D integration, CMOS 65 nm)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 27 2 Two(+) PS module versions presented 3D techniques in a pixel-strip module for a prompt

momentum discriminating tracker at HL-LHC SSA Strip senProvidesor information for Level-1 trigger processing, with 5 local rejection of signals from low-momentumCooling particles. 2. Foresee cocorrelatingmpa signalstib inil twoit closelyy w-spacedith sensors TS. Vs in Substrate Pixel SenOptimizesor pT cut by tuning sensor spacing and acceptance window. MPA the centeTSVr oat fthe t peripheryhe m of theo dpixelu ASICsle f “obridgingr ” two rows of chips in the middle, avoiding regions of stub finding inefficiency poweStrrip isensor g and hit sharing

Cooling

Substrate SSA Pixel Se nsor Strip sensor .

D. Abbaneo, A. Marchioro, A hybrid Cooling module architecture for aJu promptne 201 3 [email protected] momentum MPA discriminating tracker at HL-LHC, Substrate JINST 7 C09001 Pixel Sensor Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013

June 2013 [email protected] Enabling technologies for high-performance 4-side buttable X-ray imaging module: active edge pixel sensors, through-silicon vias, 65 nm CMOS,… Large area detectors with no or minimum dead area to be used at next generation FEL experiments

Lodovico Ratti et al, INFN PIXFEL project, 2013

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 WhaAt w3De reintegratedally want : circuitAGIPD (AGIPD) 3-tier AS forICs the readout of edgeless pixel sensors for X-ray imaging at XFEL > mid term: “logic – on - memory” 1) bump-bond to the detector 5) digital 2) amplification & signal double sampling readout

tech #1 (CMOS Low Pow) Heinz Graafsma, 532.WE-Heraeus Seminar,May 2013 tech #2 (CMOS High Perf) 3) ADConversion

tech #3 4) store the digitalized (DRAM) signal in a digital memory cell

532. Heraeus-Seminar l May 2013 | Page 33 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 Conclusions

The first 3D-IC run provided demonstrators of 3D CMOS chips, and confirmed potential advantages of 3D integration. The problems associated with this run do not have to prevent us to continue pursuing 3D as a way of devising advanced pixel detectors.

3D integration is progressing in the microelectronic industry, and we have to be ready to exploit it. Ultimately, it may allow designers to avoid using sub-50 nm processes for analog and digital circuits in very small pixel readout cells.

R&D activities in these technologies have to be supported by our community, since they enable new concepts for detector systems. AIDA WP3 is doing this job of testing diverse approaches to 3D.

New detector ideas exploiting 3D integration are being proposed, for particle tracking and vertexing and for X-ray imaging at FELs.

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 31 The INFN VIPIX collaboration

VIPIX - Vertically Integrated PIXels

G. Batignani1, S. Bettarini1, G. Casarosa1, M. Dell’Orso1, F. Forti1, P. Giannetti1 , M. A. Giorgi1, F. Morsani1, N. Neri1, E. Paoloni1, M. Piendibene1, G. Rizzo1 L. Ratti2, V. Speziali2, M. Manghisoni2,3, V. Re2,3, G. Traversi2,3, L.Gaioni2 , A. Manazza2, S. Zucca2 L. Bosisio4, L. Lanceri4 G. Bruni5, M. Bruschi5, R. Di Sipio5, B. Giacobbe5, F. M. Giorgi5, A. Gabrielli5, C. Sbarra5, N. Semprini5, M. Villa5, A. Zoccoli5, M. Caccia6, F. Risigo6 G.F. Dalla Betta7 , A. Repchankova7, V. Tyzhnevyi7, G. Verzellesi7 L. Bissi8, P. Ciampolini8, A. Marras8, G. Matrella8, P. Placidi8, E. Pilicer8, D. Passeri8, L. Servoli8, P. Tucceri8 E. Bernieri9, G. Conte9, M. C. Rossi9, G. Assanto9, L. Colace9, E. Spiriti9 1INFN Pisa 2INFN Pavia 3Università di Bergamo 4INFN Trieste 5INFN Bologna 6INFN Milano 7Università degli Studi di Trento and INFN Padova 8INFN Perugia 9INFN Roma III

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 32 Backup slides

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 33 First MPW run of the 3D-IC consortium

 Several groups from US and Europe TXL TYL TYR TXR have been involved in the first 3D MPW AL BL BR AR for HEP (pixel and strip readout chips CL DL DR CR for ATLAS, CMS, B-factory, ILC) and photon science applications (X-ray F1EL E1FL E2FR F2ER imaging) GL HL HR GR  Single set of masks used for both tiers to save money IL JL JR IR  identical wafers produced by Chartered (now GlobalFoundries) and face-to-face bonded by Tezzaron symmetry line  backside metallization by Tezzaron

F1 E1 E2 F2

Top layer flipped over Bottom layer

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 Tezzaron vertical integration (3D) process

Tezzaron uses a “via middle” approach for the fabrication of 3D chip

Step 1: On all wafer to be stacked complete transistor fabrication, form TSV, passivation and fill TSV at Step 2: Complete back end of same time connections are made to line (BEOL) process by adding Al transistors metal layers and top Cu metal (0.7um)

Step 3: bond wafer 2 to wafer Step 4: thin the wafer 2 to about 1 (Cu-Cu thermo-compression 12um to expose TSV. Add Cu to back bond) of wafer 2 to bond wafer 2 to wafer Step 5: stack wafer 3, thin 3 OR add metallization on back of wafer 3 to expose TSV, add final wafer 2 for bump bonding or wire passivation and metal for bond bonding pads. Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 A case study: Deep N-Well (DNW) CMOS pixel sensors New approach in CMOS MAPS design with the goal of achieving “hybrid pixel-like” functionalities in monolithic devices (pixel-level sparsification and time stamping). SHAPER

PREAMPL DISC LATCH

Classical optimum signal processing chain for capacitive detectors at pixel level: • Charge-to-Voltage conversion done by the charge-sensitive preamplifier • The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 36 Intertrain Readout Architecture for an “ILC-like” MAPS 337 0.95 ms ns Suggested by FNAL IC design group, 0.2 s first implemented in the VIP chip Digital readout Readout x282 CK 0 4 X 4 Y bunch train interval intertrain interval 5 MUX T Serial data output Cell CK 4 5 Time 4 5 Time 4 5 Time X=1 Stamp X=2 Stamp X=1 Stamp 1 Buffer 1 1 Buffer 2 6 1 Buffer 16 5 5 5 Cell (1,1) gXb Cell (1,2) gXb Cell (1,16)gXb gXb=get_X_bus First TS TS TS gYb=get_Y_bus token in Tkin Tkout Tkin Tkout Tkin Tkout TS=Time_Stamp 4 1 gYb gYb gYb Y=1 Tkin=token_in

Cell (2,1) gXb Cell (2,2) gXb Cell (2,16)gXb Tkout=Token_out TS TS TS Tkout Tkin Tkout Tkin Tkout Tkin 4 1 gYb gYb gYb Y=2 The number of elements may be increased without Cell (16,1)gXb Cell (16,2)gXb Cell (16,16)gXb changing the pixel logic Last TS TS TS (just larger X- and Y- token out Tkout Tkin Tkout Tkin Tkout Tkin registers and serializer 4 1 gYb gYb gYb will be required) Y=1 6 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 37 The approach to 3D within the deep N-well sensor concept Guideline: move the digital section to a second layer, at the same time reducing the area of competitive PMOS N-wells in the sensing layer and the size of the pixel

Digital section Digital section Analog section

NMOS P-well N-well

PMOS DNW sensor Analog section DNW sensor

Tier 1: collecting electrode (deep N-well/P-substrate junction), analog front- end and first discriminator stage Tier 2: digital front-end (latches for hit storage, pixel-level digital blocks for sparsification, time stamp registers, kill mask,…) and digital back-end (X and Y registers, time stamp line drivers, serializer,…)

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 38 3D processing and MOSFET radiation hardness

3D processing does not degrade MOSFET behavior after exposure to ionizing radiation. At small drain currents, standard NMOSFETs show a moderate radiation-induced increase of 1/f noise, of a similar magnitude as in standard (2D) 130 nm CMOS. This effect is associated with noisy lateral parasitic transistors, which are turned on by radiation induced positive charge buildup in isolation oxides.

39 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 3D enclosed NMOSFETs

The enclosed layout geometry has been successfully used since the 250 nm node to achieve a large tolerance to very high total doses of ionizing radiation, by removing lateral leakage paths along lateral thick oxides. As expected, this technique works also in 3D-IC 130 nm MOSFETs in the Tezzaron/GlobalFoundries process.

Leakage path G G

S D D S

Standard Enclosed 40 Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 AIDA WP3: 3D interconnection Sub-Projects

1) Bonn/CPPM: Interconnection of the ATLAS FEI4 chips to sensors using bump bonding and TSVs from IZM (large diameter TSV, large interconnection pitch). 2) CERN: Interconnection of MEDIPIX3 chips using the CEA-LETI process 3) INFN/IPHC-IRFU: Interconnection of chips from Tezzaron/Chartered to edgeless sensors and/or CMOS sensors using an advanced interconnection process (T-MICRO or others) 4) LAL/LAPP/LPNHE/MPP: Readout ASICs in 65nm technology interconnected using the CEA-LETI or EMFT process. 5) MPP/GLA/LAL/LIV/LPNHE: Interconnection of ATLAS FEI4 chips to sensors using SLID interconnection and ICV (high density TSVs) from EMFT. 6) Barcelona use a 2-tier approach to increase the fill factor of APD-sensors (based on Tezzaron/Chartered) 7) RAL/UPPSALA Integration of a 2-Tier readout ASIC for a CZT pixel sensor using EMFT SLID technology and TSV, including redistribution of I/O connections to the backside for a 4- side buttable device.

Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013 41 Detection efficiency in 2D and 3D DNW CMOS sensors (simulations) 2D 25x25mm2 pixel 3D 20x20mm2 pixel

Moving most PMOS to the digital layer strongly reduces undetected hits (black dots in the pictures). In the 3D device, the fill factor is larger than 90 % (ratio between the DNW area and the total area of N-wells), which may lead to a detection efficiency close to 99% (see next) Valerio Re – XCIX Congresso Nazionale SIF – Trieste – September 24, 2013