Energy-Efficient Near-Threshold Standard Cell Library for IoT Applications

AbdelRahman Hesham1, Amin Nassar1, and Hassan Mostafa1,2 1Electronics and Communications Engineering Department, Cairo University, Egypt. 2University of Science and technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt. {[email protected], [email protected], [email protected]}

Abstract—In this paper, a low-energy minimum-area CMOS a much better energy/performance trade-off than subthreshold standard cell library suitable for IoT applications is proposed. operation [3]. Energy consumption reduction is achieved by operating the In addition to computation power and energy concerns in library in Near-Threshold Voltage (NTV) region, and by design- ing layout of cells at the minimum possible area for the used IoT applications, the possible threats deriving from widespread technology process. Body biasing technique is proposed to boost adoption of such a technology are stressed. As predicted by pMOS performance. Operating voltage and transistor sizing are Cisco, there will be 50 billion IoT connected devices by 2020 also selected to achieve the minimum energy consumption while [6]. Integration of such a tremendous number of devices into operating at the frequency range of 1MHz to 20MHz which is IoT potentially brings in a new concern, System Security. suitable for IoT applications. The proposed library was designed and characterized in UMC 130 nm CMOS technology process. Thus, cryptography became one of the main approaches to The library was modeled to be used in synthesis tools. To prove secure and overcome attacks on user data. Significant research the benefit for IoT applications, the library was benchmarked by effort was done to provide algorithmic level cryptography implementing 3 cryptographic algorithms: ASCON, AEGIS-128, solutions and to assess hardware implementation of these and AEZ. Synthesis results are showing that the three cores can algorithms. In [7], ASIC implementation of 3 commonly used operate at 18 MHz, 14 MHz, and 16 MHz respectively, while consuming 0.466 pJ, 3.006 pJ, and 5.064 pJ. cryptography algorithms is conducted to check their suitability Index Terms—CMOS digital integrated circuits, design for IoT applications. Similarly, architectural solutions are methodology, near-threshold CMOS circuits, ultra-low power proposed in [8] and used to implement co-processor suitable design, ultra-low energy, IoT, ASCON, AEGIS, AEZ for Narrow-Band (NB) IoT devices. Also, in this direction and in 2012, the European Network of Excellence in Cryptology I.INTRODUCTION (ECRYPT) called for a new competition for authenticated The Internet of Things (IoT) is a novel paradigm that is ciphers: CAESAR (Competition for Authenticated Encryption: rapidly gaining ground in the scenario of modern wireless Security, Applicability, and Robustness) [9]. Review of hard- communication. This is resulting in a wide range of applica- ware implementation of CAESAR algorithms are presented tions touching every aspect of our life, like wearable devices, in [10], [11]. The winning algorithms were announced in connected cars, and smart homes. Enablement of IoT spread 2019, and they were covering 3 main areas of application: is depending on the reliability of devices accessing it. Device lightweight, high performance, and defense-in-depth. In this reliability is based on: (1) computation power, (2) efficiency of paper, 3 of these applications were explored for potential energy consumption, and (3) security against possible threats. benefit in IoT devices. Computation power of IoT devices has been widely ex- In this paper, a low-energy minimum-area standard cell plored in the literature [1]–[5], with a major interest in energy library is proposed in UMC 130 nm process. Library is reduction techniques. These techniques have been explored operating in NTV region at 350 mV supply. This supply was and proposed at all design levels; namely circuit, logic, RTL, selected to achieve the minimum Power Delay Product (PDP) algorithm, and system levels. For IoT devices, most of energy for the used process node. The minimum area is achieved saving is achieved by circuit-level solutions. One of the most by minimizing cell height and by utilizing Euler’s Path in growing topics in this area is the feasibility of voltage scaling design of each cell layout. A calculation method is proposed to reduce energy consumption. Circuit design in subthreshold to get minimum cell height as a function of technology region has gained increasing interest to achieve low power parameters. The Inverse Narrow Width Effect (INWE) was requirements by operating the circuits at the Minimum Energy checked and utilized for library PPA gains. The proposed Point (MEP) [1]. The drawback of this MEP paradigm is the library is showing better energy and area measurements com- significant loss in performance [2]. To recover some of the pared to other libraries surveyed. To show the gains from performance loss while maintaining the power gains, Near- utilizing NTV operation, the library is benchmarked against Threshold Voltage (NTV) operation was introduced [2]. It was a commercial library operating in Super-Threshold Voltage shown that in NTV, energy savings can be in the order of region to implement three of CAESAR finalists: ASCON [12], 10X, with only a 10X degradation in performance, providing AEGIS-128 [13], and AEZ [14]. The rest of the paper is organized as follows. Section II describes the library architecture design and discusses the pro- n = max(Hmin,F EOL,Hmin,BEOL)/Pm2 (4) posed solutions for improving library PPA. Then,comparison result with similar library is presented. Section III describes where n is the minimum cell architecture tracks for a given the flow used for designing the set of cells constructing technology. This equation is technology-independent, and can the library. Section IV reports the benchmark results of the be applied to planar CMOS process nodes. proposed library using cryptography IPs. Lastly, the paper is concluded in Section V.

II.LIBRARY ARCHITECTURE DESIGN In digital design using standard-cell approach, all modules must have the same height [15], [16]. The placement of standard cells has to be aligned with some pre-specified standard-cell rows in the placement region. And because of its popularity, most placement algorithms assume a standard- cell design style. The minimum cell dimensions or in other words the minimum resolution of cell placement in 2D area is defined as Unit Tile. All the cells in standard-cell library have to be of –or multiples of– unit tile height and to have a width that is a multiple of unit tile width. A. Minimum Cell Height Design Here, we are proposing a method to define the minimum cell height for a given process node. All the drawings inside cell must meet the Design Rule Checks (DRC). And given that the shapes drawn inside any cell are from Front-End Of Line (FEOL) layers or Back-End Of Line (BEOL) layers, rules related to both layer groups must be considered. The process parameters needed for FEOL checks are: minimum diffusion enclosure inside NPLUS (ENn), minimum diffusion enclosure inside PPLUS (ENp), minimum diffusion width inside NPLUS (Wn), and minimum diffusion width inside PPLUS (Wp). From Fig. 1, the minimum cell height Fig. 1. Technology FEOL parameters to calculate minimum tracks. (Hmin,FEOL) is calculated as:

Hmin,F EOL = 2ENp + 2ENp + Wn + Wp (1) For UMC 130nm process, and based on the process Design Rule Manual (DRM), the minimum cell height tracks is calcu- Then, to calculate H from BEOL rules, we need to construct min lated to be 5T. This is the minimum number of tracks reported the layout given in Fig. 2. The limitation here is coming from in the literature. In [17], a 6T architecture is developed, in the first metal layer (metal 1). (1) Any metal 1 shape must [18]–[21] 8T–12T architectures are developed by utilizing keep a spacing distance of S to other metal 1 shapes, (2) m1 multi-finger structure to achieve more area efficiency. any via connecting metal 1 to poly shape or diffusion shape (CONT) must be enclosed by metal 1 shape, and finally (3) PG B. Cell Layout Design rails needs to be drawn on metal 1 to provide supply voltage to transistors. The minimum PG rail width is the minimum Implementation of 5T architecture is enabled by: using metal 1 width (Wm1). So: Euler’s path theory for layout design, and using 3 metal layers for intra-cell routing. Hmin,BEOL = 4Sm1 + 3CEm1 + Wm1 (2) Euler’s path theory [22]–[24] is used in [25] to provide In order to avoid any routing problem, either internally to the minimum-area transistor placement inside given cell area. connect transistors, or externally when the cell gets connected The resulting transistor placement can be routed in multiple to other cells, cell height must be integer multiples of the pitch ways. The selected routing of each cell used in our library of the first horizontal metal layer -metal 2 in our proposed considers: (1) pin accessibility when used in Placement and Routing tools, (2) minimizing pin capacitance, and (3) meeting library- (Pm2). technology DRC rules. Three metal layers are used for intra- cell routing. Metal 1 and metal 2 are used extensively, while Hmin = nPm2 (3) metal 3 is rarely used when all metal 1 and metal 2 resources And from Equations (1), (2), (3), we can define: are used. Fig. 3. NMOS threshold voltage vs transistor width at different supply Fig. 2. Technology BEOL parameters to calculate minimum tracks. voltages in 130 nm.

C. Transistor Sizing Transistor sizing is one of the main factors deciding the li- brary power and speed performance. The used 5T architecture sets a limit on the maximum transistor sizing:

Wn + Wp ≤ 5Pm2 − 2ENp − 2ENn (5) For the used process, this limit is calculated to be 1.04 µM. This value is allowing transistor sizing in the range around and beyond minimum pMOS and nMOS widths. Literature was explored for the different transistor sizing techniques in NTV region in order to improve performance with the minimum impact on power. The Inverse-Narrow- Width Effect (INWE) was introduced in [26] as the reduction in the threshold voltage due to reduction in transistor width, allowing for higher driving currents. INWE can be utilized to achieve performance gain while operating in the NTV. [18] has used the minimum pMOS and nMOS finger widths to maximize INWE while having the minimum threshold voltage. [18] has shown the INWE in 90 nm, 65 nm, and 45 nm Fig. 4. PMOS absolute threshold voltage vs transistor width at different process nodes. In Fig. 3 and Fig. 4, the INWE impact in 130 supply voltages in 130 nm. nm process node is shown, which aligns with the previously introduced results for NMOS. For PMOS, the INWE is not significant. As shown in Fig. 4, a slight reduction in threshold increasing PMOS size, body biasing technique is used. The voltage near the minimum width is noticed while reducing conventional body-biasing used in digital circuits is done supply voltage. So, sizing PMOS at minimum width is not by connecting n-well to the supply voltage and connecting as important as NMOS. This was also shown for 180 nm in p-substrate to the ground. This technique is cancelling the [27]. Also, from Fig. 4, Wp needs to be >350 nm to avoid body effect, hence, the dependence of threshold voltage on the threshold voltage curve peak, but increasing it too much the body voltage is not noticed. This technique is used in will not improve performance due to increase in fanout load. superthreshold region, and can be used also for NTV region [28]. In [29] the low-voltage swapped body biasing (LVSB) D. pMOS Body Biasing Technique was used in 180 nm at 0.5 V, where the n-well and p-substrate In order to balance the NMOS and PMOS currents and voltages are swapped compared to the conventional biasing. to reduce the difference between rise and fall times without The technique used in [28] is compromising between the con- ventional technique and the LVSB one. In this technique, the body terminals of all nMOS and pMOS devices are connected together without supply or ground connections. The proposed technique in this paper is to connect only pMOS body to the ground. With this way, the forward body biasing provides significant performance gain for the pull-up network, while keeping the pull-down one at the same power consumption. E. Testing and Supply Selection

Inverter INV X1 was created with Wn set to 160 nm, the minimum width available, and with pMOS body terminal connected to ground. A Fanout-of-4 (FO4) test-bench for the inverter cell was created to simulate the impact of transistor sizing and body biasing on delay, power, and PDP. Fig. 5 and Fig. 6 are showing that, the proposed body biasing is providing better performance with slight increase in power in the subthreshold and nearthreshold regions when compared to conventional biasing. This is not the case as the supply voltage Fig. 6. Inverter PDP vs the supply voltage. increases, where power starts to grow faster. Supply voltage is selected to be 350 mV, where the performance gain is achieved TABLE I at the cost of power increase while achieving the same PDP POWER,DELAY, AND PDP COMPARISONBETWEENPROPOSED 5T LIBRARY AND SIMILAR 6T LIBRARY as of the conventional body biasing. This supply voltage is selected at the center of flat range in PDP curve to allow for Library Delay, ns Power, nW PDP, fJ PVT margins while having the same value. cell Proposed Lib1a Proposed Lib1 Proposed Lib1 INV X1 3.59 0.96 0.117 - 0.000421 1.432 ND2 X1 3.99 1.24 0.127 - 0.000506 1.605 NR2 X1 3.6 1.2 0.215 - 0.000754 1.522 a 6T NTV library implemented in 130 nm [17].

and sequential cells (e.g. D-Flipflop and D-Latch). The flow used is shown in Fig. 7. For each cell, static CMOS imple- mentation is selected, which is needed to provide Rail-to- Rail swing with the low supply used. Then, a test-bench is created to check circuit functionality and to measure its timing and power parameters. Once passed, design is transformed into its layout implementation. Qualified layout needs to pass essential physical verification checks, namely DRC and LVS. Then, design functionality and specifications are rechecked to avoid any corruption due to layout design. SPICE model describing our cell is then generated. This model is passed to cell characterization and modeling flow, which creates the Fig. 5. Inverter power and delay vs the supply voltage. library model needed for synthesis tools. The generated model includes all cell delay information, in addition to cell power F. Literature Comparison performance. This view is essential input to logic synthesis process. Proposed library model was generated using Synopsys In this section, comparison with other work is provided. In Siliconsmart tool. The tool takes cell SPICE model as input, Table I, comparison is done with a 6T NVT library designed and based on user configuration, it generates the cell model in 130 nm operating at 400 mV. Comparison is held for the in .LIB format. nominal corner: TT, nominal supply, and room temperature of 25◦C. Although our proposed library is lagging in delay by IV. LIBRARY BENCHMARKING about 3X, it is achieving better PDP by about 2000X. In this section, comparison results are provided to show III.CELL DESIGN FLOW the power and performance gains of proposed library. Table The list of cells included in proposed library are covering II is showing the ratio of frequency lost by moving from the basic functions to build any design; namely combinational superthreshold to subthreshold region. In Table III, power cells (e.g. INV, AND, OR, NAND, NOR, XOR, and XNOR) and frequency were explored considering process, voltage, AEZ is another algorithm that was one of the finalists in the same competition. Assessment of the library was done by comparing synthesis results of the three designs using the proposed Near-Threshold library compared to using a commercial library operating in Super-Threshold region at the same technology node. The used RTL implementations are the ones used for CAESAR candidates benchmarking [31].

TABLE II MAXIMUM FREQUENCY COMPARISON WITH FOUNDRY COMMERCIAL LIBRARY

Max Frequency, MHz Ratio of Tested Proposed Commercial Frequency Core Library Library Loss ASCON 18 330 18.33 AEGIS-128 14 100 7.14 AEZ 16 125 7.81

TABLE III LIBRARY POWERAND FREQUENCY ACROSS PVTCORNERS

Internal Switching Leakage Total Max Corner (nW) (nW) (nW) (nW) Freq TT0p35v25c 62.547 2.1999 6.1509 70.896 16 SS0p315vm40c 2.07 0.079 61.5 2.22 1 SS0p315v125c 4.13 0.165 19.0 23.7 5 FF0p385vm40c 295 9.86 2.29 307.0 52 FF0p385v125c 383.1 12.0 808 1203 67

V. CONCLUSION The proposed Near-Threshold standard cell library is show- ing significant energy saving when used in essential applica- tions in IoT. This energy saving comes at the cost of frequency reduction. The paper has provided solutions to find opti- mal Power-Performance-Area operating point. A technology- dependent methodology is proposed for minimum standard cell layout architecture design. INWE was utilized in addition to a proposed body biasing technique that boosts performance in NVT. Three of the latest and best cryptographic cores are considered in this paper for benchmarking the proposed library. Quality of improvement can be measured as the ratio of energy improvement and frequency reduction. ASCON archives a ratio of 1.7, while AEGIS-128 achieves a ratio of Fig. 7. The Used Cell Design Flow. 2.5, and finally AEZ achieves a ratio of 4.1. Still, the achieved frequencies are sufficient for IoT applications. and temperature (PVT) variations. A 10% supply variation VI.ACKNOWLEDGMENT is considered. The worst performance corner found to be This work was partially funded by ONE Lab at Zewail City SS0p315vm40c with about 16X reduction from nominal of Science and Technology and at Cairo University, NTRA, one. The worst power consumption corner is found to be ITIDA, ASRT, and NSERC. FF0p385v125c with about 10X increase compared to nominal REFERENCES one. [1] A. Wang, and A. Chandrakasan, “A 180-mV Subthreshold FFT Proces- Finally, in Table IV, implementation of cryptographic cores sor Using a Minimum Energy Design Methodology,” IEEE JOURNAL is done. In the final portfolio of the CAESAR competition [30], OF SOLID-STATE CIRCUITS, vol. 40, pp. 310–319, January 2005. ASCON was selected as the primary choice for lightweight [2] B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw, “Energy- authenticated encryption, and AEGIS-128 was selected as the Efficient Subthreshold Processor Design,” IEEE Trans. On VLSI Sys- primary choice for high performance authenticated encryption. tems, vol. 17, no. 8, pp. 1127–1137, Aug. 2009. TABLE IV POWERAND ENERGY COMPARISON AT TYPICAL CORNERBETWEENPROPOSED LIBRARY AND FOUNDRY LIBRARY

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