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United States Patent (19) 11 Patent Number: 5,130,269 Kitahara Et Al

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United States Patent (19) 11 Patent Number: 5,130,269 Kitahara Et Al USOO5130269A United States Patent (19) 11 Patent Number: 5,130,269 Kitahara et al. 45 Date of Patent: Jul. 14, 1992 54. HETERO-EPITAXIALLY GROWN 0214610 3/1987 European Pat. Off. COMPOUND SEMCONDUCTOR 00641 18 4/1986 Japan ................................... 437/132 SUBSTRATE AND A METHOD OF 000.224 1/1987 Japan ... ... 437/32 0001225 l/1987 Japan ................................... 437/132 GROWNG THE SAME 62-291909 12/1987 Japan. 75) Inventors: Kuninori Kitahara, Zama; Nobuyuki 0228714 9/1988 Japan. Ohtsuka, Atsugi; Masashi Ozeki, 02898.12 l/1988 Japan ................................... 437/132 Yokohama, all of Japan OTHER PUBLICATIONS 73 Assignee: Fujitsu Limited, Kanagawa, Japan Applied Physics Letters; vol. 48, No. 16, 21 Apr. 1986, 21 Appl. No.: 342,785 pp. 1083-1084, New York, USA; B. F. Levine et al.; "Long Wavelength GaSb Photoconductive Detectors 22 Filed: Apr. 25, 1989 Grown on Si Substrates'. 30 Foreign Application Priority Data Journal of Vacuum Science and Technology; vol. 5, No. 4, Jul/Aug. 1987, pp. 1184-1186, New York, USA; Apr. 27, 1988 JP Japan ................................ 631OSO36 M. Ozeki et al.; "Kinetic Processes in Atomic-Layer Oct. 20, 1988 JP Japan ................................ 63-26468 Epitaxy of GaAs and AlAs Using a Pulsed Vapor 51 int. Cl. ............................................. H01. 21/20 Phase Method'. 52 U.S. C. .................................... 437/111; 437/132; Vernon et al., "Metalorganic Chemical Vapor Deposi 437/133; 437/976 tion of GaAs on Si... ', J. Crys. Growth, vol. 77, 1986, 58 Field of Search ................... 148/DIG. 17, 56, 65, pp. 530-538. 148/72,97, 110, 149, 169,33, 33.1, 33.4; Mendez et al., "... InAs/AlAs Strained-Layer Super 156/610-614; 427/248.1, 255.1; 437/81, 84, lattices ... ', Appl. Phys, A48, 1989, pp. 471-473. 105, 107, 108, 110, 111, 126, 129, 132,936, 939, Sugo et al., "Buffer Layer Effects on Residual Stress in 946, 945, 976 InP on Si Substrates," Appl. Phys. Lett., 54(18), 1 May (56) References Cited 1989, pp. 1754-1756. Shinohara, ". AlAs-GaAs Superlattice Buffer Lay U.S. PATENT DOCUMENTS ers," Appl. Phys. Lett., 52(7), 15 Feb. 1988, pp. 4,058,430 1 1/1977 Suntola et al. ...................... 156/611 543-545. 4,180,825 12/1979 Mason ................................. 437/126 4,588,451 5/1986 Vernon ............................... 437/126 Primary Examiner-Olik Chaudhuri 4,767,494 8/1988 Kobayashi et al. ................. 437/110 Assistant Examiner-David E. Graybill 4,806,996 2/1989 Luryi..................................... 437/84 Attorney, Agent, or Firm-Armstrong & Kubovcik 4,829,022 5/1989 Kobayashi et al. ................. 437/110 4,833,103 5/1989 Agostinelli et al. w 57 ABSTRACT 4,835,116 4/1989 Lee et al. ...... A method of growing a gallium arsenide single crystal 4,840,92 6/1989 Matsumoto ... 437/132 4,843,029 6/1989 Joyce et al. ......................... 437/126 layer on a silicon substrate comprises steps of growing 4,859,627 8/1989 Sunakawa ........................... 437/126 a buffer layer of aluminum arsenide on the silicon sub 4,933,300 6/1990 Koinuma et al. ................... 437/10 strate by atomic layer epitaxy, and growing the gallium 4,963,508 10/1990 Umeno et al. ...................... 437/976 arsenide single crystal layer on the buffer layer epitaxi ally. FOREIGN PATENT DOCUMENTS 02072.16 1/1987 European Pat. Off. 4 Claims, 7 Drawing Sheets FOW RAE GoAs GROWTH (MOCVO) TIME U.S. Patent July 14, 1992 Sheet 1 of 7 5,130,269 C EVACUATION 27C TMA As H3 H2 2. TMG + H2 H2 Y-A-------|-A-N CONTROL I-28 EXHAUST FIG.1 U.S. Patent July 14, 1992 Sheet 2 of 7 5,130,269 PHASE I TEMPERATURE 1000 PHASE I PHASE II c : 2O 40 60 8O 18O TIME(MINUTES) FLOW RATE A. As GROWTH GOAS GROWTH (MOCVD) H2 HH HH %: TMA N: TMG TMA OR TMG N TIME FIG.3 al U.S. Patent July 14, 1992 Sheet 3 of 7 5,130,269 pupsýD9SvøyISuo *| OglºV uæquunNsuÐKolouou?o 37*9)I- All Sueul SV-1S pezil DuoN U.S. Patent July 14, 1992 Sheet 4 of 7 5,130,269 swooISuo d???ngS\/D9–ETV J???ngsvøy-ETV7 018: A Sueu U.S. Patent July 14, 1992 Sheet 7 of 7 5,130,269 5,130,269 1. 2 difficult to achieve with reliability in the presently HETERO-EPTAXALLY GROWN COMPOUND available technique. SEMICONDUCTORSUBSTRATE AND AMETHOD Alternatively, it is proposed to interpose a polycrys OF GROWING THE SAME talline gallium arsenide buffer layer between the silicon substrate and the gallium arsenide layer to absorb the BACKGROUND OF THE INVENTION mismatching of the lattice constant and thermal expan The present invention generally relates to fabrication sion. In this approach, a thin gallium arsenide polycrys of semiconductor devices and more particularly to an talline buffer layer having a thickness of typically 10 nm epitaxial growth of a compound semiconductor layer is deposited on the silicon substrate at a temperature of such as gallium arsenide on a silicon wafer. 10 about 400-450 C. prior to deposition of the single Gallium arsenide (GaAs) is a typical compound semi crystal gallium arsenide substrate layer. Then, the ten conductor material used for laser diodes and various perature is raised to about 600-750 C. and the gallium fast speed semiconductor devices such as metal-semi arsenide substrate layer is deposited for a thickness of conductor field effect transistor (MESFET), high elec about a few microns. When the temperature is raised tron mobility transistor (HEMT), heterojunction bipo 15 from the first temperature to the second temperature, lar transistor (HBT) and the like because of its charac the polycrystalline gallium arsenide buffer layer is re teristic band structure and high electron mobility. Such crystalized into single crystal and the gallium arsenide a semiconductor device is constructed on a gallium substrate layer deposited thereon grows while maintain arsenide wafer sliced from a gallium arsenide ingot ing epitaxial relation with the gallium arsenide buffer grown as a single crystal or on a gallium arsenide sub 20 layer underneath. strate grown epitaxially on a surface of a silicon wafer. In this technique, however, it is difficult to obtain a In the latter construction, one can avoid the difficulty of satisfactorily flat surface for the single crystal gallium handling heavy and brittle gallium arsenide wafer dur arsenide layer. This is because the polycrystalline gal ing the fabrication process of the device by using a light lium arsenide buffer layer takes an island structure on and strong silicon wafer fabricated by a well established 25 the surface of the silicon wafer and the non-flat mor process for the base of the substrate. Further, one can phology of the surface of the polycrystalline gallium easily obtain a large diameter wafer in such a construc arsenide buffer layer is transferred to the gallium arse tion. As a result, one can handle the wafer easily and reduce the manufacturing cost of the device. Further, nide substrate layer provided thereon. In other words, such a wafer is suited for fabrication of a so called opto 30 the the surface of the gallium arsenide substrate layer electronic integrated circuit (OEIC) devices wherein becomes waved in correspondence to the island struc gallium arsenide laser diode and the like are assembled ture of the buffer layer. In spite of the use of reduced together with silicon transistors on a common semicon temperature at the time of formation of the buffer layer ductor chip. so as to suppress the formation of the island structure by When growing gallium arsenide on silicon wafer 35 reducing the growth rate, the island structure cannot be epitaxially, however, one encounters various difficul eliminated satisfactorily. Further, such a waved surface ties. Such difficulties are caused mainly due to large of the gallium arsenide substrate cannot be eliminated difference in the lattice constant and thermal expansion even if the thickness of the gallium arsenide layer is between silicon and gallium arsenide. For example, the increased to a few microns or more. lattice constant of silicon is smaller than that of gallium Further, it is proposed to use other material such as arsenide by about 4% and the thermal expansion coeffi silicon-germanium solid solution SiyGety for the buffer cient of silicon is smaller than that of gallium arsenide layer while changing the composition y continuously by about 230%. From simple calculation based on the from the surface of the silicon substrate to the bottom of difference in the lattice constant, it is predicted that the the gallium arsenide substrate layer as is described in the gallium arsenide substrate constructed as such contains 45 Japanese Laid-open Patent Application No. 62-87490. dislocations with a density in the order of 1012/cm2. Alternatively, it is proposed to use a gallium arsenide Thus epitaxial growth of gallium arsenide layer made based mixed crystal such as InGaAs or AlxGa1-xAs directly on silicon substrate is usually unsuccessful. with a composition x of about 4.5x103 for the buffer Even if successful, such a layer involves significant layer (Japanese Laid-open Patent Application No. defects such that they cannot be used as the substrate 50 62-291909). In both of these alternatives, there is a prob for a semiconductor device. lem in the surface morphology as already described. In order to eliminate these problems and obtain a On the other hand, the applicants made a discovery gallium arsenide substrate layer having a quality satis during a series of experiments to deposit a group III-V factory for a substrate of semiconductor device, it is compound such as aluminium arsenide (AlAs) on a proposed to interpose a buffer layer between the silicon 55 gallium arsenide substrate by atomic layer epitaxy wafer and the gallium arsenide substrate so as to absorb (ALE) that aluminium deposited on an arsenic plane of any stress caused as a result of mismatch in the lattice the gallium arsenide substrate rapidly covers the surface constant and thermal expansion between the wafer and of the substrate with a surface density corresponding to the substrate.
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