Enhancement-/Depletion-PHEMT Device and Manufacturing Method

(19) TZZ _T

(11) EP 2 555 242 B1

(12) EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention (51) Int Cl.: of the grant of the patent: H01L 27/088 (2006.01) H01L 27/06 (2006.01) 23.07.2014 Bulletin 2014/30 H01L 21/8252 (2006.01)

(21) Application number: 12178617.2

(22) Date of filing: 31.07.2012

(54) Enhancement-/depletion-PHEMT device and manufacturing method thereof Verstärkungs-/Verarmungs-PHEMT-Vorrichtung und Herstellungsverfahren dafür Dispositif PHEMT à enrichissement et appauvrissement et procédé pour sa fabrication

(84) Designated Contracting States: (56) References cited: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB EP-A1- 0 371 686 WO-A2-2006/083587 GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO JP-A- 63 222 462 JP-A- 2009 032 729 PL PT RO RS SE SI SK SM TR US-A1- 2006 208 279 US-A1- 2008 251 837 US-A1- 2010 001 318 US-A1- 2011 049 526 (30) Priority: 01.08.2011 IT TO20110713 • HURM V ET AL: "10 Gbit/s monolithic integrated (43) Date of publication of application: optoelectronic receiver using an MSM 06.02.2013 Bulletin 2013/06 photodiode and AlGaAs/GaAs HEMTs", MICROELECTRONIC ENGINEERING, ELSEVIER (73) Proprietor: SELEX ES S.p.A. PUBLISHERS BV., AMSTERDAM, NL, vol. 15, no. 00131 Roma (IT) 1-4, 1 October 1991 (1991-10-01), pages 275-278, XP024484431, ISSN: 0167-9317, DOI: (72) Inventors: 10.1016/0167-9317(91)90228-6 [retrieved on • Chini, Alessandro 1991-10-01] 00131 ROMA (IT) • HSIEN-CHIN CHIU ET AL: "High uniformity • Lanzieri, Claudio enhancementand depletion- modeInGaP/ InGaAs 00131 ROMA (IT) pHEMTs using a selective succinic acid gate recess process; High uniformity enhancement (74) Representative: Bergadano, Mirko et al and depletion-mode InGaP/InGaAs pHEMTs", Studio Torta S.p.A. SEMICONDUCTOR SCIENCE AND Via Viotti, 9 TECHNOLOGY, IOP PUBLISHING LTD, GB, vol. 10121 Torino (IT) 21, no. 1, 1 January 2006 (2006-01-01), pages 55-59, XP020098204, ISSN: 0268-1242, DOI: 10.1088/0268-1242/21/1/010

Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). EP 2 555 242 B1

Printed by Jouve, 75001 PARIS (FR) 1 EP 2 555 242 B1 2

Description [0008] Therefore, the object of the present invention is that of providing an enhancement/depletion PHEMT de- TECHNICAL FIELD OF THE INVENTION vice and a method of manufacturing an enhancement/de- pletion PHEMT device. [0001] The present invention relates, in general, to en- 5 [0009] This object is achieved by the present invention hancement/depletion Pseudomorphic High Electron Mo- in that the latter relates to a layered epitaxial structure bility Transistors (PHEMTs) and, in particular, to an en- for enhancement/depletion PHEMT devices, to an en- hancement/depletion PHEMT device and a method for hancement/depletion PHEMT device and to a method manufacturing enhancement/depletion PHEMT devices for manufacturing an enhancement/depletion PHEMT that finds advantageous, but not exclusive, application 10 device, according to that defined in the appended claims. in the production of integrated circuits operating at milli- [0010] In particular, the layered epitaxial structure for metre-wave and microwave frequencies. PHEMT devices comprises:

STATE OF THE ART • a superlattice and buffer layer; 15 • an undoped back-barrier layer formed on the super- [0002] As is known, Pseudomorphic High Electron Mo- lattice and buffer layer and made of aluminium gal- bility Transistors (PHEMTs) are widely used in integrated lium arsenide (AlGaAs); circuits operating at millimetre-wave and microwave fre- • a doped back delta doping layer formed on the back- quencies, such as the so-called Monolithic Microwave barrier layer; Integrated Circuits (MMICs). 20 • an undoped back-spacer layer formed on the back [0003] In particular, PHEMTs are widely exploited in delta doping layer and made of aluminium gallium various types of system, such as radio communication arsenide (AlGaAs); systems and radar systems. • an undoped channel layer formed on the back-spac- [0004] In detail, PHEMTs have found wide utilization er layer and made of indium gallium arsenide (In- over the years because they provide high Radio Frequen- 25 GaAs); cy gain (RF gain), high Power Added Efficiency (PAE) • an undoped spacer layer formed on the channel lay- and a low Noise Figure (NF). er and made of aluminium gallium arsenide (Al- GaAs); OBJECT AND SUMMARY OF THE INVENTION • a delta doping layer formed on the spacer layer; 30 • an undoped enhancement barrier layer formed on [0005] The applicant, in consideration of the excellent the delta doping layer; properties of PHEMTs that, as previously mentioned, • a doped first etch stopper layer formed on the en- have given rise to extensive usage thereof in various hancement barrier layer and made of aluminium ar- types of systems over the years, has carried out an in- senide (AlAs); depth study on currently-known enhancement/depletion 35 • a doped first depletion barrier layer formed on the PHEMT devices. first etch stopper layer; [0006] In particular, the applicant has carried out an • an undoped second depletion barrier layer formed exhaustive analysis regarding the characteristics of the on the first depletion barrier layer; enhancement/depletion PHEMT devices described in • a doped second etch stopper layer formed on the United States patent applications US 2006/0027840 and 40 second depletion barrier layer and made of alumin- US 2006/0208279, in European patent application EP ium arsenide (AlAs); 0371686 and in United States patents US 6,670,652, US • a first cap layer doped with n-type doping, formed 6,703,638 and US 7,361,536. onthe second etch stopperlayer and made of gallium [0007] On the basis of the results of said analysis, the arsenide (GaAs); applicant felt, thence, the need to develop: 45 • an undoped second cap layer formed on the first cap layer and made of gallium arsenide (GaAs); • an innovative enhancement/depletion PHEMT de- • a third etch stopper layer doped with n-type doping, vice having superior properties than currently known formed on the second cap layer and made of alu- enhancement/depletion PHEMT devices, in particu- minium arsenide (AlAs); and lar the enhancement/depletion PHEMT devices de- 50 • an ohmic layer doped with n-type doping, formed on scribed in United States patent applications US the third etch stopper layer and made of gallium ar- 2006/0027840 and US 2006/0208279, in European senide (GaAs). patent application EP 0371686 and in United States patents US 6,670,652, US 6,703,638 and US [0011] Furthermore, the enhancement/depletion 7,361,536; and 55 PHEMT device according to the present invention com- • an innovative method for manufacturing enhance- prises: ment/depletion PHEMT devices. • the above-stated layered epitaxial structure;

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• a first region comprising surface of the second depletion barrier layer de- fining the second Schottky contact region and - a first recess vertically formed through the ohmic extending vertically from said second Schottky layer and the third etch stopper layer so as to contact region through the fifth and fourth re- expose a first upper surface of the second cap 5 cesses so as to protrude from said fourth recess. layer, - a second recess that is narrower than the first BRIEF DESCRIPTION OF THE DRAWINGS recess and which vertically extends from the first recess through the second cap layer, the first [0012] For a better understanding of the present inven- cap layer and the second etch stopper layer so 10 tion, some preferred embodiments, provided by way of as to expose a first upper surface of the second non-limitative example, will now be illustrated with refer- depletion barrier layer, and ence to the attached drawings (not to scale), where: - a third recess that is narrower than the second recess and which vertically extends from the • Figures 1-6 are schematic section views that illus- second recess through the second depletion 15 trate successive manufacturing steps of a first en- barrier layer, the first depletion barrier layer and hancement/depletion PHEMT device according to a the first etch stopper layer so as to expose an first preferred embodiment of the present invention; upper surface of the enhancement barrier layer and defining a first Schottky contact region; • Figures 7 and 8 are schematic section views of a 20 second enhancement/depletion PHEMT device ac- • a second region laterally spaced apart, and electri- cording to a second preferred embodiment of the cally insulated, from said first region and comprising present invention.

- a fourth recess vertically formed through the DETAILED DESCRIPTION OF PREFERRED EMBOD- ohmic layer and the third etch stopper layer so 25 IMENTS OF THE INVENTION as to expose a second upper surface of the sec- ond cap layer, and [0013] The present invention will now be described in - a fifth recess that is narrower than the fourth detail with reference to the attached Figures to enable recess and which vertically extends from the an expert in the field to embody it and use it. Various fourth recess through the second cap layer, the 30 modifications to the described embodiments will be im- first cap layer and the second etch stopper layer mediately obvious to experts in the field, and the generic so as to expose a second upper surface of the principles described herein can be applied to other em- second depletion barrier layer defining a second bodiments and applications without leaving the scope of Schottky contact region; protection of the present invention, as defined in the ap- 35 pended claims. Therefore, the present invention should • an enhancement transistor formed in first region and not be considered as limited to the embodiments de- comprising scribed and illustrated herein, but be conceded the broadest scope of protection consistent with the princi- - first source and drain electrodes formed on, and ples and characteristics described and claimed herein. in ohmic contact with, said ohmic layer in the40 [0014] Figures 1-6 are schematic section views that first region externally to the first recess, and illustrate successive manufacturing steps of a first en- - a first gate electrode formed in the third recess hancement/depletion PHEMT device according to a first in Schottky contact with the upper surface of the preferred embodiment of the present invention, said first enhancement barrier layer defining the first enhancement/depletion PHEMT device being indicated Schottky contact region and extending vertically 45 as a whole in said Figures 1-6 by reference numeral 1. from said first Schottky contact region through [0015] In particular, with reference to Figure 1, the first the third, second and first recesses so as to pro- enhancement/depletion PHEMT device 1 comprises a trude from said first recess; and layered epitaxial structure that includes:

• a depletion transistor formed in second region and 50 • a superlattice and buffer layer 11, the function of comprising which mainly lies in enabling the growth of the lay- ered epitaxial structure described herein and shown - second source and drain electrodes formed on, in Figure 1 on semi-insulating gallium arsenide and in ohmic contact with, said ohmic layer in (GaAs) substrates, ensuring effective confinement thesecond region externally to the fourth recess, 55 of electrons in a channel made of indium gallium ar- and senide (InGaAs) (said InGaAs channel being indi- - a second gate electrode formed in the fifth re- cated in Figure 1 by reference numeral 15 and de- cess in Schottky contact with the second upper scribed in detail below) and avoiding the formation

3 5 EP 2 555 242 B1 6

of undesired conductive channels in the layers be- preferably having a doping level greater than 0 and neath the indium gallium arsenide (InGaAs) channel; less than or equal to 6e18, and a thickness within the one possible embodiment of said superlattice and range of 1.5-2.5 nm; buffer layer 11, which in any case envisages multiple • a doped first depletion barrier layer 20, formed on alternative solutions, is that of alternating undoped 5 the first etch stopper layer 19 and made of gallium layers of aluminium arsenide (AlAs) and gallium ar- arsenide (GaAs) (or aluminium gallium arsenide (Al- senide (GaAs) with thicknesses of around a few tens GaAs), preferably with a weight concentration of alu- of nanometres (nm), repeating the growth of these minium (Al) within the range of 18%-28%), said first layers roughly ten times; however, it is still possible depletion barrier layer 20 preferably having a thick- to also make use of solutions that use layers of alu- 10 ness within the range of 10-30 nm and a doping level minium gallium arsenide (AlGaAs) instead of the lay- greater than 0 and less than or equal to 6e18; ers of aluminium arsenide (AlAS) or, in any case, • an undoped second depletion barrier layer 21, other epitaxial solutions used to eliminate the forma- formed on the first depletion barrier layer 20 and tion of parasitic electrically conductive channels; made of gallium arsenide (GaAs) (or aluminium gal- • an undoped back-barrier layer 12, formed on the su- 15 lium arsenide (AlGaAs), preferably with a weight perlattice and buffer layer 11 and made of aluminium concentration of aluminium (Al) within the range of gallium arsenide (AlGaAs), said back-barrier layer 18%-28%), said second depletion barrier layer 21 12 preferably having a weight concentration of alu- preferably having a thickness greater than 0 nm and minium (Al) within the range of 18%-28% and a thick- less than or equal to 10 nm; ness greater than 0 nm and less than or equal to 50 20 • a doped second etch stopper layer 22, formed on nm; the second depletion barrier layer 21 and made of • a doped back delta doping layer 13, formed on the aluminium arsenide (AlAs), said second etch stopper back-barrier layer 12, said back delta doping layer layer 22 preferably having a doping level greater than 13 having a doping level greater than 0 and less than 0 and less than or equal to6e 18 and a thickness or equal to 4e12; 25 within the range of 1.5-2.5 nm; • an undoped back-spacer layer 14, formed on the • a first cap layer 23 doped with n-type doping, formed back delta doping layer 13 and made of aluminium on the second etch stopper layer 22 and made of gallium arsenide (AlGaAs), said back-spacer layer gallium arsenide (GaAs), said first cap layer 23 pref- 14 preferably having a weight concentration of alu- erably having a doping level within the range of 1e17- minium (Al) within the range of 18%-28% and a thick- 30 6e17 and a thickness within the range of 20-50 nm; ness within the range of 3-10 nm; • an undoped second cap layer 24 formed on the first • an undoped channel layer 15, formed on the back- cap layer 23, said second cap layer 24 preferably spacer layer 14 and made of indium gallium arsenide having a thickness greater than 0 nm and less than (InGaAs), said channel layer 15 preferably having a or equal to 10 nm; weight concentration of indium (In) within the range 35 • a third etch stopper layer 25 doped with n-type dop- of 15%-25% and a thickness within the range of ing, formed on the second cap layer 24 and made 10-20 nm; of aluminium arsenide (AlAs), said third etch stopper • an undoped spacer layer 16, formed on the channel layer 25 preferably having a doping level within the layer 15 and made of aluminium gallium arsenide range of 1e18-6e18 and a thickness within the range (AlGaAs), said spacer layer 16 preferably having a 40 of 1.5-2.5 nm; and weight concentration of aluminium (Al) within the • an ohmic layer 26 doped with n-type doping, formed range of 18%-28% and a thickness within the range onthe thirdetch stopper layer 25 and made ofgallium of 3-10 nm; arsenide (GaAs), said ohmic layer 26 preferably hav- • a delta doping layer 17 formed on the spacer layer ing a doping level within the range of 1e18-6e18 and 16; in particular, said delta doping layer 17 can be 45 a thickness within the range of 30-70 nm. undoped or doped with a doping level greater than 0 and less than or equal to 4e12; [0016] Again with reference to Figure 1, the first en- • an undoped enhancement barrier layer 18, formed hancement/depletion PHEMT device 1 also comprises: on the delta doping layer 17 and made of gallium arsenide (GaAs) (or aluminium gallium arsenide (Al- 50 • a first region 27 in which an enhancement transistor GaAs), preferably with a weight concentration of alu- is manufactured, as will be described in detail below; minium (Al) within the range of 18%-28%), said en- • a second region 28 that is laterally spaced apart from hancement barrier layer 18 preferably having a thick- the first region 27 and in which a depletion transistor ness greater than 0 nm and less than or equal to 30 is manufactured, as will be described in detail below; nm; 55 • a first pair of electrodes 29 comprising a first source • a doped first etch stopper layer 19, formed on the electrode and a first drain electrode arranged in the enhancement barrier layer 18 and made of alumin- first region 27; said first source electrode being ium arsenide (AlAs), said first etch stopper layer 19 formed on, and in ohmic contact with, a first portion

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of the ohmic layer 26 extending in the first region 27 layer 26. The ion implantation is then carried out so as and defining a first ohmic contact region; said first to implant ions through the two openings of the second drain electrode being formed on, and in ohmic con- mask and into the fifth and sixth portions of the ohmic tact with, a second portion of the ohmic layer 26 ex- layer 26 and also into the corresponding underlying por- tending in the first region 27 and defining a second 5 tions of all layers of the layered epitaxial structure, i.e. ohmic contact region laterally spaced apart from the up to the superlattice and buffer layer 11. first ohmic contact region, in particular preferably set [0022] With reference to Figure 2, after having electri- apart at a distance within the range of 3-6 mm; and cally insulated the first region 27 and the second region • a second pair of electrodes 30 comprising a second 28 of the enhancement/depletion PHEMT device 1, a first source electrode and a second drain electrode ar- 10 recess 33 and a second recess 34 are formed in said ranged in the second region 28; said second source first region 27 and in said second region 28, respectively. electrode being formed on, and in ohmic contact [0023] In particular, said first recess 33 is formed with, a third portion of the ohmic layer 26 extending through a seventh portion of the ohmic layer 26 extending in the second region 28 and defining a third ohmic in the first region 27 and laterally spaced apart from the contact region; said second drain electrode being 15 first and second portions of the ohmic layer 26, i.e. from formed on, and in ohmic contact with, a fourth portion the first and the second ohmic contact regions, and also of the ohmic layer 26 extending in the second region through a first portion of the third etch stopper layer 25 28 and defining a fourth ohmic contact region later- extending in the first region 27 beneath said seventh por- ally spaced apart from the third ohmic contact region, tion of the ohmic layer 26, so as to leave exposed an in particular preferably set apart at a distance within 20 upper surface of a first portion of the second cap layer the range of 3-6 mm. 24 extending in the first region 27 beneath said first por- tion of the third etch stopper layer 25. [0017] Preferably said pairs of electrodes 29 and 30 [0024] Furthermore, said second recess 34 is formed are manufactured by forming a first mask (for simplicity, through an eighth portion of the ohmic layer 26 extending not shown in Figure 1) on the ohmic layer 26 so as to 25 in the second region 28 and laterally spaced apart from leave only the four ohmic contact regions exposed. Said the third and fourth portions of the ohmic layer 26, i.e. first mask is conveniently formed by means of a layer of from the third and fourth ohmic contact regions, and also photoresist deposited on the ohmic layer 26 and pat- through a second portion of the third etch stopper layer terned so as to form a respective window on each ohmic 25 extending in the second region 28 beneath said eighth contact region. The metallizations of the source and drain 30 portion of the ohmic layer 26, so as to leave exposed an electrodes are then deposited on the four ohmic contact upper surface of a second portion of the second cap layer regions through the four windows of the first mask and 24 extending in the second region 28 beneath said sec- are subjected to an annealing treatment. ond portion of the third etch stopper layer 25. [0018] After having made the pairs of electrodes 29 [0025] In order to form said first recess 33 and said and 30, the first region 27 and the second region 28 of 35 second recess 34, a third mask 35 is preferably formed the first enhancement/depletion PHEMT device 1 are on the first enhancement/depletion PHEMT device 1 so electrically insulated through ion implantation. as to leave only the upper surfaces of the seventh and [0019] In particular, again with reference to Figure 1, eighth portions of the ohmic layer 26 exposed. a first electrical insulation barrier 31 and a second elec- [0026] Said third mask 35 is conveniently formed by trical insulation barrier 32 are formed by ion implantation 40 means of a layer of photoresist deposited on the first inthe layered epitaxial structure external to the firstregion enhancement/depletion PHEMT device 1 and patterned 27 and the second region 28, respectively, so as to lat- so as to form a first window 35a on the upper surface of erally surround, and therefore electrically insulate, said the seventh portion of the ohmic layer 26 and a second first region 27 and said second region 28, respectively. window 35b on the upper surface of the eighth portion of [0020] The ion implantation is preferably carried out 45 the ohmic layer 26, said first window 35a and said second using a second mask (for simplicity, not shown in Figure window 35b of the third mask 35 having a lateral width 1) formed on the first enhancement/depletion PHEMT preferably within the range of 2-5 mm. device 1 so as to cover the first region 27 and the second [0027] After having formed the third mask 35, the first region 28, or rather so as to leave exposed the upper recess33 and the second recess34 are formed by means surfaces of a fifth and a sixth portion of the ohmic layer 50 of a first etching process, dry or wet, carried out through 26 that extend externally to said first region 27 and to the first window 35a and the second window 35b of said said second region 28, respectively. third mask 35. [0021] Said second mask is conveniently formed by [0028] In particular, said first etching process, which means of a layer of photoresist deposited on the first can be carried out by means of a single chemical solution enhancement/depletion PHEMT device 1 and patterned 55 or an opportune sequence of chemical solutions, re- so as to form a first opening on the upper surface of the moves: fifth portion of the ohmic layer 26 and a second opening on the upper surface of the sixth portion of the ohmic • the seventh portion of the ohmic layer 26 and also

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the underlying first portion of the third etch stopper [0035] With reference to Figure 4, after having formed layer 25, stopping at the interface with the second the third recess 36, said third recess 36 is widened, form- cap layer 24 so as to leave exposed the upper sur- ing a widened third recess 36* extending in the first region face of the first portion of said second cap layer 24 27 and a fourth recess 38 and a fifth recess 39 are si- extending in the first region 27 beneath the first por- 5 multaneously formed in the first region 27 and in the sec- tion of the third etch stopper layer 25 removed by ond region 28, respectively. said first etching process; and [0036] In particular, said widened third recess 36* is • the eighth portion of the ohmic layer 26 and also the formed through a second sub-portion of the first portion underlying second portion of the third etch stopper of the second cap layer 24 that extends in the first region layer 25, stopping at the interface with the second 10 27 and that, before said widening, laterally surrounds the cap layer 24 so as to leave exposed the upper sur- third recess 36, through a second portion of the first cap face of the second portion of said second cap layer layer 23 that extends in the first region 27 beneath said 24 extending in the second region 28 beneath the second sub-portion of the first portion of the second cap second portion of the third etch stopper layer 25 re- layer 24 and that, before said widening, laterally sur- moved by said first etching process. 15 rounds the third recess 36, and also through a second portion of the second etch stopper layer 22 that extends [0029] With reference to Figure 3, after having formed in the first region 27 beneath said second portion of the the first recess 33 and the second recess 34, a third re- first cap layer 23 and that, before said widening, laterally cess 36 is formed in the first region 27. surrounds the third recess 36, so as to leave exposed an [0030] In particular, said third recess 36 is formed20 upper surface of a second portion of the second depletion through a first sub-portion of the first portion of the second barrier layer 21 that extends in the first region 27 beneath cap layer 24, through a first portion of the first cap layer said second portion of the second etch stopper layer 22, 23 extending in the first region 27 beneath said first sub- and that, before the formation of the fourth recess 38, portion of the first portion of the second cap layer 24, and laterally surrounds the first portion of the second deple- also through a first portion of the second etch stopper 25 tion barrier layer 21, while, after the formation of the fourth layer 22 extending in the first region 27 beneath said first recess 38, laterally surrounds said fourth recess 38. portion of the first cap layer 23, so as to leave exposed [0037] Furthermore, said fourth recess 38 is formed an upper surface of a first portion of the second depletion through the first portion of the second depletion barrier barrier layer 21 extending in the first region 27 beneath layer 21, through a portion of the first depletion barrier said first portion of the second etch stopper layer 22. 30 layer 20 extending in the first region 27 beneath said first [0031] In order to form said third recess 36, a fourth portion of the second depletion barrier layer 21, and also mask 37 is preferably formed on the first enhance- through a portion of the first etch stopper layer 19 ex- ment/depletion PHEMT device 1 so as to leave exposed tending in the first region 27 beneath said portion of the only an upper surface of the first sub-portion of the first first depletion barrier layer 20, so as to leave exposed an portion of the second cap layer 24. 35 upper surface of a portion of the enhancement barrier [0032] Said fourth mask 37 is conveniently formed by layer 18 that extends in the first region 27 beneath said means of a layer of photoresist deposited on the first portion of the first etch stopper layer 19 and defines a enhancement/depletion PHEMT device 1 and patterned first Schottky contact region. so as to form a window 37a on the upper surface of the [0038] Furthermore, said fifth recess 39 is formed first sub-portion of the first portion of the second cap layer 40 through a first sub-portion of the second portion of the 24, said window 37a of the fourth mask 37 having a lateral second cap layer 24, through a third portion of the first width preferably within the range of 0.1-0.5 mm. cap layer 23 extending in the second region 28 beneath [0033] After having formed the fourth mask 37, the third said first sub-portion of the second portion of the second recess 36 is formed by means of a second etching proc- cap layer 24, and also through a third portion of the sec- ess, dry or wet, carried out through the window 37a of 45 ond etch stopper layer 22 extending in the second region said fourth mask 37. 28 beneath said third portion of the first cap layer 23, so [0034] In particular, said second etching process, as to leave exposed an upper surface of a third portion which can be carried out by means of a single chemical of the second depletion barrier layer 21 that extends in solution or an opportune sequence of chemical solutions, the second region 28 beneath said third portion of the removes the first sub-portion of the first portion of the50 second etch stopper layer 22 and defines a second second cap layer 24, the first portion of the first cap layer Schottky contact region. 23 and also the first portion of the second etch stopper [0039] In order to widen said third recess 36 and to layer 22, stopping at the interface with the second deple- form said fourth recess 38 and said fifth recess 39, a fifth tion barrier layer 21 so as to leave exposed the upper mask 40 is preferably formed on the first enhance- surface of the first portion of said second depletion barrier 55 ment/depletion PHEMT device 1 so as to leave exposed layer 21 extending in the first region 27 beneath the first only the upper surfaces of the second sub-portion of the portion of the second etch stopper layer 22 removed by first portion of the second cap layer 24, of the first portion said second etching process. of the second depletion barrier layer 21 and of the first

6 11 EP 2 555 242 B1 12 sub-portion of the second portion of the second cap layer [0043] With reference to Figures 5 and 6, after having 24. formed the widened third recess 36*, the fourth recess [0040] Said fifth mask 40 is conveniently formed by 38 and the fifth recess 39, a first gate electrode 41 and means of a layer of photoresist deposited on the first a second gate electrode 42 are formed in the first region enhancement/depletion PHEMT device 1 and patterned 5 27 and in the second region 28, respectively, thereby so as to form: making an enhancement transistor in the first region 27 and a depletion transistor in the second region 28. • a first window 40a on the third recess 36 and the [0044] In particular, said first gate electrode 41 is upper surface of the second sub-portion of the first formed inthe fourthrecess 38, in thewidened third recess portion of the second cap layer 24 that laterally sur- 10 36* and in the first recess 33, and said second gate elec- rounds said third recess 36; and trode 42 is formed in the fifth recess 39 and in the second • a second window 40b on the upper surface of the recess 34. first sub-portion of the second portion of the second [0045] In detail, the first gate electrode 41 is formed so cap layer 24. Preferably, said first window 40a and as to comprise: said second window 40b of the fifth mask 40 have a 15 lateral width within the range of 0.2-0.7 mm or even • a Schottky contact portion that is formed on, and is greater. in Schottky contact with, said portion of the enhance- ment barrier layer 18 defining the first Schottky con- [0041] After having formed the fifth mask 40, the wid- tact region, vertically extending through all of the ened third recess 36*, the fourth recess 38 and the fifth 20 fourth recess 38, and can adhere or not adhere to recess 39 are formed by means of a third etching process, the lateral walls of the fourth recess 38; and dry or wet, carried out through the first window 40a and • a field plate portion that vertically extends through the second window 40b of said fifth mask 40. all of the widened third recess 36* and all of the first [0042] In particular, said third etching process, which recess 33 arriving to protrude in height from said first can be carried out by means of a single chemical solution 25 recess 33, laterally extending on the upper surface or an opportune sequence of chemical solutions, re- of the second portion of the second depletion barrier moves: layer 21 that laterally surrounds the fourth recess 38 so as to rest on and be mechanically supported by • the second sub-portion of the first portion of the sec- said second portion of the second depletion barrier ond cap layer 24, the second portion of the first cap 30 layer 21, and can adhere or not adhere to the lateral layer 23 and the second portion of the second etch walls of the widened third recess 36*. stopper layer 22, stopping at the interface with the second depletion barrier layer 21 so as to leave ex- [0046] Furthermore, the second gate electrode 42 is posed the upper surface of the second portion of formed on, and is in Schottky contact with, said third por- said second depletion barrier layer 21 extending be- 35 tion of the second depletion barrier layer 21 defining the neath the second portion of the second etch stopper second Schottky contact region, is formed so as to ver- layer 22 removed by said third etching process; tically extend through all of the fifth recess 39 and all of • the first portion of the second depletion barrier layer the second recess 34 arriving to protrude in height from 21, the underlying portion of the first depletion barrier said second recess 34, and can adhere or not adhere to layer 20 and the underlying portion of the first etch 40 the lateral walls of the fifth recess 39. stopper layer 19, stopping at the interface with the [0047] Preferably, as shown in Figure 5, said gate elec- enhancement barrier layer 18 so as to leave exposed trodes 41 and 42 are made using the fifth mask 40. the upper surface of the portion of said enhancement [0048] In particular, the first gate electrode 41 is pref- barrier layer 18 that extends beneath the portion of erably made by means of chemical vapour deposition the first etch stopper layer 19 removed by said third 45 self-aligned to the first window 40a of the fifth mask 40 etching process and that defines said first Schottky and the second gate electrode 42 is preferably made by contact region; and means of chemical vapour deposition self-aligned to the • the first sub-portion of the second portion of the sec- second window 40b of said fifth mask 40. ond cap layer 24, the third portion of the first cap [0049] Figure 6 shows the first enhancement/depletion layer 23 and the third portion of the second etch stop- 50 PHEMT device 1 comprising the enhancement transistor per layer 22, stopping at the interface with the second made in the first region 27 and the depletion transistor depletion barrier layer 21 so as to leave exposed the made in the second region 28 after removal of the fifth upper surface of the third portion of said second de- mask 40. pletion barrier layer 21 that extends beneath the third [0050] Figures 7 and 8 are schematic section views of portion of the second etch stopper layer 22 removed 55 a second enhancement/depletion PHEMT device made by said third etching process and that defines said according to a second preferred embodiment of the second Schottky contact region. present invention, said second enhancement/depletion PHEMT device being indicated as a whole in said Figures

7 13 EP 2 555 242 B1 14

7 and 8 by reference numeral 1’. the depletion transistor of the second enhancement/de- [0051] In particular, the second enhancement/deple- pletion PHEMT device 1’ is formed so as to comprise: tion PHEMT device 1’ is made with the same manufac- turing process described in relation to the first enhance- • a respective Schottky contact portion that is formed ment/depletion PHEMT device 1 up to the step of forming 5 on, and is in Schottky contact with, said third portion the widened third recess 36*, the fourth recess 38 and of the second depletion barrier layer 21 defining the the fifth recess 39, while the step of forming the gate second Schottky contact region, vertically extending electrodes of the second enhancement/depletion through all of the fifth recess 39, and can adhere or PHEMT device 1’ is different from that previously de- not adhere to the lateral walls of the fifth recess 39; scribed in relation to the enhancement/depletion PHEMT 10 and device 1. • a respective field plate portion that vertically extends [0052] In detail, with reference to Figures 7 and 8, after through all of the second recess 34 arriving to pro- having formed the widened third recess 36*, the fourth trude in height from said second recess 34, and lat- recess 38 and the fifth recess 39, a first gate electrode erally extending on the upper surface of a second 43 and a second gate electrode 44 of the second en- 15 sub-portion of the second portion of the second cap hancement/depletion PHEMT device 1’ are formed in the layer 24 that laterally surrounds the fifth recess 39 first region 27 and in the second region 28, respectively, so as to rest on and be mechanically supported by of the second enhancement/depletion PHEMT device 1’, said second sub-portion of the second portion of the thereby making an enhancement transistor in said first second cap layer 24. region 27 of the second enhancement/depletion PHEMT 20 device 1’ and a depletion transistor in said second region [0055] Preferably, as shown in Figure 7, in order to 28 of the enhancement/depletion PHEMT device 1’. In form said gate electrodes 43 and 44 of the second en- particular, saidfirst gateelectrode 43 of the enhancement hancement/depletion PHEMT device 1’, a sixth mask 45 transistor of the second enhancement/depletion PHEMT is formed on the second enhancement/depletion PHEMT device 1’ is formed in the fourth recess 38, in the widened 25 device 1’ so as to leave exposed only the upper surfaces third recess 36* and in the first recess 33, while said of the portion of the enhancement barrier layer 18 defin- second gate electrode 44 of the depletion transistor of ing the first Schottky contact region, of the second portion the second enhancement/depletion PHEMT device 1’ is of the second depletion barrier layer 21 that laterally sur- formed in the fifth recess 39 and in the second recess 34. rounds the fourth recess 38, of the third sub-portion of [0053] Entering into even greater detail, the first gate 30 the first portion of the second cap layer 24 that laterally electrode 43 of the enhancement transistor of the second surrounds the widened third recess 36*, of the third por- enhancement/depletion PHEMT device 1’ is formed so tion of the second depletion barrier layer 21 defining the as to comprise: second Schottky contact region and of the second sub- portion of the second portion of the second cap layer 24 • a respective Schottky contact portion that is formed 35 that laterally surrounds the fifth recess 39. on, and is in Schottky contact with, said portion of [0056] Said sixth mask 45 is conveniently formed by the enhancement barrier layer 18 defining the first means of a layer of photoresist deposited on the second Schottky contact region, vertically extending through enhancement/depletion PHEMT device 1’ and patterned all of the fourth recess 38, and can adhere or not so as to form: adhere to the lateral walls of the fourth recess 38; and 40 • a respective field plate portion that vertically extends • a first window 45a on the widened third recess 36* through all of the widened third recess 36* and all of and the upper surface of the third sub-portion of the the first recess 33 arriving to protrude in height from first portion of the second cap layer 24 that laterally said first recess 33, laterally extending on the upper surrounds said widened third recess 36*; and surface of the second portion of the second depletion 45 • a second window 45b on the fifth recess 39 and the barrier layer 21 that laterally surrounds the fourth upper surface of the second sub-portion of the sec- recess 38 so as to rest on and be mechanically sup- ond portion of the second cap layer 24 that laterally ported by said second portion of the second deple- surrounds said fifth recess 39. tion barrier layer 21, also laterally extending on the upper surface of a third sub-portion of the first portion 50 [0057] After having formed the sixth mask 45, the first of the second cap layer 24 that laterally surrounds gate electrode 43 of the enhancement transistor of the the widened third recess 36* so as to rest on and be second enhancement/depletion PHEMT device 1’ is pref- mechanically supported by said third sub-portion of erably made by means of chemical vapour deposition the first portion of the second cap layer 24, and can self-aligned to the first window 45a of the sixth mask 45, adhere or not adhere to the lateral walls of the wid- 55 and the second gate electrode 44 of the depletion tran- ened third recess 36*. sistor of the second enhancement/depletion PHEMT de- vice 1’ is preferably made by means of chemical vapour [0054] Furthermore, the second gate electrode 44 of deposition self-aligned to the second window 45b of said

8 15 EP 2 555 242 B1 16 sixth mask 45. arsenide (GaAs) instead of aluminium gallium arsenide [0058] Figure 8 shows the second enhancement/de- (AlGaAs) as in currently known enhancement/depletion pletion PHEMT device 1’ comprising the enhancement PHEMT devices enables obtaining a lower barrier for the transistor made in the first region 27 and the depletion electrons that flow between the source and drain contacts transistor made in the second region 28 after removal of 5 in the enhancement transistor channel and in the deple- the sixth mask 45. tion transistor channel. [0059] The present invention has numerous advantag- [0064] Finally, the manufacturing of the field plate por- es. tions of the gate electrodes enables reducing the output [0060] In particular, according to the present invention conductance of the enhancement transistors and the de- the etch stopper layers 19, 22 and 25, which enable mak- 10 pletion transistors, said output conductance representing ing the first recess 33, the second recess 34, the third a critical factor for the performance of digital circuits. recess 36, the widened third recess 36*, the fourth recess 38 and the fifth recess 39 in a controlled manner, are made of aluminium arsenide (AlAs) instead of indium gal- Claims lium phosphide (InGaP) as in currently known enhance- 15 ment/depletion PHEMT devices. This innovative charac- 1. A layered epitaxial structure for enhancement and teristic of the present invention ensures that the previ- depletion PHEMT devices (1;1’), comprising: ously described manufacturing processes have high uni- formity and high repeatability. • a superlattice and buffer layer (11); [0061] Furthermore, according to the present inven- 20 • an undoped back-barrier layer (12) formed on tion: the superlattice and buffer layer (11) and made of aluminium gallium arsenide (AlGaAs); • the undoped enhancement barrier layer 18 enables • a doped back delta doping layer (13) formed reducing leakage current from the Schottky contact on the back-barrier layer (12); portions of the first gate electrodes 41 and 43 of the 25 • an undoped back-spacer layer (14) formed on enhancement transistors that are formed on, and in the back delta doping layer (13) and made of Schottky contact with, said enhancement barrier lay- aluminium gallium arsenide (AlGaAs) ; er 18; • an undoped channel layer (15) formed on the • the undoped second depletion barrier layer 21 ena- back-spacer layer (14) and made of indium gal- bles reducing leakage current from the field plate 30 lium arsenide (InGaAs) ; portions of the first gate electrodes 41 and 43 of the • an undoped spacer layer (16) formed on the enhancement transistors that rest on and are me- channel layer (15) and made of aluminium gal- chanically supported by said second depletion bar- lium arsenide (AlGaAs); rier layer 21; • a delta doping layer (17) formed on the spacer • the undoped second depletion barrier layer 21 ena- 35 layer (16); bles reducing leakage current from the Schottky con- • an undoped enhancement barrier layer (18) tact portions of the second gate electrodes 42 and formed on the delta doping layer (17); 44 of the depletion transistors that are formed on, • a doped first etch stopper layer (19), formed and in Schottky contact with, said second depletion on the enhancement barrier layer (18) and made barrier layer 21; and 40 of aluminium arsenide (AlAs); • the undoped second cap layer 24 enables reducing • a doped first depletion barrier layer (20) formed leakage current from the field plate portions of the on the first etch stopper layer (19); first gate electrode 43 and of the second gate elec- • an undoped second depletion barrier layer (21) trode 44 of the second enhancement/depletion formed on the first depletion barrier layer (20); PHEMT device 1’ that rest on and are mechanically 45 • a doped second etch stopper layer (22) formed supported by said second cap layer 24. on the second depletion barrier layer (21) and made of aluminium arsenide (AlAs) ; [0062] In addition, the layered epitaxial structure and • a first cap layer (23) doped with n-type doping, the manufacturing processes according to the present formed on the second etch stopper layer (22) invention enable preventing the aluminium-based layers 50 and made of gallium arsenide (GaAs); from being exposed to air, so as to reduce the phenom- • an undoped second cap layer (24) formed on ena of current breakdown often observed when alumin- the first cap layer (23) and made of gallium ar- ium-based layers are exposed to air. senide (GaAs); [0063] Furthermore, the enhancement barrier layer 18, • a third etch stopper layer (25) doped with n- the first depletion barrier layer 20, the second depletion 55 type doping, formed on the second cap layer barrier layer 21, the first cap layer 23, the second cap (24) and made of aluminium arsenide (AlAs); layer 24 and the ohmic layer 26 made, according to a and preferred embodiment of the present invention, in gallium • an ohmic layer (26) doped with n-type doping,

9 17 EP 2 555 242 B1 18

formed on the third etch stopper layer (25) and formed on, and in ohmic contact with, said made of gallium arsenide (GaAs). ohmic layer (26) in the first region (27) ex- ternally to the first recess (33), and 2. The layered epitaxial structure of claim 1, wherein - a first gate electrode (41;43) formed in the the enhancement barrier layer (18), the first deple- 5 third recess (38) in Schottky contact with tion barrier layer (20) and the second depletion bar- the upper surface of the enhancement bar- rier layer (21) are made of gallium arsenide (GaAs). rier layer (18) defining the first Schottky con- tact region and extending vertically from 3. An enhancement/depletion PHEMT device (1;1’) said first Schottky contact region through comprising: 10 the third (38), the second (36*) and the first recess (33) so as to protrude from said first • the layered epitaxial structure claimed in claim recess (33); and 1 or 2 ; • a first region (27) comprising • a depletion transistor formed in the second re- 15 gion (28) and comprising - a first recess (33) vertically formed through the ohmic layer (26) and the third etch stop- - second source and drain electrodes (30) per layer (25) so as to expose a first upper formed on, and in ohmic contact with, said surface of the second cap layer (24), ohmic layer (26) in the second region (28) - a second recess (36*) that is narrower than 20 externally to the fourth recess (34), and the first recess (33) and which vertically ex- - a second gate electrode (42;44) formed in tends from the first recess (33) through the the fifth recess (39) in Schottky contact with second cap layer (24), the first cap layer (23) the second upper surface of the second de- and the second etch stopper layer (22) so pletion barrier layer (21) defining the second as to expose a first upper surface of the sec- 25 Schottky contact region and extending ver- ond depletion barrier layer (21), and tically from said second Schottky contact re- - a third recess (38) that is narrower than gion through the fifth (39) and the fourth re- the second recess (36*) and which vertically cess (34) so as to protrude from said fourth extends from the second recess (36*) recess (34). through the second depletion barrier layer 30 (21), the first depletion barrier layer (20) and 4. The enhancement/depletion PHEMT device of claim the first etch stopper layer (19) so as to ex- 3, wherein the first gate electrode (41;43) comprises pose an upper surface of the enhancement a field plate portion that laterally extends in the sec- barrier layer (18) defining a first Schottky ond recess (36*) on the first upper surface of the contact region; 35 second depletion barrier layer (21) so as to rest on and be mechanically supported by said first upper • a second region (28) laterally spaced apart, surface of the second depletion barrier layer (21). and electrically insulated, from said first region (27) and comprising 5. The enhancement/depletion PHEMT device of claim 40 4, wherein the field plate portion of the first gate elec- - a fourth recess (34) vertically formed trode (43) laterally extends in the first recess (33) on through the ohmic layer (26) and the third a portion of the first upper surface of the second cap etch stopper layer (25) so as to expose a layer (24) so as to rest on and be mechanically sup- second uppersurface ofthe secondcap lay- ported by said portion of the first upper surface of er (24), and 45 the second cap layer (24). - a fifth recess (39) that is narrower than the fourth recess (34) and which vertically ex- 6. The enhancement/depletion PHEMT device accord- tends from the fourth recess (34) through ing to any of claims 3-5, wherein the second gate the second cap layer (24), the first cap layer electrode (44) comprises a field plate portion that (23) and the second etch stopper layer (22) 50 laterally extends in the fourth recess (34) on a portion so as to expose a second upper surface of of the second upper surface of the second cap layer the second depletion barrier layer (21) de- (24) so as to rest on and be mechanically supported fining a second Schottky contact region; by said portion of the second upper surface of the second cap layer (24). • an enhancement transistor formed in the first 55 region (27) and comprising 7. A method of manufacturing an enhancement/deple- tion PHEMT device, comprising: - first source and drain electrodes (29)

10 19 EP 2 555 242 B1 20

• providing a layered epitaxial structure that in- taxial structure laterally spaced apart from said cludes first region (27), said first pair of electrodes (29) comprising a first source electrode and a first - a superlattice and buffer layer (11), drain electrode, said second pair of electrodes - an undoped back-barrier layer (12) formed 5 (30) comprising a second source electrode and on the superlattice and buffer layer (11) and a second drain electrode; made of aluminium gallium arsenide (Al- • electrically insulating the first region (27) and GaAs), the second region (28); - a doped back delta doping layer (13) • forming formed on the back-barrier layer (12), 10 - an undoped back-spacer layer (14) formed - in the first region (27), a first recess (33) on the back delta doping layer (13) and that is laterally spaced apart from the first made of aluminium gallium arsenide (Al- pair of electrodes (29) and which vertically GaAs), extends through the ohmic layer (26) and - an undoped channel layer (15) formed on 15 the third etch stopper layer (25) so as to the back-spacer layer (14) and made of in- expose a first upper surface of the second dium gallium arsenide (InGaAs), cap layer (24), and - an undoped spacer layer (16) formed on - in the second region (28), a second recess the channel layer (15) and made of alumin- (34) that is laterally spaced apart from the ium gallium arsenide (AlGaAs), 20 second pair of electrodes (30) and which - a delta doping layer (17) formed on the vertically extends through the ohmic layer spacer layer (16), (26) and the third etch stopper layer (25) so - an undoped enhancement barrier layer as to expose a second upper surface of the (18) formed on the delta doping layer (17), second cap layer (24); - a doped first etch stopper layer (19) formed 25 on the enhancement barrier layer (18) and • forming made of aluminium arsenide (AlAs), - a doped first depletion barrier layer (20) - in the first region (27), a third recess (36*) formed on the first etch stopper layer (19), that is narrower than the first recess (33) - an undoped second depletion barrier layer 30 and which vertically extends from the first (21) formed on the first depletion barrier lay- recess (33) through the second cap layer er (20), (24), the first cap layer (23) and the second - a doped second etch stopper layer (22) etch stopper layer (22) so as to expose a formed on the second depletion barrier lay- first upper surface of the second depletion er (21) and made of aluminium arsenide 35 barrier layer (21), (AlAs), - in the first region (27), a fourth recess (38) - afirst cap layer (23) dopedwith n-typedop- that is narrower than the third recess (36*) ing, formed on the second etch stopper lay- and which vertically extends from the third er (22) and made of gallium arsenide recess (36*) through the second depletion (GaAs), 40 barrier layer (21), the first depletion barrier - an undoped second cap layer (24) formed layer (20) and the first etch stopper layer on the first cap layer (23) and made of gal- (19) so as to expose an upper surface of lium arsenide (GaAs), the enhancement barrier layer (18) defining - a third etch stopper layer (25) doped with a first Schottky contact region, and n-type doping, formed on the second cap 45 - in the second region (28), a fifth recess layer (24) and made of aluminium arsenide (39) that is narrower than the second recess (AlAs), and (34) and which vertically extends from the - a ohmic layer (26) doped with n-type dop- second recess (34) through the second cap ing, formed on the third etch stopper layer layer (24), the first cap layer (23) and the (25) and made of gallium arsenide (GaAs) ; 50 second etch stopper layer (22) so as to ex- pose a second upper surface of the second • forming a first pair of electrodes (29) of an en- depletion barrier layer (21) defining a sec- hancement transistor on, and in ohmic contact ond Schottky contact region; and with, said ohmic layer (26) in a first region (27) of the layered epitaxial structure and a second 55 • forming pair of electrodes (30) of a depletion transistor on, and in ohmic contact with, said ohmic layer - in the fourth recess (38), a first gate elec- (26) in a second region (28) of the layered epi- trode (41;43) of the enhancement transistor

11 21 EP 2 555 242 B1 22

in Schottky contact with the upper surface ing from said widened third recess (36*), the fifth of the enhancement barrier layer (18) defin- recess(39) and a second portion ofthe secondupper ing the first Schottky contact region, said surface of the second cap layer (24) laterally extend- first gate electrode (41;43) vertically extend- ing from said fifth recess (39) to the chemical vapour ing from said first Schottky contact region 5 deposition. through the fourth (38), the third (36*) and the first recess (33) so as to protrude from 11. The method according to any of claims 7-10, wherein said first recess (33), and electrically insulating the first region (27) and the sec- - in the fifth recess (39), a second gate elec- ond region (28) comprises forming by ionic implan- trode (42;44) of the depletion transistor in 10 tation: Schottky contact with the second upper sur- face of the second depletion barrier layer • a first electrical insulation barrier (31) surround- (21) defining the second Schottky contact ing the first region (27) and vertically extending region, said second gate electrode (42;44) through all the layers of the layered epitaxial vertically extending from said second15 structure; and Schottky contact region through the fifth • a second electrical insulation barrier (32) sur- (39) and the second recess (34) so as to rounding the second region (28) and vertically protrude from said second recess (34). extending through all the layers of the layered epitaxial structure. 8. The method of claim 7, wherein forming the third20 recess (36*), the fourth recess (38) and the fifth re- cess (39) comprises: Patentansprüche

• forming a third recess (36) by means of a first 1. Eine geschichtete epitaktische Struktur für Anreiche- etching process carried out by using a first mask 25 rungs- und Verarmungs- PHEMT-Vorrichtungen (1; (37) formed on the layered epitaxial structure, 1’), umfassend: on the first pair of electrodes (29) and on the second pair of electrodes (30) so as to expose ein Übergitter und eine Pufferschicht (11); a first portion of the first upper surface of the eine auf dem Übergitter und der Puffer Schicht second cap layer (24) to said first etching proc- 30 (11) ausgebildete und aus Aluminiumgalliumar- ess; and senid (AlGaAs) hergestellte undotierte Rück- • widening said third recess (36) and forming the sperrschicht (12); fourth recess (38) and the fifth recess (39) by eine auf der Rücksperrschicht (12) ausgebildete means of a second etching process carried out dotierte Rückdeltadotierungsschicht (13); by using a second mask (40) formed on the lay- 35 eine auf der Rückdeltadotierungsschicht (13) ered epitaxial structure, on the first pair of elec- ausgebildete und aus Aluminiumgalliumarsenid trodes (29) and on the second pair of electrodes (AlGaAs) hergestellte undotierte Rückab- (30) so as to expose the third recess (36), a sec- standsschicht (14); ond portion of the first upper surface of the sec- eine auf der Rückabstandsschicht (14) ausge- ond cap layer (24) laterally extending from said 40 bildete und aus Indiumgalliumarsenid (InGaAs) third recess (36) and a first portion of the second hergestellte undotierte Kanalschicht (15); upper surface of the second cap layer (24) to eine auf der Kanalschicht (15) ausgebildete und said second etching process. aus Aluminiumgalliumarsenid (AlGaAs) herge- stellte undotierte Abstandsschicht (16); 9. The method of claim 8, wherein the first gate elec- 45 eine auf der Abstandsschicht (16) ausgebildete trode (41) and the second gate electrode (42) are Deltadotierungsschicht (17); formed by means of chemical vapour deposition car- eine auf der Deltadotierungsschicht (17) ausge- ried out by using the second mask (40). bildete undotierte Anreicherungssperrschicht (18); 10. The method of claim 8, wherein the first gate elec- 50 eine auf der Anreicherungssperrschicht (18) trode (43) and the second gate electrode (44) are ausgebildete und aus Aluminiumarsenid (AlAs) formed by means of chemical vapour deposition car- hergestellte dotierte erste Ätzstoppschicht (19); ried out by using a third mask (45) formed on the eine auf der ersten Ätzstoppschicht (19) ausge- layered epitaxial structure, on the first pair of elec- bildete dotierte erste Verarmungssperrschicht trodes (29) and on the second pair of electrodes (30) 55 (20); so as to expose the fourth recess (38), the widened eine auf der ersten Verarmungssperrschicht third recess (36*), a third portion of the first upper (20) ausgebildete undotierte zweite Verar- surface of the second cap layer (24) laterally extend- mungssperrschicht (21);

12 23 EP 2 555 242 B1 24

eine auf der zweiten Verarmungssperrschicht standeten und elektrisch isolierten zweiten Re- (21) ausgebildete und aus Aluminiumarsenid gion (28), die umfasst: (AlAs) hergestellte dotierte zweite Ätzstopp- schicht (22); - eine vertikal durch die Ohmsche Schicht eine auf der zweiten Ätzstoppschicht (22) aus- 5 (26) und die dritte Ätzstoppschicht (25) aus- gebildete und aus Galliumarsenid (GaAs) her- gebildete vierte Vertiefung (34), so dass ei- gestellte, mit n- Typ Dotierung dotierte erste ne zweite obere Oberfläche der zweiten Deckschicht (23); Deckschicht (24) freiliegt, und eine auf der ersten Deckschicht (23) ausgebil- - eine fünfte Vertiefung (39), die enger als dete und aus Galliumarsenid (GaAs) hergestell- 10 die vierte Vertiefung (34) ist und die sich te undotierte zweite Deckschicht (24); vertikal von der vierten Vertiefung (34) eine auf der zweiten Deckschicht (24) ausgebil- durch die zweite Deckschicht (24), die erste dete und aus Aluminiumarsenid (AlAs) herge- Deckschicht (23) und die zweite Ätzstopp- stellte, mit n- Typ Dotierung dotierte dritte Ätz- schicht (22) erstreckt, so dass eine zweite stoppschicht (25); 15 obere Oberfläche der zweiten Verarmungs- eine auf der dritten Ätzstoppschicht (25) ausge- sperrschicht (21), die eine zweite Schottky- bildete und aus Galliumarsenid (GaAs) herge- Kontakt-Region definiert, freiliegt; stellte, mit n- Typ Dotierung dotierte Ohmschen Schicht (26). einem in der ersten Region (27) ausgebildeten 20 Anreicherungstransistor, der umfasst: 2. Die geschichtete epitaktische Struktur gemäß An- spruch 1, wobei die Anreicherungssperrschicht (18), - erste Source- und Drainelektroden (29), die erste Verarmungssperrschicht (20) und die zwei- die in der ersten Region (27) außerhalb der te Verarmungssperrschicht (21) aus Galliumarsenid ersten Vertiefung (33) auf der Ohmschen (GaAs) hergestellt sind. 25 Schicht (26) ausgebildet sind und mit der Ohmschen Schicht (26) in Ohmschen Kon- 3. Eine Anreicherungs- /Verarmungs- PHEMT- Vor- takt stehen, und richtung (1; 1’) mit: - eine in der dritten Vertiefung (38) in Schott- ky- Kontakt mit der oberen Oberfläche der dergeschichteten epitaktischen Struktur gemäß 30 Anreicherungssperrschicht (18) ausgebil- Anspruch 1 oder 2; dete ersteGatelektrode (41; 43), die dieers- einer ersten Region (27) umfassend: te Schottky- Kontakt- Region definiert und sich vertikal von der ersten Schottky- Kon- - eine vertikal durch die Ohmsche Schicht takt-Region durch die dritte (38), die zweite (26) und die dritte Ätzstoppschicht (25) aus- 35 (36*) und die erste Vertiefung (33) erstreckt, gebildete erste Vertiefung (33), so dass ei- so dass sie aus der ersten Vertiefung (33) ne erste obere Oberfläche der zweiten heraus ragt; und Deckschicht (24) freiliegt, - eine zweite Vertiefung (36*), die enger als einem in der zweiten Region (28) ausgebildeten die erste Vertiefung (33) ist, und die sich 40 Verarmungstransistor, der umfasst vertikal von der ersten Vertiefung (33) durch die zweite Deckschicht (24), die erste Deck- - zweite Source- und Drainelektroden (30), schicht (23) und die zweite Ätzstoppschicht die in der zweiten Region (28) außerhalb (22) erstreckt, so dass eine erste obere der vierten Vertiefung (34) auf der Ohm- Oberfläche der zweiten Verarmungssperr- 45 schen Schicht (26) ausgebildet sind und mit schicht (21) freiliegt, und der Ohmschen Schicht (26) in Ohmschen - eine dritte Vertiefung (38), die enger als Kontakt stehen, und die zweite Vertiefung (36*) ist, und die sich - eine in der fünften Vertiefung (39) in vertikal von der zweiten Vertiefung (36*) Schottky- Kontakt mit der zweiten oberen durch die zweite Verarmungssperrschicht 50 Oberfläche der zweiten Verarmungssperr- (21), die erste Verarmungssperrschicht schicht (21) ausgebildete zweite Gatelekt- (20) und die erste Ätzstoppschicht (19) er- rode (42; 44), die die zweite Schottky- Kon- streckt, so dass eine obere Oberfläche der takt- Region definiert und sich vertikal von Anreicherungssperrschicht (18), die eine der zweiten Schottky- Kontakt- Region erste Schottky- Kontakt- Region definiert, 55 durch die fünfte (39) und die vierte Vertie- freiliegt; fung (34) erstreckt, so dass sie aus der vier- ten Vertiefung (34) heraus ragt. einer von der ersten Region (27) lateral beab-

13 25 EP 2 555 242 B1 26

4. Die Anreicherungs- /Verarmungs- PHEMT- Vorrich- - eine auf der Abstandsschicht (16) ausge- tung gemäß Anspruch 3, wobei die erste Gateelek- bildete Deltadotierungsschicht (17); trode (41; 43) einen Feldplattenbereich umfasst, der - eine auf der Deltadotierungsschicht (17) sich lateral in die zweite Vertiefung (36*) auf der ers- ausgebildete undotierte Anreicherungs- ten oberen Oberfläche der zweiten Verarmungs- 5 sperrschicht (18); sperrschicht (21) erstreckt, so dass er auf der ersten - eine auf der Anreicherungssperrschicht oberen Oberfläche der zweiten Verarmungsbarrier- (18) ausgebildete und aus Aluminiumarse- eschicht (21) aufliegt und mechanisch von der ersten nid (AlAs) hergestellte dotierte erste Ätz- oberen Oberfläche der zweiten Verarmungsbarrier- stoppschicht (19); eschicht (21) gestützt ist. 10 - eine auf der ersten Ätzstoppschicht (19) ausgebildete dotierte erste Verarmungs- 5. Die Anreicherungs- /Verarmungs- PHEMT- Vorrich- sperrschicht (20); tung gemäß Anspruch 4, wobei der Feldplattenbe- - eine auf der ersten Verarmungssperr- reich der ersten Gateelektrode (43) sich lateral in die schicht (20) ausgebildete undotierte zweite ersten Vertiefung (33) auf einen Bereich der ersten 15 Verarmungssperrschicht (21); oberen Oberfläche der zweiten Deckschicht (24) er- - eine auf der zweiten Verarmungssperr- streckt, so dass er auf dem Bereich der ersten obe- schicht (21) ausgebildete und aus Alumini- ren Oberfläche der zweiten Deckschicht (24) aufliegt umarsenid (AlAs) hergestellte dotierte und mechanisch vom Bereich der ersten oberen zweite Ätzstoppschicht (22); Oberfläche der zweiten Deckschicht (24) gestützt ist. 20 - eine auf der zweiten Ätzstoppschicht (22) ausgebildete und aus Galliumarsenid 6. Die Anreicherungs- /Verarmungs- PHEMT- Vorrich- (GaAs) hergestellte, mit n- Typ Dotierung tung gemäß einem der Ansprüche 3-5, wobei die dotierte ersten Deckschicht (23); zweite Gateelektrode (44) einen Feldplattenbereich - eine auf der ersten Deckschicht (23) aus- umfasst, der sich lateral in die vierte Vertiefung (34) 25 gebildete und aus Galliumarsenid (GaAs) auf einen Bereich der zweiten oberen Oberfläche hergestellte undotierte zweite Deckschicht der zweiten Deckschicht (24) erstreckt, so dass er (24); auf dem Bereich der zweiten oberen Oberfläche der - eine auf der zweiten Deckschicht (24) aus- zweiten Deckschicht (24) aufliegt und mechanisch gebildete und aus Aluminiumarsenid (AlAs) vom Bereich der zweiten oberen Oberfläche der30 hergestellte, mit n- Typ Dotierung dotierte zweiten Deckschicht (24) gestützt ist. dritte Ätzstoppschicht (25); - eine auf der dritten Ätzstoppschicht (25) 7. Ein Verfahren zur Herstellung einer Anreicherungs- ausgebildete und aus Galliumarsenid /Verarmungs- PHEMT- Vorrichtung, umfassend: (GaAs) hergestellte, mit n- Typ Dotierung 35 dotierte Ohmschen Schicht (26); Bereitstellen einer geschichteten epitaktischen Struktur, die enthält: Ausbilden eines ersten Elektrodenpaars (29) ei- nes Anreicherungstransistors auf der Ohm- - ein Übergitter und eine Pufferschicht (11); schen Schicht (26) und mit der Ohmschen - ein auf dem Übergitter und der Puffer40 Schicht (26) in Ohmschen Kontakt in einer ers- Schicht (11) ausgebildete und aus Alumini- ten Region (27) der geschichteten epitaktischen umgalliumarsenid (AlGaAs) hergestellte Struktur und eines zweiten Elektrodenpaars undotierte Rücksperrschicht (12); (30) eines Verarmungstransistors auf der Ohm- - eine auf der Rücksperrschicht (12) ausge- schen Schicht (26) und mit der Ohmschen bildete dotierte Rückdeltadotierungs-45 Schicht (26) in Ohmschen Kontakt in einer zwei- schicht (13); ten Region (28) der geschichteten epitaktischen - eine auf der Rückdeltadotierungsschicht Struktur, die lateral beabstandet von der ersten (13) ausgebildete und aus Aluminiumgalli- Region (27) ist, wobei das erste Elektrodenpaar umarsenid (AlGaAs)hergestellte undotierte (29) eine erste Sourceelektrode und eine erste Rückabstandsschicht (14) 50 Drainelektrode aufweist, wobei das zweite Elek- - eine auf der Rückabstandsschicht (14) trodenpaar (30) eine zweite Sourceelektrode ausgebildete und aus Indiumgalliumarse- und eine zweite Drainelektrode aufweist; nid (InGaAs) hergestellte undotierte Kanal- Elektrisches Isolieren der ersten Region (27) schicht (15); und der zweiten Region (28); - eine auf der Kanalschicht (15) ausgebil- 55 Ausbilden dete und aus Aluminiumgalliumarsenid (AlGaAs) hergestellte undotierte Abstands- - einer ersten Vertiefung (33) in der ersten schicht (16); Region (27), die lateral vom ersten Elektro-

14 27 EP 2 555 242 B1 28

denpaar (29) beabstandet ist, und die sich tiefung (33) erstreckt, so dass sie aus der vertikal durch die Ohmsche Schicht (26) ersten Vertiefung (33) heraus ragt, und und die dritte Ätzstoppschicht (25) er- - einer zweiten Gateelektrode (42; 44) des streckt, so dass eine erste obere Oberflä- Verarmungstransistors in der fünften Ver- che der zweiten Deckschicht (24) freigelegt 5 tiefung (39) in Schottky- Kontakt mit der wird, und zweiten oberen Oberfläche der zweiten - einer zweiten Vertiefung (34) in der zwei- Verarmungssperrschicht (21), die die zwei- ten Region (28), die lateral vom zweiten te Schottky- Kontakt- Region definiert, wo- Elektrodenpaar (30) beabstandet ist, und bei sich die zweite Gateleketrode (42; 44) die sich vertikal durch die Ohmsche Schicht 10 vertikal von der zweiten Schottky- Kontakt- (26) und die dritte Ätzstoppschicht (25) er- Region durch die fünfte (39) und die zweite streckt, so dass eine zweite obere Oberflä- Vertiefung (34) erstreckt, so dass sie aus che der zweiten Deckschicht (24) freigelegt der zweiten Vertiefung (34) heraus ragt. wird, 15 8. Das Verfahren gemäß Anspruch 7, wobei das Aus- Ausbilden bilden der dritten Vertiefung (36*), der vierten Ver- tiefung (38) und der fünften Vertiefung (39) umfasst: - einer dritten Vertiefung (36*) in der ersten Region (27), die enger als die erste Vertie- Ausbilden einer dritten Vertiefung (36) durch ei- fung (33) ist, und die sich vertikal von der 20 nen ersten Ätzprozess, der durch Verwendung ersten Vertiefung (33) durch die zweite einer auf der geschichteten epitaktischen Struk- Deckschicht (24), die erste Deckschicht tur ausgebildeten ersten Maske (37) auf dem (23) und die zweite Ätzstoppschicht (22) er- ersten Elektrodenpaar (29) und auf dem zweiten streckt, so dass eine erste obere Oberflä- Elektrodenpaar (30) ausgeführt wird, so dass che der zweite Verarmungssperrschicht25 ein erster Bereich der ersten oberen Oberfläche (21) freigelegt wird, der zweiten Deckschicht (24) dem ersten Ätz- - einer vierten Vertiefung (38) in der ersten prozess ausgesetzt wird; und Region (27), die enger als die dritte Vertie- Verbreitern der dritten Vertiefung (36) und Aus- fung (36*) ist, und die sich vertikal von der bilden der vierten Vertiefung (38) und der fünften dritten Vertiefung (33) durch die zweite Ver- 30 Vertiefung (39) durch einen zweiten Ätzprozess, armungssperrschicht (21), die erste Verar- der durch Verwendung einer auf der geschich- mungssperrschicht (20) und die erste Ätz- teten epitaktischen Struktur, auf dem ersten stoppschicht (19) erstreckt, so dass eine Elektrodenpaar (29) und auf dem zweiten Elek- obere Oberfläche der Anreicherungssperr- trodenpaar (30) ausgebildeten zweiten Maske schicht (18), die eine erste Schottky- Kon- 35 (40) ausgeführt wird, so dass die dritte Vertie- takt- Region definiert, freigelegt wird, und fung (36), ein zweiter Bereich der ersten oberen - einer fünften Vertiefung (39) in der zweiten Oberfläche der zweiten Deckschicht (24), die Region (28), die enger als die zweite Ver- sich lateral von der dritten Vertiefung (36) er- tiefung (34) ist, und die sich vertikal von der streckt, und ein erster Bereich der zweiten obe- zweiten Vertiefung (34) durch die zweite 40 ren Oberfläche der zweiten Deckschicht (24) Deckschicht (24), die erste Deckschicht dem zweiten Ätzprozess ausgesetzt wird. (23) und die zweite Ätzstoppschicht (22) er- streckt, so dass eine zweite obere Oberflä- 9. Das Verfahren gemäß Anspruch 8, wobei die erste che der zweiten Verarmungssperrschicht Gateelektrode (41) und die zweite Gateelektrode (21), die eine zweite Schottky- Kontakt- Re- 45 (42) mittels Ausführung einer chemischen Gasab- gion definiert, freigelegt wird, scheidung durch Verwendung der zweiten Maske (40) ausgebildet werden. Ausbilden 10. Das Verfahren gemäß Anspruch 8, wobei die erste - einer ersten Gateelektrode (41; 43) des 50 Gateelektrode (43) und die zweite Gateelektrode Verstärkungstransistors in der vierten Ver- (44) mittels Ausführung einer chemischen Gasab- tiefung (38) in Schottky- Kontakt mit der scheidung durch Verwendung einer dritten Maske oberen Oberfläche der Anreicherungs- (45) ausgebildet wird, die auf der geschichteten epi- sperrschicht (18), die die erste Schottky- taktischen Struktur, auf dem ersten Elektrodenpaar Kontakt- Region definiert, wobei sich die 55 (29) und auf dem zweiten Elektrodenpaar (30) aus- ersteGateelektrode (41; 43) vertikal vonder gebildet wird, so dass die vierte Vertiefung (38), die ersten Schottky- Kontakt- Region durch die verbreiterte dritte Vertiefung (36*), ein dritter Bereich vierte (38), die dritte (36*) und die erste Ver- der ersten oberen Oberfläche der zweiten Deck-

15 29 EP 2 555 242 B1 30

schicht (24), die sich lateral von der verbreiterten • une deuxième couche de barrière à appauvris- dritten Vertiefung (36*) erstreckt, der fünften Vertie- sement non dopée (21) formée sur la première fung (39) und ein zweiter Bereich der zweiten oberen couche de barrière à appauvrissement (20) ; Oberfläche der zweiten Deckschicht (24), die sich • une deuxième couche d’arrêt d’attaque dopée lateral von der fünften Vertiefung (39) erstreckt, der 5 (22) formée sur la deuxième couche de barrière chemischen Gasabscheidung ausgesetzt wird. à appauvrissement (21) et composée d’arséniu- re d’aluminium (AlAs) ; 11. Das Verfahren gemäß jedem der Ansprüche 7- 10, • une première couche chapeau (23) dopée wobei das elektrische Isolieren der ersten Region avec un agent de dopage du type n, formée sur (27) und der zweiten Region (28) die Ausbildung ei- 10 la deuxième couche d’arrêt d’attaque (22) et ner Ionenimplementierung umfasst: composée d’arséniure de gallium (GaAs) ; • une deuxième couche chapeau non dopée (24) eine die erste Region (27) umgebende und sich formée sur la première couche chapeau (23) et vertikal durch alle Schichten der geschichteten composée d’arséniure de gallium (GaAs) ; epitaktischen Struktur erstreckende erste elek- 15 • une troisième couche d’arrêt d’attaque (25) do- trische Isolationssperre (31); und pée avec un agent de dopage du type n, formée eine die zweite Region (28) umgebende und sur la deuxième couche chapeau (24) et com- sich vertikal durch alle Schichten der geschich- posée d’arséniure d’aluminium (AlAs) ; et teten epitaktischen Struktur erstreckende zwei- • une couche ohmique (26) dopée avec un agent te elektrische Insolationssperre (32). 20 de dopage du type n, formée sur la troisième couche d’arrêt d’attaque (25) et composée d’ar- séniure de gallium (GaAs). Revendications 2. Structure épitaxiale en couches selon la revendica- 1. Structure épitaxiale en couches pour dispositifs25 tion 1, dans laquelle la couche de barrière à enri- PHEMT à enrichissement et appauvrissement (1 ; chissement (18), la première couche de barrière à 1’), comprenant : appauvrissement (20) et la deuxième couche de bar- rière à appauvrissement (21) sont composées d’ar- • une couche de tampon et de super-réseau séniure de gallium (GaAs). (11) ; 30 • une couche de barrière arrière non dopée (12) 3. Dispositif PHEMT à enrichissement et appauvrisse- formée sur la couche de tampon et de super- ment (1 ; 1’) comprenant : réseau (11) et composée d’arséniure de gal- lium-aluminium (AlGaAs) ; • la structure épitaxiale en couches selon la re- • une couche de dopage delta arrière dopée (13) 35 vendication 1 ou 2 ; formée sur la couche de barrière arrière (12) ; • une première région (27) comprenant • une couche d’écartement arrière non dopée (14) formée sur la couche de dopage delta ar- - un premier renfoncement (33) verticale- rière (13) et composée d’arséniure de gallium- ment formé dans la couche ohmique (26) aluminium (AlGaAs) ; 40 et la troisième couche d’arrêt d’attaque (25) • une couche de canal non dopée (15) formée de manière à exposer une première surface sur la couche d’écartement arrière (14) et com- supérieure de la deuxième couche chapeau posée d’arséniure de gallium-indium (InGaAs) ; (24), • une couche d’écartement non dopée (16) for- - un deuxième renfoncement (36*) qui est mée sur la couche de canal (15) et composée 45 plus étroit que le premier renfoncement (33) d’arséniure de gallium-aluminium (AlGaAs) ; et qui s’étend verticalement depuis le pre- • une couche de dopage delta (17) formée sur mier renfoncement (33) dans la deuxième la couche d’écartement (16) ; couche chapeau (24), la première couche • une couche de barrière à enrichissement non chapeau (23) et la deuxième couche d’arrêt dopée (18) formée sur la couche de dopage del- 50 d’attaque (22) de manière à exposer une ta (17) ; première surface supérieure de la deuxiè- • une première couche d’arrêt d’attaque dopée me couche de barrière à appauvrissement (19) formée sur la couche de barrière à enrichis- (21), et sement (18) et composée d’arséniure d’alumi- - un troisième renfoncement (38) qui est nium (AlAs) ; 55 plus étroit que le deuxième renfoncement • une première couche de barrière à appauvris- (36*) et qui s’étend verticalement depuis le sement dopée (20) formée sur la première cou- deuxième renfoncement (36*) dans la che d’arrêt d’attaque (19) ; deuxième couche de barrière à appauvris-

16 31 EP 2 555 242 B1 32

sement (21), la première couche de barrière formée dans le cinquième renfoncement à appauvrissement (20) et la première cou- (39) en contact Schottky avec la deuxième che d’arrêt d’attaque (19) de manière à ex- surface supérieure de la deuxième couche poser une surface supérieure de la couche de barrière à appauvrissement (21) délimi- de barrière à enrichissement (18) délimitant 5 tant la deuxième région de contact Schottky une première région de contact Schottky ; et s’étendant verticalement depuis ladite deuxième région de contact Schottky dans • une deuxième région (28) latéralement espa- les cinquième (39) et quatrième (34) ren- cée et électriquement isolée de ladite première foncements de manière à faire saillie depuis région (27) et comprenant 10 ledit quatrième renfoncement (34).

- un quatrième renfoncement (34) vertica- 4. Dispositif PHEMT à enrichissement et appauvrisse- lement formé dans la couche ohmique (26) ment selon la revendication 3, dans lequel la pre- et la troisième couche d’arrêt d’attaque (25) mière électrode de grille (41 ; 43) comprend une par- de manière à exposer une deuxième surfa- 15 tie plaque de champ qui s’étend latéralement dans ce supérieure de la deuxième couche cha- le deuxième renfoncement (36*) sur la première sur- peau (24), et face supérieure de la deuxième couche de barrière - un cinquième renfoncement (39) qui est à appauvrissement (21) de manière à reposer sur plus étroit que le quatrième renfoncement ladite première surface supérieure de la deuxième (34) et qui s’étend verticalement depuis le 20 couche de barrière à appauvrissement (21) et à être quatrième renfoncement (34) dans la supportée mécaniquement par celle-ci. deuxième couche chapeau (24), la premiè- re couche chapeau (23) et la deuxième cou- 5. Dispositif PHEMT à enrichissement et appauvrisse- che d’arrêt d’attaque (22) de manière à ex- ment selon la revendication 4, dans lequel la partie poser une deuxième surface supérieure de 25 plaque de champ de la première électrode de grille la deuxième couche de barrière à appau- (43) s’étend latéralement dans le premier renfonce- vrissement (21) délimitant une deuxième ment (33) sur une partie de la première surface su- région de contact Schottky ; périeure de la deuxième couche chapeau (24) de manière à reposer sur ladite partie de la première • un transistor à enrichissement formé dans la 30 surface supérieure de la deuxième couche chapeau première région (27) et comprenant (24) et à être supportée mécaniquement par celle-ci.

- des premières électrodes de source et de 6. Dispositif PHEMT à enrichissement et appauvrisse- drain (29) formées sur ladite couche ohmi- ment selon l’une quelconque des revendications 3 que (26), et en contact ohmique avec celle- 35 à 4, dans lequel la deuxième électrode de grille (44) ci, dans la première région (27) à l’extérieur comprend une partie plaque de champ qui s’étend du premier renfoncement (33), et latéralement dans le quatrième renfoncement (34) - une première électrode de grille (41 ; 43) sur une partie de la deuxième surface supérieure de formée dans le troisième renfoncement (38) la deuxième couche chapeau (24) de manière à re- en contact Schottky avec la surface supé- 40 poser sur ladite partie de la deuxième surface supé- rieure de la couche de barrière à enrichis- rieure de la deuxième couche chapeau (24) et à être sement (18) délimitant la première région supportée mécaniquement par celle-ci. de contact Schottky et s’étendant verticale- ment depuis ladite première région de con- 7. Procédé de fabrication d’un dispositif PHEMT à en- tact Schottky dans les troisième (38),45 richissement et appauvrissement, comprenant les deuxième (36*) et premier (33) renfonce- étapes consistant à : ments de manière à faire saillie depuis ledit premier renfoncement (33) ; et • fournir une structure épitaxiale en couches qui comprend • un transistor à appauvrissement formé dans 50 la deuxième région (28) et comprenant - une couche de tampon et de super-réseau (11), - des deuxièmes électrodes de source et de - une couche de barrière arrière non dopée drain (30) formées sur ladite couche ohmi- (12) formée sur la couche de tampon et de que (26), et en contact ohmique avec celle- 55 super-réseau (11) et composée d’arséniure ci, dans la deuxième région (28) à l’extérieur de gallium-aluminium (AlGaAs), du quatrième renfoncement (34), et - une couche de dopage delta arrière dopée - une deuxième électrode de grille (42 ; 44) (13) formée sur la couche de barrière arrière

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(12), vrissement sur ladite couche ohmique (26), et - une couche d’écartement arrière non do- en contact ohmique avec celle-ci, dans une pée (14) formée sur la couche de dopage deuxième région (28) de la structure épitaxiale delta arrière (13) et composée d’arséniure en couches latéralement espacée de ladite pre- de gallium-aluminium (AlGaAs), 5 mière région (27), ladite première paire d’élec- - une couche de canal non dopée (15) for- trodes (29) comprenant une première électrode mée sur la couche d’écartement arrière (14) de source et une première électrode de drain, et composée d’arséniure de gallium-indium ladite deuxième paire d’électrodes (30) compre- (InGaAs), nant une deuxième électrode de source et une - une couche d’écartement non dopée (16) 10 deuxième électrode de drain ; formée sur la couche de canal (15) et com- • isoler électriquement la première région (27) posée d’arséniure de gallium-aluminium et la deuxième région (28) ; (AlGaAs), • former - une couche de dopage delta (17) formée sur la couche d’écartement (16), 15 - dans la première région (27), un premier - une couche de barrière à enrichissement renfoncement (33) qui est latéralement es- non dopée (18) formée sur la couche de do- pacé de la première paire d’électrodes (29) page delta (17), et qui s’étend verticalement dans la couche - une première couche d’arrêt d’attaque do- ohmique (26) et dans la troisième couche pée (19) formée sur la couche de barrière 20 d’arrêt d’attaque (25) de manière à exposer à enrichissement (18) et composée d’arsé- une première surface supérieure de la niure d’aluminium (AlAs), deuxième couche chapeau (24), et - une première couche de barrière à appau- - dans la deuxième région (28), un deuxiè- vrissement dopée (20) formée sur la pre- me renfoncement (34) qui est latéralement mière couche d’arrêt d’attaque (19), 25 espacé de la deuxième paire d’électrodes - une deuxième couche de barrière à ap- (30) et qui s’étend verticalement dans la pauvrissement non dopée (21) formée sur couche ohmique (26) et dans la troisième la première couche de barrière à appauvris- couche d’arrêt d’attaque (25) de manière à sement (20), exposer une deuxième surface supérieure - une deuxième couche d’arrêt d’attaque 30 de la deuxième couche chapeau (24) ; dopée (22) formée sur la deuxième couche de barrière à appauvrissement (21) et com- • former posée d’arséniure d’aluminium (AlAs), - une première couche chapeau (23) dopée - dans la première région (27), un troisième avec un agent de dopage du type n, formée 35 renfoncement (36*) qui est plus étroit que sur la deuxième couche d’arrêt d’attaque le premier renfoncement (33) et qui s’étend (22) et composée d’arséniure de gallium verticalement depuis le premier renfonce- (GaAs), ment (33) dans la deuxième couche cha- - une deuxième couche chapeau non dopée peau (24), la première couche chapeau (23) (24) formée sur la première couche cha- 40 et ladeuxième couche d’arrêt d’attaque(22) peau (23) et composée d’arséniure de gal- de manière à exposer une première surface lium (GaAs), supérieure de la deuxième couche de bar- - une troisième couche d’arrêt d’attaque rière à appauvrissement (21), (25) dopée avec un agent de dopage du ty- - dans la première région (27), un quatrième pe n, formée sur la deuxième couche cha- 45 renfoncement (38) qui est plus étroit que le peau (24) et composée d’arséniure d’alumi- troisième renfoncement (36*) et qui s’étend nium (AlAs) ; et verticalement depuis le troisième renfonce- - une couche ohmique (26) dopée avec un ment (36*)dans la deuxième couche de bar- agent de dopage du type n, formée sur la rière à appauvrissement (21), la première troisième couche d’arrêt d’attaque (25) et 50 couche de barrière à appauvrissement (20) composée d’arséniure de gallium (GaAs) ; et la première couche d’arrêt d’attaque (19) de manière à exposer une surface supé- • former une première paire d’électrodes (29) rieure de la couche barrière à enrichisse- d’un transistor à enrichissement sur ladite cou- ment (18) délimitant une première région de che ohmique (26), et en contact ohmique avec 55 contact Schottky, et celle-ci, dans une première région (27) de la - dans la deuxième région (28), un cinquiè- structure épitaxiale en couches et une deuxième me renfoncement (39) qui est plus étroit que paire d’électrodes (30) d’un transistor à appau- le deuxième renfoncement (34) et qui

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s’étend verticalement depuis le deuxième épitaxiale en couches, sur la première paire renfoncement (34) dans la deuxième cou- d’électrodes(29) et sur la deuxièmepaire d’élec- che chapeau (24), la première couche cha- trodes (30) de manière à exposer le troisième peau (23) et la deuxième couche d’arrêt renfoncement (36), une deuxième partie de la d’attaque (22) de manière à exposer une 5 première surface supérieure de la deuxième deuxième surface supérieure de la deuxiè- couche chapeau (24) s’étendant latéralement me couche de barrière à appauvrissement depuis ledit troisième renfoncement (36) et une (21) délimitantune deuxième région de con- première partie de la deuxième surface supé- tact Schottky ; et rieure de la deuxième couche chapeau (24) 10 audit deuxième procédé d’attaque. • former 9. Procédé selon la revendication 8, dans lequel la pre- - dans le quatrième renfoncement (38), une mière électrode de grille (41) et la deuxième électro- première électrode de grille (41 ; 43) du de de grille (42) sont formées au moyen d’un dépôt transistor à enrichissement en contact15 chimique en phase vapeur réalisé en utilisant le Schottky avec la surface supérieure de la deuxième masque (40). couche de barrière à enrichissement (18) délimitant la première région de contact 10. Procédé selon la revendication 8, dans lequel la pre- Schottky, ladite première électrode de grille mière électrode de grille (43) et la deuxième électro- (41 ;43) s’étendant verticalement depuis la- 20 de de grille (44) sont formées au moyen d’un dépôt dite première région de contact Schottky chimique en phase vapeur réalisé en utilisant un troi- dans les quatrième (38), troisième (36*) et sième masque (45) formé sur la structure épitaxiale premier (33) renfoncements de manière à en couches, sur la première paire d’électrodes (29) faire saillie depuis ledit premier renfonce- et sur la deuxième paire d’électrodes (30) de maniè- ment (33), et 25 re à exposer le quatrième renfoncement (38), le troi- - dans le cinquième renfoncement (39), une sième renfoncement élargi (36*), une troisième par- deuxième électrode de grille (42 ; 44) du tie de la première surface supérieure de la deuxième transistor à appauvrissement en contact couche chapeau (24) s’étendant latéralement de- Schottky avec la deuxième surface supé- puis ledit troisième renfoncement élargi (36*), le cin- rieure de la deuxième couche de barrière à 30 quième renfoncement (39) et une deuxième partie appauvrissement (21) délimitant la deuxiè- de la deuxième surface supérieure de la deuxième me région de contact Schottky, ladite couche chapeau (24) s’étendant latéralement de- deuxième électrode de grille (42 ; 44) puis ledit cinquième renfoncement (39) au dépôt chi- s’étendant verticalement depuis ladite mique en phase vapeur. deuxième région de contact Schottky dans 35 les cinquième (39) et deuxième (34) renfon- 11. Procédé selon l’une quelconque des revendications cements de manière à faire saillie depuis 7 à 10, dans lequel l’isolation électrique de la pre- ledit deuxième renfoncement (34). mière région (27) et de la deuxième région (28) com- prend la formation par implantation ionique : 8. Procédé selon la revendication 7, dans lequel la for- 40 mation du troisième renfoncement (36*), du quatriè- • d’une première barrière d’isolation électrique me renfoncement (38) et du cinquième renfonce- (31) entourant la première région (27) et s’éten- ment (39) consiste à : dant verticalement dans toutes les couches de la structure épitaxiale en couches ; et • former un troisième renfoncement (36) au45 • d’une deuxième barrière d’isolation électrique moyen d’un premier procédé d’attaque réalisé (32) entourant la deuxième région (28) et s’éten- en utilisant un premier masque (37) formé sur dant verticalement dans toutes les couches de la structure épitaxiale en couches, sur la pre- la structure épitaxiale en couches. mière paire d’électrodes (29) et sur la deuxième paire d’électrodes (30) de manière à exposer 50 une première partie de la première surface su- périeure de la deuxième couche chapeau (24) audit premier procédé d’attaque ; et • élargir ledit troisième renfoncement (36) et for- mer le quatrième renfoncement (38) et le cin- 55 quième renfoncement (39) au moyen d’un deuxième procédé d’attaque réalisé en utilisant un deuxième masque (40) formé sur la structure

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• US 20060027840 A [0006] [0007] • US 6670652 B [0006] [0007] • US 20060208279 A [0006] [0007] • US 6703638 B [0006] [0007] • EP 0371686 A [0006] [0007] • US 7361536 B [0006] [0007]

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