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Intel 815 Chipset Family: 82815 Graphics and Memory Controller

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Intel 815 Chipset Family: 82815 Graphics and Memory Controller R Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) Datasheet June 2000 Document Reference Number: 290688-001 82815 GMCH R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 815 chipset GMCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 *Third-party brands and names are the property of their respective owners. Copyright © Intel Corporation 2000 2 Datasheet 82815 GMCH R Contents 1. Overview.....................................................................................................................................13 1.1. Related Documents .......................................................................................................13 1.2. The Intel 815 Chipset Family........................................................................................14 1.3. 82815 GMCH Overview .................................................................................................16 1.4. Host Interface.................................................................................................................17 1.5. System Memory Interface ..............................................................................................17 1.6. Multiplexed AGP and Display Cache Interface ..............................................................18 1.6.1. AGP Interface ..............................................................................................18 1.6.2. Display Cache Interface...............................................................................18 1.7. Hub Interface..................................................................................................................18 1.8. 82815 GMCH Integrated Graphics Support...................................................................19 1.8.1. Display, Digital Video Out, and LCD/Flat Panel/Digital CRT........................19 1.9. System Clocking ............................................................................................................20 1.10. GMCH Power Delivery ...................................................................................................20 2. Signal Description.......................................................................................................................21 2.1. Host Interface Signals....................................................................................................22 2.2. System Memory Interface Signals .................................................................................23 2.3. AGP Interface Signals....................................................................................................24 2.3.1. AGP Addressing Signals..............................................................................24 2.3.2. AGP Flow Control Signals............................................................................25 2.3.3. AGP Status Signals .....................................................................................25 2.3.4. AGP Clocking Signals (Strobes)..................................................................26 2.3.5. AGP FRAME# Signals .................................................................................27 2.4. Display Cache Interface Signals ....................................................................................29 2.5. Hub Interface Signals.....................................................................................................30 2.6. Display Interface Signals................................................................................................30 2.7. Digital Video Output Signals/TV-Out Pins......................................................................31 2.8. Power Signals................................................................................................................32 2.9. Clock Signals.................................................................................................................32 2.10. GMCH Power-Up/Reset Strap Options..........................................................................33 2.11. Multiplexed Display Cache and AGP Signal Mapping....................................................34 2.11.1. Display Cache Mapping at the AGP Connector...........................................35 3. Configuration Registers ..............................................................................................................37 3.1. Register Nomenclature and Access Attributes ..............................................................37 3.2. PCI Configuration Space Access...................................................................................38 3.2.1. PCI Bus Configuration Mechanism ..............................................................38 3.2.2. Logical PCI Bus #0 Configuration Mechanism.............................................39 3.2.3. Primary PCI (PCI0) and Downstream Configuration Mechanism ................39 3.2.4. Internal Graphics Device Configuration Mechanism....................................39 3.2.5. GMCH Register Introduction........................................................................39 3.3. I/O Mapped Registers ....................................................................................................40 3.3.1. CONF_ADDRConfiguration Address Register.........................................40 3.3.2. CONF_DATAConfiguration Data Register ...............................................41 Datasheet 3 82815 GMCH R 3.4. Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) ................... 42 3.4.1. VID—Vendor Identification Register (Device 0) .......................................... 44 3.4.2. DID—Device Identification Register (Device 0)........................................... 44 3.4.3. PCICMD—PCI Command Register (Device 0) ........................................... 45 3.4.4. PCISTS—PCI Status Register (Device 0)................................................... 46 3.4.5. RID—Revision Identification Register (Device 0)........................................ 47 3.4.6. SUBC—Sub-Class Code Register (Device 0)............................................. 47 3.4.7. BCC—Base Class Code Register (Device 0).............................................. 47 3.4.8. MLT—Master Latency Timer Register (Device 0)....................................... 48 3.4.9. HDR—Header Type Register (Device 0)..................................................... 48 3.4.10. APBASE—Aperture Base Configuration Register (Device 0: AGP Mode Only) .................................................................................................. 48 3.4.11. SVID—Subsystem Vendor Identification Register (Device 0) ..................... 50 3.4.12. SID—Subsystem Identification Register (Device 0) .................................... 50 3.4.13. CAPPTR—Capabilities Pointer (Device 0).................................................. 50 3.4.14. GMCHCFG—GMCH Configuration Register (Device 0)............................. 51 3.4.15. APCONT—Aperture Control (Device 0) ...................................................... 53 3.4.16. DRP—DRAM Row Population Register (Device 0)..................................... 54 3.4.17. DRAMT—DRAM Timing Register (Device 0).............................................. 55 3.4.18. DRP2—DRAM Row Population Register 2 (Device 0)................................ 56 3.4.19. FDHC—Fixed DRAM Hole Control Register (Device 0).............................. 57 3.4.20. PAM—Programmable Attributes Map Registers (Device 0)........................ 57 3.4.21. SMRAM—System Management RAM Control Register (Device 0) ........... 62 3.4.22. MISCC—Miscellaneous Control Register (Device 0) .................................
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