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Matrox MGA-1064SG Developer Specification

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Matrox MGA-1064SG Developer Specification Matrox Graphics Inc. Matrox MGA-1064SG Developer Specification Document Number 10524-MS-0100 February 10, 1997 Trademark Acknowledgements MGA,™ MGA-1064SG,™ MGA-1164SG,™ MGA-2064W,™ MGA-2164W,™ MGA-VC064SFB,™ MGA-VC164SFB,™ MGA Marvel,™ MGA Millennium,™ MGA Mystique,™ MGA Rainbow Run- ner,™ MGA DynaView,™ PixelTOUCH,™ MGA Control Panel,™ and Instant ModeSWITCH,™ are trademarks of Matrox Graphics Inc. Matrox® is a registered trademark of Matrox Electronic Systems Ltd. VGA,® is a registered trademark of International Business Machines Corporation; Micro Channel™ is a trademark of International Business Machines Corporation. Intel® is a registered trademark, and 386,™ 486,™ Pentium,™ and 80387™ are trademarks of Intel Corporation. Windows™ is a trademark of Microsoft Corporation; Microsoft,® and MS-DOS® are registered trade- marks of Microsoft Corporation. AutoCAD® is a registered trademark of Autodesk Inc. Unix™ is a trademark of AT&T Bell Laboratories. X-Windows™ is a trademark of the Massachusetts Institute of Technology. AMD™ is a trademark of Advanced Micro Devices. Atmel® is a registered trademark of Atmel Corpora- tion. Catalyst™ is a trademark of Catalyst Semiconductor Inc. SGS™ is a trademark of SGS-Thompson. Toshiba™ is a trademark of Toshiba Corporation. Texas Instruments™ is a trademark of Texas Instru- ments. National™ is a trademark of National Semiconductor Corporation. Microchip™ is a trademark of Microchip Technology Inc. All other nationally and internationally recognized trademarks and tradenames are hereby acknowledged. This document contains confidential proprietary information that may not be disclosed without written permission from Matrox Graphics Inc. © Copyright Matrox Graphics Inc., 1997. All rights reserved. Disclaimer: Matrox Graphics Inc. reserves the right to make changes to specifications at any time and without notice. The information provided by this document is believed to be accurate and reliable. How- ever, no responsibility is assumed by Matrox Graphics Inc. for its use; nor for any infringements of pat- ents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Matrox Graphics Inc. or Matrox Electronic Systems Ltd. Contents Chapter 1: MGA Overview 1.1 Introduction. 1-2 1.2 System Block Diagram . 1-3 1.3 Application Areas . 1-3 1.4 Typical Implementation. 1-3 1.4.1 Target Markets . 1-3 1.5 Features . 1-4 1.5.1 Core GUI Accelerator . 1-4 1.5.2 3D Texture Mapping Engine . 1-4 1.5.3 Digital Video Engine . 1-5 1.5.4 DirectDraw Support. 1-5 1.5.5 Direct 3D Support . 1-5 1.5.6 Integrated DAC . 1-6 1.5.7 Synchronous Memory Interface . 1-6 1.5.8 Miscellaneous . 1-6 1.6 Typographical Conventions Used. 1-7 1.7 Locating Information. 1-7 Chapter 2: MGA-1064SG Overview 2.1 Introduction. 2-2 2.2 PCI Bus interface . 2-2 2.3 VGA Graphics Controller . 2-2 2.4 VGA Attributes Controller . 2-2 2.5 CRTC . 2-2 2.6 Video Interface . 2-2 2.7 Address Processing Unit (APU) . 2-4 2.8 Data Processing Unit (DPU). 2-4 2.9 Texture Mapper . 2-4 2.10 Memory Controller . 2-4 Chapter 3: Resource Mapping 3.1 Memory Mapping . 3-2 3.1.1 Configuration Space Mapping. 3-2 3.1.2 MGA General Map . 3-3 3.1.3 MGA Control Aperture . 3-4 3.2 Register Mapping . 3-5 Chapter 4: Register Descriptions 4.1 Power Graphic Mode Register Descriptions. 4-2 4.1.1 Power Graphic Mode Configuration Space Registers . 4-2 Contents 1 4.1.2 Power Graphic Mode Memory Space Registers . .4-19 4.2 VGA Mode Registers . 4-85 4.2.1 VGA Mode Register Descriptions . .4-85 4.3 DAC Registers . 4-159 4.3.1 DAC Register Descriptions . .4-159 Chapter 5: Programmer’s Specification 5.1 PCI Interface . 5-2 5.1.1 Introduction . .5-2 5.1.2 PCI Retry Handling . .5-3 5.1.3 PCI Burst Support . .5-3 5.1.4 PCI Target-Abort Generation. .5-4 5.1.5 Transaction Ordering. .5-4 5.1.6 Direct Access Read Cache . .5-4 5.1.7 Big Endian Support . .5-5 5.1.8 Host Pixel Format . .5-8 5.2 Memory Interface . 5-14 5.2.1 Frame Buffer Organization . .5-14 5.2.2 Pixel Format. .5-18 5.3 Chip Configuration and Initialization . 5-19 5.3.1 Reset . .5-19 5.3.2 Operations After Hard Reset . .5-20 5.3.3 Power Up Sequence . .5-20 5.3.4 Operation Mode Selection . .5-22 5.4 Direct Frame Buffer Access . 5-24 5.5 Drawing in Power Graphic Mode . 5-25 5.5.1 Drawing Register Initialization Using General Purpose Pseudo-DMA5-25 5.5.2 Overview . .5-26 5.5.3 Global Initialization (All Operations). .5-27 5.5.4 Line Programming . .5-28 5.5.5 Trapezoid / Rectangle Fill Programming . .5-33 5.5.6 Bitblt Programming . .5-40 5.5.7 ILOAD Programming . .5-46 5.5.8 Scaling Operations . .5-51 5.5.9 IDUMP Programming. .5-60 5.6 CRTC Programming . 5-62 5.6.1 Horizontal Timing. .5-62 5.6.2 Vertical Timing. .5-63 5.6.3 Memory Address Counter . .5-64 5.6.4 Programming in VGA Mode. .5-65 5.6.5 Programming in Power Graphic Mode. .5-66 Contents 2 5.7 Video Interface . 5-70 5.7.1 Operation Modes . 5-70 5.7.2 Palette RAM (LUT) . 5-73 5.7.3 Hardware Cursor. 5-73 5.7.4 Keying Functions . 5-74 5.7.5 Zooming . ..
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