DOCSLIB.ORG

US5103499.Pdf

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
US5103499.Pdf |||||||||||||| US005103499A United States Patent (19) 11) Patent Number: 5,103,499 Miner et al. 45 Date of Patent: Apr. 7, 1992 54 BEAM SYNCHRONIZED COPROCESSOR 4,180,805 12/1979 Burson ................................ 340/709 4,243,984 1/1981 Ackley et al. ....................... 340/703 (75) Inventors: Jay G. Miner, Mtn. View; Dave 4,420,770 2/1983 Rahman .......... ... 358/183 Dean, Ukiah; Joseph C. Decuir, 4,572,506 2/1986 DiOrio ........ 364/521 X Albany; Ronald H. Nicholson, 4,777,621 10/1988 Miner et al. ......................... 364/900 Sunnyvale; Akio Tanaka, 4,809, 169 2/1989 Sfavti et al. ......................... 364/200 Burlingame, all of Calif. Primary Examiner-Heather R. Herndon (73) Assignee: Commodore-Amiga, Inc., Los Gatos, Attorney, Agent, or Firm-Finnegan, Henderson, Calif. Farabow, Garrett & Dunner (21) Appl. No.: 422,022 (57) ABSTRACT Filed: Oct. 16, 1989 A computer that provides data to a video display using (22) a bitmap display memory organization and bitplane Related U.S. Application Data addressing. Separate control is provided for two bit plane backgrounds and for eight reusable and easily 62) Division of Ser. No. 886,796, Jul. 18, 1986, Pat. No. movable sprites. Additional logic allows for dynamical 4,874,164. ly-controllable interobject priority and collision detec (51) Int. Cl. .............................................. G06F 3/153 tion among data in each of the bitplane backgrounds (52) U.S. C. ..................................... 395/162; 340/750 and sprites. A coprocessor provides for video beam 58) Field of Search ....................... 364/518, 521, 522; synchronized changes to data in registers, freeing the 340/721, 723, 748-750; 273/1 E, DIG. 28; main processor for general purpose computing tasks. A 358/22 block image transferer is provided to rapidly copy data (56) References Cited in large blocks from one memory location to another. In U.S. PATENT DOCUMENTS hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane 3,996,585 12/1976 Hogan et al................. 340/324 AD 4,034,983 7/1977 Dash et al. ........................ 373/85 R data modifies those values, allowing for simultaneous 4,053,740 10/1977 Rosenthal ........................... 364/705 display of a greatly increased number of colors. 4,070,710 1/1978 Sukonick et al. ................... 364/900 4,177,462 12/1979 Chung................................. 340/703 34 Claims, 11 Drawing Sheets AABS EEn TESA) E) NNRO U.S. Patent Apr. 7, 1992 Sheet 2 of 11 5,103,499 A/6 2. DATABUS (BLTTER CONTROL) SELECT BITS (8) n FILL CARRY IN FLLENABLE STORE TO DESTINATION DATABUS U.S. Patent Apr. 7, 1992 Sheet 3 of 11 5,103,499 A/6 t. SPRITE VER. POSITION 39 COMPARATOR SYNCH LIGHT PEN VIDEO BEAM CTR. 404 DMA CONTROL ----- J REGISTER ADDRESS - -27 29 f DECODER wentarams GATE NHBT SIGNAL is AUDIO 2 BT BIT MAP PLANE COPROCESSOR 33 U.S. Patent Apr. 7, 1992 Sheet 4 of 11 5,103,499 |||| WW0 31}}}dS 8BITMOHINO0 OZIJ!!! JAWAWOO(-69 ----–—-1------ \----- º9/3/ (9)S18WIW0____j------------; U.S. Patent 5,103,499 Z39/3/ ">?HIM,62 çLI»THWNE U.S. Patent Apr. 7, 1992 Sheet 6 of 11 5,103,499 (TWWU)ISH/1038WW0 (H80)(NWW30S/18 U.S. Patent Apr. 7, 1992 Sheet 8 of 11 5,103,499 ÇǺ O/39/-/ (](9)118[)SI?3Nºld U.S. Patent 5,103,499 (91)03}} U.S. Patent Apr. 7, 1992 Sheet 10 of 11 5,103,499 A/6 A. COLLISION DETECTION LOGC 335 SPRUs III| | H.| | | -DOH 372 || || BIT PLANE BUS 333 -DOH 372 O 372 : H5OH 373 353 6 BTS-LINES 373A COLLISION 375 ---L-- E-iREG. (6) 5 CSIONSTRAGE 5 O BES || |||st DC (6) U.S. Patent Apr. 7, 1992 Sheet 11 of 11 5,103,499 g 53 N S. UM) CO No No S. ZY 1 N (NZY/N r N rf s D 2 - 2 asse a as Caa 3 5,103,499 1. 2 Motorola Inc. 68000 and a 6502. In this system, the first BEAM SYNCHRONIZED COPROCESSOR processor is dedicated to computational operations and the second microprocessor is dedicated to video display This is a division of application Ser. No. 06/886,796, information retrieval. filed July 18, 1986, now U.S. Pat. No. 4,874,164. Other early game circuits, such as Dash et al., U.S. Pat. No. 4,034,983 utilized special purpose control cir BACKGROUND OF THE INVENTION cuits to generate signals to the antenna connection of a This invention relates to the field of microprocessor commercial color television receiver. Such a special powered computers for video games and personal com purpose control circuit could include analog interface puters, incorporating DMA techniques, especially such 10 circuits for processing gamepaddle paddle signals and systems which are implemented in MOS (metal oxide decoding functions, and sync pulse generation could be semiconductor) LSI (large scale integrated) circuitry used to generate horizontal sync and raster scan infor where circuit area is a consideration. The invention nation. further relates to enhanced systems where auxiliary Personal computer and microprocessor driven sys circuitry has been added to the host system; where a 15 tems, such as Chung, U.S. Pat. No. 4,177,462, have used televisiontype display device is used; and where bitmap display generator circuitry driven off of an address bus, mode (at least one bit of video information is stored in data bus and control bus, including raster line genera memory for every element location (pixel) of the pic tion and vertical position counters. ture displayed) is likewise incorporated. Likewise, Sukonick et al., U.S. Pat. No. 4,070,710 The invention also relates to video display drives for 20 incorporates video control circuits and raster memory color video display monitors where color sprites access into a system with data and address bus architec (which are sometimes called background) are operated ture. Sukonicket al. uses a video control circuit which in unison. relies upon a plurality of vertical and horizontal posi Bit mapping, while space and time implementation tion registers, a skip pattern memory and modulo com consuming, has proven to be a straightforward and an 25 parison circuitry for "FIFO" processing of video infor accurate method for video display generation. Complex mation. displays provided by video games and personal comput Sukonick, U.S. Pat. No. 4,070,710, shows a two pro ers require overlay presentations of movable and/or cessor system. Sukonick has added a display system 16 changeable information and offixed information; and of to programmed host computer 10. This video display collisions between movable objects. Bit map implemen 30 system 16 contains an Intel Corporation 8088 micro tation has been the focus of various prior circuits. processor 76 within the micro-control unit 22 of the Prior video game circuits have provided a complex video display system. display format to a television receiver display unit (a Along this line Burson, U.S. Pat. No. 4,180,805, has cathode ray tube), which display unit generates the provided a video display circuit which incorporates a presentation with a plurality of horizontal scans or ras 35 general purpose microprocessor 15, the TMS 1100 mi ter lines. A video game circuit which is capable of dis crocomputer. A character memory is provided separate playing fixed objects as background, as well as moving from a display memory and character generator mem objects, is shown by Rosenthal, U.S. Pat. No. 4,053,740. ory. Each display memory word is partitioned into two Rosenthal has built a special purpose digital computer bytes, with the first of byte being a character memory to generate video game information from a plurality of 40 address and the second being a sub-address to locate a selected, on a mutually exclusive basis, software defined character-word within a set of character words in mem programs. Operator commands are separated into an ory. Each character memory word is likewise parti independent computational section and an independent tioned into two bytes with the first byte determining display section of the circuit for processing. Rosenthal, color and the second byte selecting a particular charac U.S. Pat. No. 4,053,740, utilized arithmetic logic units to 45 ter from a prestored set. drive accumulators to control x and y registers and The use of a second general purpose commercially associated horizontal and vertical beam direction drive available microcomputer to process video display infor circuits for cathode ray tube displays. mation, while increasing the system speed, also in Personal computers, such as the Apple Computer, creases the cost of manufacture for the system, as well have utilized a main microprocessor to perform compu 50 as, the size of the system, i.e., chip "real estate.” tational operations and to process (retrieve) video dis A micro-control unit is also used and is necessary to play information to generate displays to a television the circuitry. The micro-control unit decodes instruc type receiver. tions from a host computer for use by the raster memory The Appie Computer has incorporated a general unit and generates (encodes) control information to purpose microprocessor, the MOS Technology Inc. 55 cause the raster memory to write display information, as Model 6502, to perform both computational operations well as to control the video control circuit to read infor and video display information retrieval. Such a single mation from the raster memory and to translate it into microprocessor driven system has speed limitations, as video signals usable by a CRT drive circuit. Ackley et most microprocessors, including the Model 6502, have al., U.S. Pat. No. 4,243,984, show a video display pro significant processing dead time used for refreshing cessor including general circuit components for overlay registers and resetting and initializing operations.
Load more

Recommended publications
  • Release Notes for X11R6.8.2 the X.Orgfoundation the Xfree86 Project, Inc
    Release Notes for X11R6.8.2 The X.OrgFoundation The XFree86 Project, Inc. 9February 2005 Abstract These release notes contains information about features and their status in the X.Org Foundation X11R6.8.2 release. It is based on the XFree86 4.4RC2 RELNOTES docu- ment published by The XFree86™ Project, Inc. Thereare significant updates and dif- ferences in the X.Orgrelease as noted below. 1. Introduction to the X11R6.8.2 Release The release numbering is based on the original MIT X numbering system. X11refers to the ver- sion of the network protocol that the X Window system is based on: Version 11was first released in 1988 and has been stable for 15 years, with only upwardcompatible additions to the coreX protocol, a recordofstability envied in computing. Formal releases of X started with X version 9 from MIT;the first commercial X products werebased on X version 10. The MIT X Consortium and its successors, the X Consortium, the Open Group X Project Team, and the X.OrgGroup released versions X11R3 through X11R6.6, beforethe founding of the X.OrgFoundation. Therewill be futuremaintenance releases in the X11R6.8.x series. However,efforts arewell underway to split the X distribution into its modular components to allow for easier maintenance and independent updates. We expect a transitional period while both X11R6.8 releases arebeing fielded and the modular release completed and deployed while both will be available as different consumers of X technology have different constraints on deployment. Wehave not yet decided how the modular X releases will be numbered. We encourage you to submit bug fixes and enhancements to bugzilla.freedesktop.orgusing the xorgproduct, and discussions on this server take place on <[email protected]>.
    [Show full text]
  • Matrox MGA-1064SG Developer Specification
    Matrox Graphics Inc. Matrox MGA-1064SG Developer Specification Document Number 10524-MS-0100 February 10, 1997 Trademark Acknowledgements MGA,™ MGA-1064SG,™ MGA-1164SG,™ MGA-2064W,™ MGA-2164W,™ MGA-VC064SFB,™ MGA-VC164SFB,™ MGA Marvel,™ MGA Millennium,™ MGA Mystique,™ MGA Rainbow Run- ner,™ MGA DynaView,™ PixelTOUCH,™ MGA Control Panel,™ and Instant ModeSWITCH,™ are trademarks of Matrox Graphics Inc. Matrox® is a registered trademark of Matrox Electronic Systems Ltd. VGA,® is a registered trademark of International Business Machines Corporation; Micro Channel™ is a trademark of International Business Machines Corporation. Intel® is a registered trademark, and 386,™ 486,™ Pentium,™ and 80387™ are trademarks of Intel Corporation. Windows™ is a trademark of Microsoft Corporation; Microsoft,® and MS-DOS® are registered trade- marks of Microsoft Corporation. AutoCAD® is a registered trademark of Autodesk Inc. Unix™ is a trademark of AT&T Bell Laboratories. X-Windows™ is a trademark of the Massachusetts Institute of Technology. AMD™ is a trademark of Advanced Micro Devices. Atmel® is a registered trademark of Atmel Corpora- tion. Catalyst™ is a trademark of Catalyst Semiconductor Inc. SGS™ is a trademark of SGS-Thompson. Toshiba™ is a trademark of Toshiba Corporation. Texas Instruments™ is a trademark of Texas Instru- ments. National™ is a trademark of National Semiconductor Corporation. Microchip™ is a trademark of Microchip Technology Inc. All other nationally and internationally recognized trademarks and tradenames are hereby acknowledged. This document contains confidential proprietary information that may not be disclosed without written permission from Matrox Graphics Inc. © Copyright Matrox Graphics Inc., 1997. All rights reserved. Disclaimer: Matrox Graphics Inc. reserves the right to make changes to specifications at any time and without notice.
    [Show full text]
  • Matrox MGA-2164W Developer's Specification
    Matrox Graphics Inc. Matrox MGA-2164W Developer’s Specification Document Number 10568-XX-0100 August 18, 1997 Trademark Acknowledgements MGA,™ MGA-1064SG,™ MGA-1164SG,™ MGA-2064W,™ MGA-2164W,™ MGA-VC064SFB,™ MGA-VC164SFB,™ MGA Marvel,™ MGA Millennium,™ MGA Mystique,™ MGA Rainbow Run- ner,™ MGA DynaView,™ PixelTOUCH,™ MGA Control Panel,™ and Instant ModeSWITCH,™ are trademarks of Matrox Graphics Inc. Matrox® is a registered trademark of Matrox Electronic Systems Ltd. VGA,® is a registered trademark of International Business Machines Corporation; Micro Channel™ is a trademark of International Business Machines Corporation. Intel® is a registered trademark, and 386,™ 486,™ Pentium,™ and 80387™ are trademarks of Intel Corporation. Windows™ is a trademark of Microsoft Corporation; Microsoft,® and MS-DOS® are registered trade- marks of Microsoft Corporation. AutoCAD® is a registered trademark of Autodesk Inc. Unix™ is a trademark of AT&T Bell Laboratories. X-Windows™ is a trademark of the Massachusetts Institute of Technology. AMD™ is a trademark of Advanced Micro Devices. Atmel® is a registered trademark of Atmel Corpora- tion. Catalyst™ is a trademark of Catalyst Semiconductor Inc. SGS™ is a trademark of SGS-Thompson. Toshiba™ is a trademark of Toshiba Corporation. Texas Instruments™ is a trademark of Texas Instru- ments. National™ is a trademark of National Semiconductor Corporation. Microchip™ is a trademark of Microchip Technology Inc. All other nationally and internationally recognized trademarks and tradenames are hereby acknowledged. This document contains confidential proprietary information that may not be disclosed without written permission from Matrox Graphics Inc. © Copyright Matrox Graphics Inc., 1997. All rights reserved. Disclaimer: Matrox Graphics Inc. reserves the right to make changes to specifications at any time and without notice.
    [Show full text]
  • Intel 815EM Chipset: 82815EM Graphics and Memory Controller
    查询82815E供应商 捷多邦，专业PCB打样工厂，24小时加急出货 R Intel® 815EM Chipset: 82815EM Graphics and Memory Controller Hub (GMCH2-M) Datasheet October 2000 Document Reference Number: 290689-001 Intel® 82815EM GMCH R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 815EM chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
    [Show full text]
  • Performance Analysis of Intel Gen9.5 Integrated GPU Architecture
    Performance Analysis of Intel Gen9.5 Integrated GPU Architecture Helder Francisco Pereira Duarte Thesis to obtain the Master of Science Degree in Electrical and Computer Engineering Supervisor(s): Doctor Aleksandar Ilic Examination Committee Chairperson: Doctor António Manuel Raminhos Cordeiro Grilo Supervisor: Doctor Aleksandar Ilic Member of the Committee: Doctor Ricardo Jorge Fernandes Chaves June 2018 Declaration I declare that this document is an original work of my own authorship and that it fulfills all the require- ments of the Code of Conduct and Good Practices of the Universidade de Lisboa. Acknowledgments I would like to thank my family and friends, whose support was paramount to the completion of this thesis, and to INESC-ID Lisboa, for providing the facilities in which this thesis was developed. In particular I would like to thank Diogo Marques for his tips that helped drive my research forward and, of course, to Prof. Aleksander for his incredible patience in dealing with me. i ii Resumo Recentemente os CPUs vemˆ equipados com placas graficas´ integradas. Este acoplamento tem o potencial de oferecer ganhos de desempenho consideraveis´ caso as ditas GPUs sejam usadas como aceleradores. No entanto, placas graficas´ integradas temˆ dificuldade em atingir os n´ıveis de desem- penho que placas discretas proporcionam devido ao menor numero´ de nucleos.´ Contudo, a sua prox- imidade com o CPU significa uma partilha de dados com menos sobrecargas associadas. Ademais, as vantagens de partilhar a hierarquia de memoria´ com o processador e o consumo de energia mais baixo que as placas discretas a` custa de desempenho permite atingir n´ıveis de eficienciaˆ energetica´ mais elevados.
    [Show full text]
  • Fire GL1 User's Guide
    User's Guide DISCLAIMER The manufacturer (MFR) reserves the right to make changes to this document and the products which it describes without notice. The MFR shall not be liable for technical or editorial errors or omissions made herein; not for incidental or consequential damages resulting from the furnishing, performance, or use of this material. The MFR makes no representation that the interconnection of products in the manner described herein will not infringe on existing or future patent rights, nor do the descriptions contained herein imply the granting of license to make, use or sell equipment constructed in accordance with this description. The PCI accelerators have been designed to support the PCI local bus standards. Some computers use proprietary local bus circuitry and therefore may not be fully compatible with the MFR’s local bus cards. Although tested successfully in a wide variety of computer systems, the MFR cannot be held responsible for any incompatibilities which may occur between this card and the system configuration you plan to use. We recommend that you check with the dealer or distributor for your computer system before installing your card. © Copyright 1999 Fire GL Graphics. All rights reserved 2 Table of Contents 1ABOUT FIRE GL1................................................... 5 HARDWARE FEATURES............................................................6 SOFTWARE FEATURES .............................................................6 PROFESSIONAL 3D RENDERING ............................................7
    [Show full text]
  • Datasheet – Volume 1 of 2
    Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet – Volume 1 of 2 Supporting 4th Generation Intel® Core™ processor based on Mobile M-Processor and H-Processor Lines Supporting Mobile Intel® Pentium® Processor and Mobile Intel® Celeron® Processor Families July 2014 Order No.: 328901-007 By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD
    [Show full text]
  • United States Patent (19) 11 Patent Number: 6,011,546 Bertram (45) Date of Patent: *Jan
    US00601-1546A United States Patent (19) 11 Patent Number: 6,011,546 Bertram (45) Date of Patent: *Jan. 4, 2000 54 PROGRAMMING STRUCTURE FOR USER 58 Field of Search ..................................... 345/326, 327, INTERFACES 345/339, 352, 353, 354; 348/6, 10, 734, 725, 601,906, 473, 563-565, 589, 584, 75 Inventor: Randal Lee Bertram, Raleigh, N.C. 586, 588; 455/3.1, 4.1, 4.2, 6.1, 6.2 73 Assignee: International Business Machines 56) References Cited Corporation, Armonk, N.Y. U.S. PATENT DOCUMENTS * Notice: This patent is Subject to a terminal dis- 5,422,674 6/1995 Hooper et al. .............................. 34.8/6 claimer. 5,539,479 7/1996 Bertram .................................. 34.8/564 5,548,340 8/1996 Bertram .................................. 34.8/559 5,657,091 8/1997 Bertram .................................. 34.8/559 21 Appl. No.: 08/937,056 5,801,941 9/1998 Bertram .................................. 364/188 22 Filed: Sep. 24, 1997 Primary Examiner-John W. Miller Attorney, Agent, or Firm-Daniel E. McConnell; Bernard Related U.S. Application Data D. Bogdon 63 Continuation-in-part of application No. 08/700,606, Aug. 57 ABSTRACT application12, 1996, Pat. No. No. 08/899,038, 5,801.941, andJul. a 23,continuation-in-part 1997, abandoned, of E. Stored E. t asSociated with irrn which is a continuation of application No. 08/551,620, Nov. COntrollerS contro Ing a display to a user are constructe 1, 1995, Pat. No. 5,657,091. a language which uses layered Statements, each of which can 7 have a description portion,s an action portion,s and a unique 51 Int.
    [Show full text]
  • Apov Issue 4 Regulars
    issue 4 - june 2010 - an abime.net publication the amiga dedicated to amIga poInt of vIew AMIGA reviews w news tips w charts apov issue 4 regulars 8 editorial 10 news 14 who are we? 116 charts 117 letters 119 the back page reviews 16 leander 18 dragon's breath 22 star trek: 25th anniversary 26 operation wolf 28 cabal 30 cavitas 32 pinball fantasies 36 akira 38 the king of chicago ap o 40 wwf wrestlemania v 4 42 pd games 44 round up 5 features 50 in your face The first person shooter may not be the first genre that comes to mind when you think of the Amiga, but it's seen plenty of them. Read about every last one in gory detail. “A superimposed map is very useful to give an overview of the levels.” 68 emulation station There are literally thousands of games for the Amiga. Not enough for you? Then fire up an emulator and choose from games for loads of other systems. Wise guy. “More control options than you could shake a joypad at and a large number of memory mappers.” 78 sensi and sensibility Best football game for the Amiga? We'd say so. Read our guide to the myriad versions of Sensi. “The Beckhams had long lived in their estate, in the opulence which their eminence afforded them.” wham into the eagles nest 103 If you're going to storm a castle full of Nazis you're going to need a plan. colorado 110 Up a creek without a paddle? Read these tips and it'll be smooth sailing.
    [Show full text]
  • Introducing the X68000: Japan's 16-Bit Beast
    Introducing the X68000: Japan’s 16-Bit Beast Ford Seidel Japanese Home Computers Circa 1987 Unlike today where nearly all machines are boring x86 boxes, there were several wildly different options back then - MSX - NEC PC-88 and PC-98 - IBM PC Compatibles - Fujitsu FM series - Sharp X1 - Sega SC-3000 - Way too many to list here MSX: Dominant Japanese Computer Standard - Created by Microsoft in 1983 in an attempt to standardize the PC market - Manufacturers would implement their own machine within the MSX standard - Z80 CPU at 3.58MHz - also sold in Europe and the Middle East - In 1987, current standard was MSX2/2+ - >= 64KB main RAM - >= 128KB VRAM - AY-3-8910/YM2149 sound chip - 3 square waves and a noise generator - 512 color palette - 256 colors at 256x212 or 16 colors at 512x512 MSX2 Graphics - Hardware only supports vertical scrolling - To avoid this, games were often restricted to 1 screen Nemesis 2: a Fairly Standard MSX2 game https://www.youtube.com/watch?v=ZfZf8XpF7_o Good Scrolling (REALLY hard to do) https://www.youtube.com/watch?v=gcZJ64PgtgA Sharp X1 - Not super popular, but also not unpopular by any means - Technically inferior to MSX2 - Z80 CPU at 4MHz - 8 colors - 320x200 or 640x200 resolution - AY-3-8910/YM2149 sound chip - Optional YM2151 FM synth soundchip X1 Twin - Contains an X1 and a PC Engine/TurboGrafx-16 - Inspired X68000’s design Space Harrier on X1 https://youtu.be/RUad5VrOQsY?t=47s The Sharp X68000 - Sharp realized that there was space in the high end market not occupied by MSX - Aimed to design machine vastly
    [Show full text]
  • Intel740™ Graphics Accelerator
    Intel740™ Graphics Accelerator Software Developer’s Manual September 1998 Order Number: 290617-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: http://www.intel.com or call 1-800-548-4725 Copyright © Intel Corporation, 1997-1998 *Third-party brands and names are the property of their respective owners.
    [Show full text]
  • Memory System Optimizations for CPU-GPU Heterogeneous Chip-Multiprocessors
    Memory System Optimizations for CPU-GPU Heterogeneous Chip-multiprocessors A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Siddharth Rai to the DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR, INDIA July, 2018 Synopsis Recent commercial chip-multiprocessors (CMPs) have integrated CPU as well as GPU cores on the same chip [42, 43, 44, 93]. In today's designs, these cores typically share parts of the memory system resources between the applications executing on the two types of cores. However, since the CPU and the GPU cores execute very different workloads leading to very different resource requirements, designing intelligent protocols for sharing resources between them such that both CPU and GPU gain in performance brings forth new challenges to the design space of these heterogeneous processors. In this dissertation, we explore solutions to dynamically allocate last-level cache (LLC) capacity and DRAM bandwidth to the CPU and GPU cores in a design where both the CPU and the GPU share the large on- die LLC, DRAM controllers, DRAM channels, DRAM ranks, and DRAM device resources (banks, rows). CPU and GPU differ vastly in their execution models, workload characteristics, and performance requirements. On one hand, a CPU core executes instructions of a latency-sensitive and/or moderately bandwidth-sensitive job progressively in a pipeline generating memory accesses (for instruction and data) only in a few pipeline stages (instruction fetch and data memory access stages). On the other hand, GPU can access different data streams having different semantic meanings and disparate access patterns throughout the rendering pipeline.
    [Show full text]