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Checking Using the Tms34010 AN INVESTIGATION OF INTEGRATED CIRCUIT HARDWARE DESIGN RULE CHECKING USING THE TMS34010 A Thesis Submitted to the Faculty of Graduate Studies and Research in Partial Fulfillment of the Requirements for the Degree of Master of Science in the Department of Electrical Engineering University of Saskatchewan Saskatoon by Amy Sze Ming Lau August, 1990 The author claims copyright. Use shall not be made of the material mnp(, herein without proper acknowledgement, as indicated on the following page. Copyright The author has agreed that the Library, University of Saskatchewan, maYI ake this thesis freely available for inspection. Moreover, the author hasl greed that permission for extensive copying of this thesis for scholarly urposes may be granted by the professor or professors who supervised the esis work recorded herein or, in their absence, by the Head of the epartment or the Dean of the in which the thesis work was done. It College I s understand that due recognition will be given to the author of this thesis. opying or publication or any other use of the thesis for fmancial gain without pproval by the University of Saskatchewan and the author's written permission s prohibited. Requests for permission to copy or to make other use of material in this esis in whole or in part should be addressed to : ead of the Department of Electrical Engineering niversity of Saskatchewan askatoon, Saskatchewan anada 7N OWO 11 Acknowledgements I would like to especially thank Dr. R. Bolton for his guidance and advice oughout the course of this work. My appreciation also goes to Mr. Lloyd his technical advice and assistance in preparing the printed circuit ards. I would like to acknowledge Dr. J. Mowchenko of the University of lberta for providing the GAP source code. Special thanks also go to the anadian Microelectronics Corporation for their permission to include the vailable process technology information in Appendix A. I would also like to thank two of my roommates, Jody Keiner and Tammy ugie, for proof-reading four chapters of this thesis. My parents and close friends deserve very special thanks for their ontinued encouragement and understanding throughout this research. iii UNIVERSITY OF SASKATCHEWAN Electrical Engineering Abstract 90A327 AN INVESTIGATION OF INTEGRATED CIRCUIT HARDWARE DESIGN RULE CHECKING USING THE TMS34010 Student : Amy S. M. Lau Supervisor: Dr. R. J. Bolton M.Sc. Thesis presented to the College of Graduate Studies and Research August 1990 Abstract Design rules in an integrated circuit layout are a set of constraints on the eature size and dimensional relationships between different layers of materials sed to fabricate the circuit. Most design rule checking is done by running atch jobs on large computer systems. By using special hardware, the speed of e integrated circuit design rule checking can be increased significantly. A hardware design rule checker (DRC) is investigated and developed in . s research. The hardware DRC prototype implements an existing design rule hecking algorithm (GAP - Geometry Analysis Program) using the TMS34010 aphics system processor. GAP is a program for checking design rules with j st two geometric primitives, and is able to identify the edges which cause a e violation. The TMS34010 is an advanced 32-bit microprocessor which is ptimized for graphics systems. It provides powerful graphics functions, oolean pixel block transfers and bit-mapped which are suitable for . graphics s application. The research is a combination of custom written software that conducts ix categories of design rules and additional hardware for optimization of erformance. Design rule checking using the Northern Telecom CMOS3 chnology has been implemented. Standard cells from the QUISC library were sed to verify the hardware DRC. IV Table of Contents Page • • • • • " • e • 11 Copyright • • • • " • • • • • • • • • • • • • • • • • • • • • .. • • • • • • • . .. III jJ cknowledgements . jJ bstract iv . .. List of Tables . ix List of Figures x 1 INTRODUCTION 1 . .. 1 1.1. The Purpose of Design Rule Checking . 1.1.1. IC Design and Verification Tools. .. 3 1.2. Design Rule Checking 5 1.3. Problems in Existing DRCs and Possible Solution. .. 7 . .. 1.3. Objective of the Research . 8 2 DESIGN RULE CHECKING 10 . .. 2.1. Introduction . 10 2.2. Introduction to Design Rules 10 2.2.1. Width . .. 12 . .. 2.2.2. Spacing . 13 2.2.3. Overlaps 15 2.2.4. Enclosures 16 2.2.5. Extensions 17 2.2.6. Special Rules 17 2.3. Software Design Rule Checkers 18 2.3.1. Raster-Scan Method 20 2.3.2. The Polygon Method 22 . .. 2.3.3. Comer-Based DRC . 24 2.3.4. MAGIC's Incremental DRC 27 2.3.5. Design Integrity and Immunity Checking . .. 30 2.3.6. Fast Algorithms . .. 32 2.3.7. Geometry Analysis Program 33 2.4. Hardware Design Rule Checker 34 2.4.1. Special Purpose Hardware for Design Rule Checking 34 2.5. Selected DRC algorithm for the hardware DRC 40 2.6. Summary 41 3 GEOMETRY ANALYSIS PROGRAM 43 v . .. 3.1. Introduction . 43 . .. 3.2. Geometric Operations . 43 . .. 3.2.1. Intersection . 44 . .. 3.2.2. Tolerance . 47 . .. 3.2.3. Error Reporting . 49 3.3. DRC Operations . .. 50 3.4. Examining GAP 54 3.4.1. Running GAP under UNIX 54 3.4.2. Running GAP from within KIC . .. 55 . .. 3.5. Design Rules in GAP . 55 3.6. Hardware Selection 57 3.7. Summary 60 4 TMS34010 GRAPHICS SYSTEM PROCESSOR 61 . .. 4.1. Introduction . 61 . .. 4.2. Design Architecture . 63 4.3. General-Purpose Instructions Overview . .. 66 . .. 4.4. Graphics Instructions Overview. 68 4.4.1. Pixel Block Transfers 69 4.4.2. Boolean and Arithmetic Operations . .. 71 4.4.3. Plane Masking 73 . .. 4.5. Applications . 74 4.6. TMS34010 as the GAP Hardware DRC Processor . .. 75 4.6.1. The TMS34010 Software Development Board. .. 78 4.7. Summary 79 5 SOFrWAREDEVELOPMENT W . .. 5.1. Introduction . 80 5.2. Implementation of the GAP Functions 80 5.2.1. Customization of GAP 81 5.2.2. Display and Intersection. .. 87 5.2.3. Screen Scanning 91 5.2.3.1. Hardware Scanning 93 5.2.3.2. Software Scanning. .. 96 5.2.4. Labelling and Tolerancing 98 5.2.5. Error Detecting and Reporting . .. 101 5.3. Layout Clipping 104 5.3.1. Edge Clearance and Overlapping of Clipping Windows. 105 5.4. Data Translation . .. 108 5.5. Data Transfer Between the PC and the SDB 109 5.6. Summary 111 6 HARDWARE DEVELOPMENT 113 . .. 6.1. Introduction . 113 6.2. Purpose of the Additional Hardware 113 6.3. Preliminary Design 115 vi 6.4. Final Design 119 6.5. Summary 122 7. TESTING AND LIMITATIONS 123 . .. 7.1. Introduction . 123 . .. 7.2. Testing . 126 7.2.1. Preliminary Testing 126 7.2.2. Testing of the QUISC Library Cells . .. 127 7.3. Limitations 128 7.3.1. The Cause of False Errors 129 7.3.2. Performance of the Software Scanning 133 . .. 7.3.3. Other Limitations . 137 7.4. Summary 138 8. SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS 139 8.1. Summary 139 . .. 8.2. Conclusions . 141 . .. 142 8.�. Recommendations for Further Study . R BFERENCES 144 All>pENDIX A NORTHERN TELECOM CMOS3 DOUBLE LAYER METAL (DLM) DESIGN RULES 146 A.1. Introduction 147 . .. A.2. CMOS DLM . 147 . .. A.2.1. CMOS DLM Process . 147 A.2.2. CMOS .DLM Mask Levels and CIF Layer Assignments 149 A.2.3. CMOS3 DLM Design Rules 149 A.2.3.1. Minimum Dimensions 153 A.2.3.2. Minimum Spacing 153 A.2.3.3. Enclosures 154 A.2.3.4. Minimum Separations 155 A.2.3.5. Overlaps 155 . .. A.2.3.6. Pad Rules. 156 . .. A.2.3.7. Capacitor Rules . 157 A.2.4. CMOS3 DLM Parameters 157 A.2.4.1. SPICE Transistor Parameters . .. 158 A.2.4.2. Other Electrical Parameters . .. 159 Al>pENDIX B THE GAP CMOS3 TECHNOLOGY FILE . .. 162 Al>pENDIX C HARDWARE SCREEN SCANNING CIRCUIT SCHEMATICS AND RELATED EXTERNAL INTERRUPT ROUTINE 171 Al>pENDIX D THE PROTOTYPICAL TECHNOLOGY FILE 176 vii A DPENDIX E THE LAYOUTS OF THE CHOSEN QUISC STANDARD CELLS. .. 182 viii List of Tables T ble 4.1 PPOP codes for Boolean and arithmetic Operations (from [11]). 72 T ble 4.2 Typical applications of the TMS34010 (from [11]). 75 T ble 5.1 The SDB default colors for analog RGB output. 87 T ble 7.1 The GAP CMOS3 design rules which can be implemented by the function calls of the six design rule categories. .. 125 Time required to check the selected QUISC library cells using GAPDRC and the GAP implementation using the TMS34010 SDB. 129 CIF layer names and colours. 152 lX List of Figures igure 1.1 Multilevel design process. 2 'gure 1,2 Design automation system (from [1]). 4 igure 1.3 Design rule checking process (from [2]). 6 . .. igure 2.1 Width rule. 131 . .. igure 2.2 Inter-layer spacing rule. 14' . igure 2.3 Intra-layer spacing rule. 14,1 igure 2.4 Overlap rule (a) buried contact, (b) split contact. .. 15! igure 2.5 Enclosure rule. 161 igure 2.6 Extension rule. 18'1' .. igure 2.7 Minimum dimensions rule. 19' . .. igure 2.8 Maximum dimensions rule. 19 igure 2.9 Enclosure rule check using the raster-scan method by Baker and Terman (from [5]). igure 2.10 Spacing rule check using the Polygon Method. 23 igure 2.11 Spacing rule in LYRA (from [6]). 21126 igure 2.12 Spacing constraints in LYRA (from [6]). 26 'I igure 2.13 An example of a comer-stitched plane in MAGIC (from [7]). .. 281 igure 2.14 Edge-based rule in MAGIC (from [7]). 281 igure 2.15 Edge-based rule with comer extension in MAGIC (from [7]).
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