AN INVESTIGATION OF INTEGRATED
CIRCUIT HARDWARE DESIGN RULE
CHECKING USING THE TMS34010
A Thesis
Submitted to the Faculty of Graduate Studies and Research
in Partial Fulfillment of the Requirements
for the Degree of
Master of Science
in the
Department of Electrical Engineering
University of Saskatchewan
Saskatoon
by
Amy Sze Ming Lau
August, 1990
The author claims copyright. Use shall not be made of the material mnp(, herein without proper acknowledgement, as indicated on the following page. Copyright
The author has agreed that the Library, University of Saskatchewan, maYI ake this thesis freely available for inspection. Moreover, the author hasl greed that permission for extensive copying of this thesis for scholarly urposes may be granted by the professor or professors who supervised the esis work recorded herein or, in their absence, by the Head of the epartment or the Dean of the in which the thesis work was done. It College I s understand that due recognition will be given to the author of this thesis. opying or publication or any other use of the thesis for fmancial gain without pproval by the University of Saskatchewan and the author's written permission s prohibited.
Requests for permission to copy or to make other use of material in this esis in whole or in part should be addressed to :
ead of the Department of Electrical Engineering niversity of Saskatchewan askatoon, Saskatchewan anada 7N OWO
11 Acknowledgements
I would like to especially thank Dr. R. Bolton for his guidance and advice
oughout the course of this work. My appreciation also goes to Mr. Lloyd
his technical advice and assistance in preparing the printed circuit
ards.
I would like to acknowledge Dr. J. Mowchenko of the University of
lberta for providing the GAP source code. Special thanks also go to the
anadian Microelectronics Corporation for their permission to include the vailable process technology information in Appendix A.
I would also like to thank two of my roommates, Jody Keiner and Tammy
ugie, for proof-reading four chapters of this thesis.
My parents and close friends deserve very special thanks for their ontinued encouragement and understanding throughout this research.
iii UNIVERSITY OF SASKATCHEWAN
Electrical Engineering Abstract 90A327
AN INVESTIGATION OF INTEGRATED CIRCUIT HARDWARE
DESIGN RULE CHECKING USING THE TMS34010
Student : Amy S. M. Lau Supervisor: Dr. R. J. Bolton
M.Sc. Thesis presented to
the College of Graduate Studies and Research
August 1990
Abstract
Design rules in an integrated circuit layout are a set of constraints on the eature size and dimensional relationships between different layers of materials sed to fabricate the circuit. Most design rule checking is done by running atch jobs on large computer systems. By using special hardware, the speed of e integrated circuit design rule checking can be increased significantly. A hardware design rule checker (DRC) is investigated and developed in . s research. The hardware DRC prototype implements an existing design rule hecking algorithm (GAP - Geometry Analysis Program) using the TMS34010 aphics system processor. GAP is a program for checking design rules with j st two geometric primitives, and is able to identify the edges which cause a e violation. The TMS34010 is an advanced 32-bit microprocessor which is ptimized for graphics systems. It provides powerful graphics functions, oolean pixel block transfers and bit-mapped which are suitable for . graphics s application.
The research is a combination of custom written software that conducts ix categories of design rules and additional hardware for optimization of erformance. Design rule checking using the Northern Telecom CMOS3 chnology has been implemented. Standard cells from the QUISC library were sed to verify the hardware DRC.
IV Table of Contents
Page
• • • • • " • e • 11 Copyright • • • • " • • • • • • • • • • • • • • • • • • • • • .. • • • • • • •
...... III jJ cknowledgements ...... jJ bstract iv
. . . .. List of Tables ...... ix
List of Figures x
1 INTRODUCTION 1
...... 1 1.1. The Purpose of Design Rule Checking .
1.1.1. IC Design and Verification Tools...... 3 1.2. Design Rule Checking 5 1.3. Problems in Existing DRCs and Possible Solution...... 7
...... 1.3. Objective of the Research ...... 8
2 DESIGN RULE CHECKING 10
...... 2.1. Introduction ...... 10 2.2. Introduction to Design Rules 10
2.2.1. Width ...... 12
...... 2.2.2. Spacing ...... 13 2.2.3. Overlaps 15 2.2.4. Enclosures 16 2.2.5. Extensions 17 2.2.6. Special Rules 17 2.3. Software Design Rule Checkers 18 2.3.1. Raster-Scan Method 20 2.3.2. The Polygon Method 22
. . .. 2.3.3. Comer-Based DRC ...... 24 2.3.4. MAGIC's Incremental DRC 27
2.3.5. Design Integrity and Immunity Checking ...... 30
2.3.6. Fast Algorithms ...... 32 2.3.7. Geometry Analysis Program 33 2.4. Hardware Design Rule Checker 34 2.4.1. Special Purpose Hardware for Design Rule Checking 34 2.5. Selected DRC algorithm for the hardware DRC 40 2.6. Summary 41
3 GEOMETRY ANALYSIS PROGRAM 43
v ...... 3.1. Introduction ...... 43
...... 3.2. Geometric Operations ...... 43
...... 3.2.1. Intersection ...... 44
...... 3.2.2. Tolerance ...... 47
...... 3.2.3. Error Reporting ...... 49
3.3. DRC Operations ...... 50 3.4. Examining GAP 54 3.4.1. Running GAP under UNIX 54
3.4.2. Running GAP from within KIC ...... 55
. . .. 3.5. Design Rules in GAP ...... 55 3.6. Hardware Selection 57 3.7. Summary 60
4 TMS34010 GRAPHICS SYSTEM PROCESSOR 61
. . .. 4.1. Introduction ...... 61
. .. 4.2. Design Architecture ...... 63
4.3. General-Purpose Instructions Overview ...... 66
...... 4.4. Graphics Instructions Overview...... 68 4.4.1. Pixel Block Transfers 69
4.4.2. Boolean and Arithmetic Operations ...... 71 4.4.3. Plane Masking 73
. . . .. 4.5. Applications ...... 74
4.6. TMS34010 as the GAP Hardware DRC Processor ...... 75
4.6.1. The TMS34010 Software Development Board...... 78 4.7. Summary 79
5 SOFrWAREDEVELOPMENT W
. . .. 5.1. Introduction ...... 80 5.2. Implementation of the GAP Functions 80 5.2.1. Customization of GAP 81
5.2.2. Display and Intersection...... 87 5.2.3. Screen Scanning 91 5.2.3.1. Hardware Scanning 93
5.2.3.2. Software Scanning...... 96 5.2.4. Labelling and Tolerancing 98
5.2.5. Error Detecting and Reporting ...... 101 5.3. Layout Clipping 104 5.3.1. Edge Clearance and Overlapping of Clipping Windows. 105
5.4. Data Translation ...... 108 5.5. Data Transfer Between the PC and the SDB 109 5.6. Summary 111
6 HARDWARE DEVELOPMENT 113
. . .. 6.1. Introduction ...... 113 6.2. Purpose of the Additional Hardware 113 6.3. Preliminary Design 115
vi 6.4. Final Design 119 6.5. Summary 122
7. TESTING AND LIMITATIONS 123
...... 7.1. Introduction ...... 123
...... 7.2. Testing ...... 126 7.2.1. Preliminary Testing 126 7.2.2. Testing of the QUISC Library Cells ...... 127 7.3. Limitations 128 7.3.1. The Cause of False Errors 129 7.3.2. Performance of the Software Scanning 133
...... 7.3.3. Other Limitations ...... 137 7.4. Summary 138
8. SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS 139 8.1. Summary 139
...... 8.2. Conclusions ...... 141
...... 142 8.�. Recommendations for Further Study .
R BFERENCES 144
All>pENDIX A NORTHERN TELECOM CMOS3 DOUBLE LAYER METAL (DLM) DESIGN RULES 146 A.1. Introduction 147
...... A.2. CMOS DLM ...... 147
...... A.2.1. CMOS DLM Process ...... 147 A.2.2. CMOS .DLM Mask Levels and CIF Layer Assignments 149 A.2.3. CMOS3 DLM Design Rules 149 A.2.3.1. Minimum Dimensions 153 A.2.3.2. Minimum Spacing 153 A.2.3.3. Enclosures 154 A.2.3.4. Minimum Separations 155 A.2.3.5. Overlaps 155
. . . .. A.2.3.6. Pad Rules...... 156
. . . .. A.2.3.7. Capacitor Rules ...... 157 A.2.4. CMOS3 DLM Parameters 157
A.2.4.1. SPICE Transistor Parameters ...... 158
A.2.4.2. Other Electrical Parameters ...... 159
Al>pENDIX B THE GAP CMOS3 TECHNOLOGY FILE ...... 162
Al>pENDIX C HARDWARE SCREEN SCANNING CIRCUIT SCHEMATICS AND RELATED EXTERNAL INTERRUPT ROUTINE 171
Al>pENDIX D THE PROTOTYPICAL TECHNOLOGY FILE 176
vii A DPENDIX E THE LAYOUTS OF THE CHOSEN QUISC STANDARD
CELLS...... 182
viii List of Tables
T ble 4.1 PPOP codes for Boolean and arithmetic Operations (from [11]). 72 T ble 4.2 Typical applications of the TMS34010 (from [11]). 75 T ble 5.1 The SDB default colors for analog RGB output. 87 T ble 7.1 The GAP CMOS3 design rules which can be implemented by the function calls of the six design rule categories...... 125 Time required to check the selected QUISC library cells using GAPDRC and the GAP implementation using the TMS34010 SDB. 129 CIF layer names and colours. 152
lX List of Figures
igure 1.1 Multilevel design process. 2 'gure 1,2 Design automation system (from [1]). 4 igure 1.3 Design rule checking process (from [2]). 6
. . . .. igure 2.1 Width rule...... 131
...... igure 2.2 Inter-layer spacing rule...... 14'
...... igure 2.3 Intra-layer spacing rule...... 14,1 igure 2.4 Overlap rule (a) buried contact, (b) split contact...... 15! igure 2.5 Enclosure rule. 161 igure 2.6 Extension rule. . 18'1'
.. igure 2.7 Minimum dimensions rule...... 19'
...... igure 2.8 Maximum dimensions rule...... 19 igure 2.9 Enclosure rule check using the raster-scan method by Baker and Terman (from [5]). igure 2.10 Spacing rule check using the Polygon Method. 23 igure 2.11 Spacing rule in LYRA (from [6]). 21126 igure 2.12 Spacing constraints in LYRA (from [6]). 26 'I igure 2.13 An example of a comer-stitched plane in MAGIC (from [7]). .. 281 igure 2.14 Edge-based rule in MAGIC (from [7]). 281 igure 2.15 Edge-based rule with comer extension in MAGIC (from [7]).. , 291 igure 2.16 Block diagram of the ORC presented by McGrath and !
...... Whitney [8]...... 311 igure 2.17 Seiler's design rule check hardware system (from [3]). 361 igure 2.18 Valid 3x3 and 4x4 windows for orthogonal width checking in
. Seiler's ORC (from [3]). . 38'11 igure 2.19 Valid 3x3 and 4x4 windows for angled width checking in I Seiler's ORC (from [3]). igure 3.1 Intersection and label example. 46,381
...... igure 3.2 Tolerancing examples...... 481 igure 3.3 Tolerance extensions (tolerance layer 1). 481 igure 3.4 Polysilicon extension rule check example (step 1). . . .. 52! igure 3,5 Polysilicon extension rule check example (step 2). 531 igure 3,6 Polysilicon extension rule check example (step 3). 531 . .. igure 4.1 System block diagram (from [11])...... 64 igure 4.2 Internal architecture block diagram (from [11])...... 65 igure 4.3 Two-operand PIXBLT operation (from [12]). 71 igure 4.4 Organization of the screen memory with 4-bit pixel size (from I [11]). 741
igure 5.1 Possible distortion due to box shrinking operation...... 83!
igure 5.2 Polysilicon extension rule check in GAP...... 851 igure 5.3 Polysilicon extension rule check using closed space for all
...... layers...... 86 igure 5.4 Reduction of box number by re-scanning after display. 89
x gure 5.5 gure 5.6 gure 5.7 gure 5.8
gure 5.9 igure 5.10
gure 5.11 igure 5.12
gure 5.13 igure 5.14 igure 5.15 igure 6.1 igure 6.2 igure 6.3 igure 6.4 igure 6.5 igure 7.1 igure 7.2 igure A.1 igure A.I igure A.2 igure A.3 igure C.1 igure E.1 igure E.2 igure E.3
xi CHAPTER 1
INTRODUCTION
11. The Purpose of Design Rule Checking
The term very large scale integration (VLSI) indicates the capabilities of t day's semiconductor industry to fabricate a complex electronic circuit which is
ade up of thousands of components on a single chip. Due to the rapid growth o the circuit size and complexity, it becomes impossible to manually conform
e circuit layouts with the specification of the fabrication process. Therefore,
e use of automated layout design and verification tools are widely used.
According to "Moore's Law" [1][2], the component density in a chip q adruples every three to four years. A major factor which contributes to this r pid growth is the reduction of circuit feature size due to the advancement of
In order to manage large circuits efficiently, techniques
s ch as hierarchy and modularity are utilized in the integrated circuit (K') design
The design process of a typical integrated system can be regarded as a
ulti-level translation scheme [1]. It undergoes the top-down design stages
s own in Figure 1.1. The designer first defines the system by a schematic
1 2
Design Description
Subsystem Logic
Mod ule Logic
Mod ule Verification
Subsystem Verification
Layout
Figure 1.1 Multilevel design process.
of interconnected subsystems such as I/O. control. bus. and memory.
his system-level specification is further broken down into hierarchical modules
xpressed in logic equations or state diagrams. The modules are then
ansformed into logic diagrams. With the sequencing and timing information.
e logic diagrams are transformed into gate- or switch-level building blocks for t e target semiconductor technology. Design verification is performed on the
ndamental modules at each hierarchical level to simplify the verification
rocess. The final stage is to convert all hierarchical levels into the physical i terconnected circuit as it appears on the integrated circuit. 3
At each design level described above, the designer has to follow a set of
onstraints which are comparable to the syntax of a program compilation process.
or example, the gate level and the layout level are governed by design rules
. ctating feature size and dimensional relationships between layers. Most of the
rimary design rules are straightforward (the details of these rules are explained i Chapter 2). However, complications appear when certain variations from the
asic design rules are introduced in some special situations. Since the
pecification of a complete design rule set for a certain IC fabrication process is
ften many pages long, these rules are commonly used as an input to the
utomated design rule checking tools. An example of the design rules for the
orthem Telecom CMOS3 Double Layer Metal (DLM) process is included in
ppendix A .
. 1.1. Ie Design and Verification Tools
The development of IC design software systems and tools is an important
actor in VLSI technology. They enable one to handle designs at a level that
oes not involve the great details of process- and fabrication-dependent
arameters. Figure 1.2 is a flow diagram of the organization and
·nterrelationships of common tools used in IC design [1]. The components of a
esign automation system are:
1) system/functional specification/simulation,
2) design entry, 4
S,slem System specification simulation
_____ J
Gl'llphics Layout layout \0018 language \oobs
Check plata
Eles.Hical Logic TlmiDg cheCker simulator simulal:Dr
OK OK OK OK
Fabricate cbip
Figure 1.2 Design automation system (from [1]). 5
3) layout,
4) generation of an intermediate format (such as the CalTech
Intermediate Form - CIF), and
5) simulators at low levels of physical design.
ashed lines indicate the recurrence of the process due to design verification and
odification prior to fabrication. Except for the implementation of system and
nctional specifications, the rest of the tools can be classified into five
ategories:
1) design entry or logic capture systems,
2) graphics- or language-based circuit layout tools,
3) layout verification tools such as design rule checking or circuit
extractor,
4) simulation tools for operative and timing confmnation, and
5) routing tools for interconnection and position .
. 2. Design Rule Checking
The hatched block in Figure 1.2 indicates that it is necessary to apply the
hysical design description against the manufacturing design rules to check for
iolations before sending the layout to the IC fabrication house. A design rule
hecker (DRC) is a piece of software or hardware design system tool that
enerally accepts two input files - the physical design description, and the t chnology-specific file which consists of the design rules. The DRC output is 6
errors physical design - data base i.e., shapes
- - design rule checking
- program technology- specific design rule set - diagnostics
Figure 1.3 Design rule checking process (from [4]).
error file which describes the nature and the location of the violations. The g neral process of design rule checking is illustrated in Figure 1.3.
Design rule checking is known to be one of the most computationally t dious aspects of integrated circuit design [3]. In most IC fabrication houses,
is process is performed by running the design rule checking program on a large c mputer system. Note that the programs whose input files are detailed target t chnology descriptions are expected to be technology independent [4]. The
RC should be capable of handling a range of technologies which have their
wn design rules and device/interconnection levels. Many variations of DRCs e ist nowadays but they generally fall into two main categories:
1) software DRCs such as:
• the raster-scan method by Baker and Terman [5], 7
• the Polygon Method by Yamin (sited in [1]),
• the comer-based DRC by Arnold and Ousterhout [6],
• the incremental-based DRC by Taylor and Ousterhout [7],
• design integrity and immunity checking by McGrath and
Whitney [8],
• the Fast Algorithms by Baird [9], and
• Geometry Analysis Program by Mowchenko [10].
2) hardware DRCs such as:
• the special purpose hardware DRC by Seiler [3].
e basic operations, advantages and shortcomings of these DRC approaches will
discussed in Chapter 2 .
.3. Problems in Existing DRCs and Possible Solution
Although software DRCs are flexible, most of them suffer from run-time
eficiencies due to their CPU intensive characteristic. When checking large
esigns, software DRCs consume valuable CPU time. A solution to this
eficiency, which introduced special purpose hardware to the verification process,
as proposed by Seiler [3]. Since the special purpose hardware is in the form
f custom chips, the resulting hardware DRC has limited flexibility. In addition,
. is a costly approach due to the expense required in the custom chip design and abrication. 8
Several high-performance commercial graphics chips have been introduced
recent years to meet the high demand in computer graphics quality and erformance. Some chips are equipped with both software and hardware evelopment tools which give the users a large degree of flexibility in ustomizing the hardware to perform specific tasks such as design rule checking.
ith the appropriate ORC algorithm, the commercial graphics chips may provide
exible, efficient, and inexpensive solutions to the problems in existing ORCs .
. 4. Objective of the Research
The purpose of this research is to investigate the suitability of utilizing a ommercial graphics system processor (such as the TMS34010 from Texas
struments) to implement a hardware ORC which uses a simple ORC algorithm such as the Geometry Analysis Program [10]). Software development tools, uch as the TMS34010 graphics software development board (SOB), are used to rovide a proficient way to examine the hardware ORC prototype. The graphics
OB, which consists of a TMS34010, is a single IBM PC format card designed
ound the PC I/O expansion bus which allows programmers to write application oftware for the TMS34010. The hardware ORC prototype should:
• utilize the interface provided by the SOB to perform tasks such as:
• transferring layout information between the host computer
system and the graphics system processor, and
• initating the ORC operations. 9
• be inexpensive,
• use simple and generalized operations,
• handle layouts which consist of orthogonal geometries (including
polygons that are formed by two or more adjacent boxes),
• handle layouts which have overlapping boxes on the same layer,
• handle layouts without hierarchy,
• perform primary design rule checks such as minimum width and
spacing,
• handle large layouts with the assistance of clipping routines,
• display rule violations,
• be capable of managing any IC technologies,
• perform the design rule checking using a resolution similar to those
of the IC fabrication house, and
• use fast software language(s) such as C or assembly language to
maximize the performance. f\ minor objective is to develop a series of data translation programs to convert ayouts described in the CalTech Intermediate Form (CIF) into a display data lormat ready for the graphics system processor. Moreover, a communication method should be developed to allow fast data transfer between the graphics system processor and the host system through the SDB interface. Chapter 2
DESIGN RULE CHECKING
.1. Introduction
Due to the limitations of the fabrication process, chip designers have to f How a set of design rules while laying out their circuits. The basic
eometrical constraints are the specification of minimum feature size and spacing.
I the first part of this chapter, the details of these primary categories of design
There are continuous efforts in developing automated
sign rule checking tools because most of them have difficulties in handling the
SI layout complexity while maintaining an acceptable run-time. In addition, t e reduction of false/unchecked errors is also a goal of the development [8]. In
the appropriate algorithm for the hardware DRC implementation,
methods were investigated and each of them will be briefly
scribed in this chapter.
. 2. Introduction to Design Rules
According to Mead and Conway [2], the most powerful characteristic of
odern IC fabrication processes is that they are pattern independent. In other
ords, there is a clean separation between the effort needed to design the
10 11
r uired circuit pattern and the processing done during wafer fabrication. Since t ere are several causes for abnormal feature shapes in fabricated circuitry (such
misalignment, variations in the photoresist edges due to exposure
undercutting of thin oxide under the comers of the photoresist and
veretching), this separation requires a specific definition for the processing line
apabilities i.e., fabrication limits. The specification is expressed usually in the
rm of permissible geometries on the mask layers. It makes the designers
ware that they are working within the resolution of the process so that t ansistors and interconnections formed by the process can function properly.
hese geometrical constraints can be simply referred to as design rules. They
e an enforced methodology for the composition of mask geometries which
efine the ways features on various layout masks may be positioned with respect t each other [2].
The purpose of design rules is to guarantee that even under deviations of
fabrication processes, the circuit topology is preserved, Le., no merging of
eparate features and no splitting (due to notching or necking) of small features.
he rules must also minimize alterations in the electrical parameters which can
feet the performance of the fabricated circuit. For example, the resistance and
apacitance of a wire are determined by the physical dimensions (such as length
d width) of the feature itself. Design rules tend to fall into the following
ategories: 12
1) width,
2) spacing or separations,
3) special cases such as contact cut dimensions,
4) overlaps,
5) enclosures. and
6) extensions.
hese are described in the following subsections. These categories are expanded i to 58 rules in the Northern Telecom Double Layer Metal (DLM) design rule
et in Appendix A. Also included in the appendix is a general description of the
C fabrication process .
• 2.1. Width
The width rule defines the minimum feature size of one layer that can be
eliably patterned without notching/necking of the line by lithographic error.
evertheless, this is not the only reason for the minimum width rule. A
eature's size may alter the operation of the circuit. For example, if the current
ensity exceeds certain limits of metal wire, metal migration might occur. Metal
igration means that as the metal atoms move towards the direction of current
ow, the wire will become thinner until it collapses as a fuse [1]. An
. lustration of this rule is shown in Figure 2.1. 13
j_ width error minimum width
T ,_
-
metal
Figure 2.1 Width rule.
• 2.2. Spacing
In order to physically separate two regions, the spacing rule is needed to ovem the dimensions that can be reliably etched apart with no accidental onnections. The spacing rule is required not only for the geometric resolution f the process but also for the physics of the devices [2]. This is because some
aterials, such as diffused regions, have a tendency to spread outward. If two
. ffused wires come too close, their depletion regions might overlap and form an nintended path between the wires. As shown in Figure 2.2 and in Figure 2.3,
can be further classified as the inter-layer spacing and the intra-layer
acing. 14
inter-layer spacing error
Legend � polysilicon D diffusion minimum spacing
Figure 2.2 Inter-layer spacing rule.
minimum spacing
intra-layer spacing error
Legend o diffusion
Figure 2.3 Intra-layer spacing rule. 15
(a) (b)
overlap r------, I I I I I I I I I I L _j
Legend _, r- overlap � polysilicon D p+ D diffusion [J p-well � contact cut
Figure 2.4 Overlap rule (a) buried contact, (b) split contact.
2 2.3. Overlaps
This rule is defined by the amount of overlapping of two different layers.
n example of this rule is the formation of a buried contact cut which connects t e polysilicon and diffusion layer in the nMOS process. As shown in
. gure 2.4, the polysilicon and diffusion layers have to overlap in the centre of t e contact cut by a certain amount to allow proper connection. Also illustrated i the figure is the overlapping of the thin oxide and p+ region of a split contact c t in the CMOS process. 16
Legend o metal � polysilicon � contact cut
Figure 2.5 Enclosure rule .
• 2.4. Enclosures
This design rule, which involves two layers, defines the amount of verhang a feature requires from a different mask layer. It is often applied to ifferent types of contact cut. For instance, Figure 2.5 shows a contact cut
tween polysilicon and metal layers which requires allowances for such things s misalignment, enlarging of contact cut size during etching, and shrinking of
. ffusion area during field oxide growth. If the diffusion does not overlap the ontact cut by a sufficient amount, the metal wire would short to the substrate. 17
In the Northern Telecom CMOS3 Double Layer Metal (DLM) technology, the overhang region has to extend by a certain amount in the direction of the metal.
2 2.S. Extensions
A good example to illustrate the extension rule is the formation of a transistor as shown in Figure 2.6. A minimum-size transistor is formed when a
II inimum-size polysilicon wire and a minimum-size diffusion wire cross. In o der to avoid a short-circuit path between the drain and source, the polysilicon gate has to extend on both sides by a certain amount (which depends on the target technology). Similarly, to ensure that there are diffusion regions to conduct the channel current, the source-drain diffusion wire has to extend past the polysilicon gate.
2 2.6. Special Rules
Additional to the fundamental design rules mentioned above, the designer has to consider several special cases as well. Two of these special cases are the minimum and maximum dimensions of the contact cut. To guarantee its e xistence, the contact cut has to meet the minimum dimensions requirement. The maximum dimensions rule is also applied to contact cuts since contact cuts larger than the minimum size tend to bloom and become uncontrolled. Therefore, 18
legend diffusion extension error I?ZJ polysllicon 0 diffusion polysilicon extension error [J extension
minimum diffusion extension past gate
minimum polysilicon __-' extension past gate
Figure 2.6 Extension rule. c ntact cuts must be minimized at least one dimension, possibly two. Figure 2.7
d Figure 2.8 summarize the above dimensional constraints .
. 3. Software Design Rule Checkers
There are more software DRCs than hardware DRCs. Therefore to cover a
oad range of software approaches, seven software DRC algorithms were
Their basic operations, advantages and shortcomings are discussed
low. 19
minimum dimension or contact cut
minimum dimension
errors
Legend
D diffusion � contact cut r- -..., minimum
L_ _ J dimension
Figure 2.7 Minimum dimensions rule.
maximum dimension of contact cut
maximum dimension
errors
legend
D diffusion � contact cut
- r- ..., I maximum
L-- _ J dimension
Figure 2.8 Maximum dimensions rule. 20
·3.1. Raster-Scan Method
Baker and Terman of MIT have developed a raster-scan method in 1980
In this method, the chip layout is represented on a 1"- graph paper and the alue of each square indicates the existence of each layer. In the set of nMOS esign rules, the largest minimum width or spacing is 3"-. Hence, there should
sufficient information in a 4"- by 4"- "window" to detect if there is any rule iolation in the window. In case of 2"- rules, such as minimum width of the olysilicon layer, a 3"- by 3"- window is sufficient. Successive windows are xamined by scanning the plot with the three-by-three or four-by-four aperture,
oving one square at a time, left to right, top to bottom. If every window beys the design rules, then the layout is free of errors.
To see how the window scanning works, consider the possible windows for erforming a. minimum width rule check on the metal layer (for which minimum
3"-). First, consider a four-by-one window. With four squares in the
there are 16 possible combinations and only eight of which are legal
= metal, W = white space): WWWW, WWWM, WWMM, WMMM,
MMM, MMMW, MMWW, and MWWW. Any other combination indicates a
It might seem sufficient to scan the layout in both x and y
. ections using this window. However, the four-by-one window does not cover 21
· agonal width and spacing check. Therefore, a four-by-four window is ecessary for complete checking.
The method is able to check not only single-layer rules, but also
omplicated multi-layer rules such as the D.. metal enclosure at contact cut. As hown in Figure 2.9, if the centre four squares of the window are all contact (C),
en the whole window must contain metal (M). If it does not, there is an nclosure error, and the coordinates of the window will be recorded in an error ile.
p p p p
p p p p U D D D and p p p p U D D D
p p p p D D D D
? ? ? ? lit N Pol Pol
? C C ? lit N Pol Pol if then AND or ? C C ? ... N Pol Pol
? ? ? ? lit N Pol Pol
D D D D p p p p
D D D D p p p p and D D D D l' l' J5 J5
D D D D p P P P
Legend
C - contact P - polysilican
- Pol metal D - diffusion
Figure 2.9 Enclosure rule check using the raster-scan method by Baker and Terman (from [5]). 22
The algorithm uses two tables: one table indicates which four-by-four
VI indows contain 3A. rule violations, the other indicates which three-by-three
VI indows contain 2A. rule violations [5]. It took 502 CPU seconds on a PDP-
11nO (running on a UNIX timesharing. system) to check a 1192 lambda by 1202
lambda circuit which consists of 1796 transistors [5]. In addition, the algorithm r rnning on a VAX 11nSO is reported to have a speed of 3 transistors/CPU
second [7].
There are several limitations to this method The algorithm reports some
false errors because it does not have any information about the electrical
connectivity of the components. A considerable amount of storage is required to
s ore the tables since it needs about S Kilo-bytes of memory per layer. The
s oeed of accessing this information can be very slow. Another drawback is the
r edundant reporting of the same width or spacing errors along the length of a
wire which results in a large error output file. The algorithm scales up poorly
when a window larger than four-by-four is required. Since all knowledge of the
c esign rules is integrated with the actual DRC code, the algorithm is design rule
cependent.
2.3.2. The Polygon Method
This DRC method invented by Yamin (sited from [1]) in 1972 can be
considered as a geometry machine. A sequence of primitive operations (such as 23
GE and EXPAND), and Boolean geometric operations (such as OR, AND,
d EXOR) are applied to a list of polygons, each belongs to a mask layer. All c mmands are self-explanatory and the design rules are expressed in term of
For instance, the spacing rule between two metal polygons can be checked
expanding (using EXPAND operation) the polygons by half the minimum s acing. Then merge the enlarged polygons (by the MERGE operation) to see if t ere is any overlapping which indicates a rule violation. Figure 2.10 contains the s eps for this spacing rule check example.
------overlapping of expanded boxes I--l 1- -l ...... , , , , I I I I I I I I Legend , , , , box I I I I o original r-l expanded box L_J L __ J L_LJ_J
Figure 2.10 Spacing rule check using the Polygon Method. 24
and The main advantages of this method are design rule independence
xibility that allows the algebra of the polygons to be easily adapted to new d sign rules. But since the method is global, the manipulation of polygons is
to the of the q ite time-consuming. The execution time is proportional square n mber of polygons involved (sited from [1]). Another limitation of the polygon
ethod is the need of a complicated operation sequence to handle asymmetric
DLM sign rules such as the contact-metal enclosure rule in the CMOS3
23.3. Corner-Based DRC
In both the raster-scan and polygon methods, many different types of
imitive operations are required for design rule checking. The most notable
ception to this condition are the comer-based DRC, "LYRA"; and the i cremental DRC, "MAGIC", which will be described in the next subsection.
LYRA, developed by Arnold and Ousterhout [6], takes the middle ground
tween the raster-scan approach which bases on checking local grid array
lements, and the polygon method which operates on polygons globally. Most
esign rules on orthogonal geometry layouts can be checked by examining small
gions around the corners on individual or derived mask layers [6].
LYRA is written in a Lisp-like text language and its operations are based
pon comers of the input layout. The comers of the geometries are classified as 25
Each rule is represented by its context and constraint
atterns. A context pattern is defined in terms of the existence of a mask layer
each of the four quadrants at a comer. Whereas each constraint specifies a
tangular area adjacent to the comer where certain mask layers are required or
During the design rule checking process, LYRA compares the
ontext patterns against the actual layer(s) existing at each comer. After
pplying the constraints to the comers with the matching context patterns, LYRA
utputs the error information [6].
The single-layer spacing rule in LYRA is illustrated in Figure 2.11. The
ontext pattern indicates that the rule is applied to all comers where layer M is
resent in one quadrant and is absent in the adjacent quadrants. The constraints
. nclude three restricted areas where the layer M must not exist. Figure 2.12
hows how the spacing constraints are applied to two layer M boxes.
LYRA can be easily adapted to new rule sets due to its single scheme.
owever, it only checks spacing, minimum dimension and overlap rules. Its
ajor drawback is its inefficiency in speed. The current version of LYRA
anipulates 50 comers/CPU-second or 2 transistors/CPU-second on a VAX-
1nSO; at this speed it uses about 2 CPU-seconds to check a simple shift
egister cell [6]. 26
NOT M :M
...
NOT NOT M M L
Context Pattern Constraints
Figure 2.11 Spacing rule in LYRA (from [6]).
Legend
,-, conslraints L_....l violated �T�Y�.- ��NOT� [(7£2 conslrainis mask 1 NOT � � NOT 1 D features LM 1:1 1:1 -.
Figure 2.12 Spacing constraints in LYRA (from [6]). 27
23.4. MAGIC's Incremental DRC
MAGIC operates incrementally on the most recently modified area in the
1 yout and reports rule violations if there are any [7]. The error information is st red in the layout; therefore, the violations which have not been fixed will a pear at the next editing session. This DRC can only handle Manhattan style
and the mask layers are specified by rectangular tiles. Tiles are
dimensions segments in a contiguous region of the same abstract
I yers. The abstract layers identify not only the primary layers (such as metal,
and but such as transistors and ffusion, polysilicon) , also composite layers
Empty areas are represented by "space" tiles.
To represent a layout, a number of planes which contain layers that have t e most interactions are used. These planes are made up of tiles by a technique c led comer stitching. As illustrated in Figure 2.13, each plane consists of
fferent types of tiles which cover the entire plane area and each tile uses four p inters at its comers to link itself to the adjacent tiles.
When MAGIC begins to execute, it reads the technology file and generates
a design rule table. This table consists of a list of rules for all possible layer
c mbinations at both sides of an edge. Each rule specifies the set of mask types
t at are permitted within a certain distance from one side of the edge. MAGIC
a plies these rules at the tile junctions in the plane. Figure 2.14 shows the way 28
Legend
o tiles ._ pointer
F gure 2.13 An example of a comer-stitched plane in MAGIC (from [7]).
-- l no I J
d .... polysilicon
Figure 2.14 Edge-based rule in MAGIC (from [7]). ------�------T------
29
I I
corner extension
areas
I
L _j
igure 2.15 Edge-based rule with comer extension in MAGIC (from [7]).
t e spacing rule is applied to the polysilicon edge. In order to cover the errors
t the comer regions, additional checks are required. This is achieved by the
orner extensions included in Figure 2.15.
Users can benefit from the continuous feedback provided by MAGIC's
i cremental style. It avoids re-checking the entire layout when only a little
ortion of the design is modified Also, by running from the same database as
t e interactive layout editor, it has a low overhead Similar to LYRA, MAGIC
i capable of adapting to a variety of design rules. While LYRA checks 2
ansistors/CPU-second, MAGIC can process 60-100 transistors/CPU-second [7].
owever it is restricted to check spacing, dimensions, and overlap rules only. 30
.3.5. Design Integrity and Immunity Checking
McGrath and Whitney reported a different approach in verifying IC layouts
[8]. It uses topological and device information to reduce most false and
nchecked errors. In addition, it avoids redundant checks with a hierarchical
ont-end which makes this layout description method suitable for DRC. The
ata format for this approach is an extension of ClF. This format allows symbol
efinitions, calls to symbol definitions, and primitive geometrical constructions
·.e. box, wire, polygons, etc.). The major format variation is the usage of i entifiers:
1) a net identifier for each primitive element, and
2) a device type identifier for each primitive symbol (such as transistor,
contact etc.).
hese extra markers provide the information about the original symbols for
eometries which are key in manipulating hierarchical designs [8].
Figure 2.16 shows the block diagram of the design rule checking technique.
t begins by parsing the design and assigning identifiers to each element. Then, t e width of all primitive elements (i.e., boxes, wires, and polygons etc.) is
More complicated checks (such as enclosure and overlap) are
erformed on the primitive symbols. The elements on the same layer which i teract are checked for legal connections. Two elements are connected if their
keletons touch, overlap or one is enclosed by another. The skeleton of an 31
Parse CIF
Check elements
Check primitive symbols
Check legal connections
Generate hierarchical net list
Check interactions
F gure 2.16 Block diagram of the DRC presented by McGrath and Whitney (from [8]). e ment is obtained by shrinking the element by half the minimum width of the c rresponding layer. Based upon the net identifiers assigned previously, the
is then generated and can be used to check electrical c nstruction rules. Finally, the interactions between elements and/or primitive s mbols are checked.
The algorithm takes into account that the expansion or shrinking of a g ometry during fabrication is dependent on the presence of other nearby
A function derived from a two-dimensional convolution of a
aussian exposure function is used to check the spacing rule. Calculation of the 32
e posure function is done at selected points and compared with certain critical
Even though this approach can avoid some false rule violations, the c culation of the function can slow down the entire DRC considerably.
Baird reported a sorted-edge vertex-scanning algorithm [9] which does not r strict the representation of layout; allows a wide range of functions; uses a
inimum amount of edges to depict a layout; and prevents pathologies associated
figure-based representations of a set of overlapped or abutted geometries.
. T s edge management method achieves not only good run-time but also a ceptable main memory demands for LSI applications. Moreover, it can process
ogonal, diagonal, and circular arc edges. It also avoids special boundary e feet processing and exploits the full precision of the coordinate system by
susing partitioned/fixed grid on the layout. Baird's algorithm can be extended
perform all Boolean combinations, multi-mask connectivity, and expansion (or
In order to eliminate all redundant edges of attaching features (which may
to pathologies), the mask is depicted as the result of logical-Oking the i terior of geometries. In the sorted-edge method used in this algorithm, each e ge is assigned a role which consists of a frontier identifier and a direction.
e frontier identifier marks group of edges connected at common vertices. The 33
· rection ensures that the interior of the region surrounded by the edge's frontier i always to the left. Using this method all edges are sorted in lexicographic o der on their past vertices and are inserted into a linked-list structure.
After discovering all intersection points, the edges are split into segments at t ese points to form new vertices. During this process for each vertex, the set
edges which is referred to as the local environment of the vertex provides the
ormation to make topological decisions. The problem with this algorithm is t at the procedures used are complicated and contradict the goal for simplicity
d generality in the hardware DRC.
.3.7. Geometry Analysis Program
GAP [10], a program written in C, was developed at the University of
lberta for checking orthogonal IC mask geometry described in CIF. It runs
ice as fast as LYRA, and is capable of checking rules such as minimum
minimum dimension, overlap, maximum dimension, notch, and
The most significant feature of GAP when compared with most
algorithms is its simple structure. While the others use complicated
operations, GAP utilizes two geometric operations for its design rule
ecking procedure, namely intersection and tolerance. Moreover, GAP can
istinguish the edges that cause the violation by using the geometric operations. 34
abels are used in this algorithm to manipulate topological information of
There are several notable advantages in GAP. Moreover, using only two
eometric operations for rule checking, the program exercises the same pattern
r checking different types of rules. The edges that cause rule violations can be
asily identified by reading the labels from an error layer. A drawback to GAP i that polygons in the two input mask layers are treated differently in the i tersection operation. The polygons are represented by either the closed space
r open space of polygons. GAP will be described in more detail in Chapter 3 .
. 4. Hardware Design Rule Checker
The DRCs described so far in the thesis are software techniques, and their
deficiency in run-time. A different approach for i plementation of DRC is using hardware. A DRC that used special purpose
ardware is introduced by Seiler [3] in 1981 and is described here .
. 4.1. Special Purpose Hardware for Design Rule Checking
The aims of the special purpose hardware DRC by Seiler [3] were to be
. nexpensive, extendable to large number of layers, and applicable to hierarchical
esign rule checking algorithms and 450 angles. The hardware DRC implements
fixed-grid raster-scan algorithm which is similar to the method established by 35
Baker and Terman [5]. The pattern matching operations for each window are c led local area design rule checks. They are subdivided into two main c tegories:
1) width and spacing checks, and
2) general boundary checks.
Siler's hardware ORe also utilizes shrink/expand operations in the width and
s acing checks. The relationship between feature edges on two mask layers are
e amined by the general boundary checks. The ORe reports all possible errors
t at rely on the connectivity or intended functionality of the design.
For a design rule check, the ORe performs three special operations as il ustrated in Figure 2.17. The system consists of a controlling processor which i eludes software to program the local ORe hardware, converts the layout into
t e appropriate format for the rasterization unit, and converts the error output
i to human readable output. First, the design is converted into a raster image b feeding the features that intersect the current scan line to the custom chips in
t e rasterization unit. Next, the resulting data stream enters the local ORe unit
f r primitive ORe operations. Finally, the error reporting hardware converts the p allel streams of error bits into a sequence of error coordinates which are
s udied by the controlling processor.
The criteria for choosing the interface points between software and
h dware is the amount of data to be processed and the complexity of the 36
Processor Control Processor Control Error Output
I
I I ' I
Parallel Parallel Error
Raslerization - Local Area - � - Reporting Hardware bit DRC Hardware bit Hardware stream stream
Figure 2.17 Seiler's design rule check hardware system (from [3]). process. Software can handle general data management but it is relatively slow w hen processing a large volume of data. On the other hand, hardware can
IT anipulate data very fast but it becomes very expensive when the complexity of the data manipulation increases [3]. In the hardware DRC, the simple data manipulations on large amounts of data are achieved by special purpose hardware wbile the general procedures are implemented by software.
These conditions put a limit on the size and complexity of the layout; the number of rasterization chips; the number of parallel mask data lines; and the number of custom chips in the local DRC unit. However, these are not serious li mitations because the wide layout can be clipped into parallel strips which can 37
be examined individually. By checking one design rule in each pass, the number
of custom chips can be reduced to just enough to handle each design rule.
Similar to Baker and Terman [5], Seiler [3] used three-by-three and four
b -four windows for both orthogonal and angled width checking. Figure 2.18
' ill strates the set of patterns that implement the orthogonal width check. A' 1
in 'cates a position where the mask must be present, a '0' symbolizes a position
were the mask must be absent, and a '-' represents a don't care position. The
m sk passes the width-two check if it matches one of the four orthogonal
ro tions of one of the three-by-three patterns in Figure 2.18. Similarly the mask pa ses the width-three check if it matches one of the four orthogonal rotations of
o of the four-by-four patterns in the figure.
For angled width checking, all edges of the features have to fall on a
Two more patterns illustrated in Figure 2.19 must be pe itted so as to perform the width-two and -three checks. There is a problem
in allowing a 45° bend since the valid patterns in angled width check may
co tradict the ones in the orthogonal width check. This can be avoided by doing
checks. The custom chip for the width check/shrink operation has the fo lowing features:
1) a clocked PLA for implementing the window patterns,
2) four successive rows of mask input lines, 38
3x3 windows
(11) (b) (c)
4x4 windows
- 1 1 1 - 1 1 1
- - 0 - - 1 1 1 - 1 1 1
- 1 1 1 - 1 1 1
- - - - 0 1 1 1
(d) (e) (f)
igure 2.18 Valid 3x3 and 4x4 windows for orthogonal width checking in Seiler's DRC (from [3]).
1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 1 1 a a
(a) (b)
Figure 2.19 Valid 3x3 and 4x4 windows for angled width checking in Seiler's DRC (from [3]). 39
3) five control lines,
4) two error output lines, and
5) two shrink output lines.
The width check/shrink chips can be cascaded to handle larger checks.
The transistor extension rule is a design rule example of the design rule t nat depends on the relative locations of the edges of two different masks. In t ne boundary check, a two-by-two window is used to examine two masks simultaneously. If one of the four rotations of a window pattern is matched, a boundary violation is located. To check the extension of polysilicon past the transistor gate, the hardware has to look for a raster element of the transistor dhannel next to an element which consists neither of diffusion nor of polysilicon.
Similar to the width check chip, the boundary check chip has row inputs and a
] )LA which checks for violations. A dynamic PLA is used in the boundary
(heck chip since there are thousands of different possible combinations.
The hardware DRC can check a 30001.. by 30001.. layout within one minute.
1 Iowever, the speed of the DRC depends on the speed of the controlling
1 nocessor. The DRC allows greater complexity of industrial design rules while
] ireserving the speed and simplicity of the university DRCs. In addition, the total cost of the DRC system is low enough to include in individual IC design workstations [3]. 40
2 . Selected DRC Algorithm for the Hardware DRC
Among all the design rule checking approaches that have been studied, the
metry Analysis Program (GAP) [10] was chosen to be the algorithm for the p oposed hardware DRC. The main attractive feature of GAP is its simplicity.
ike the Fast Algorithms [9] which utilized mixed methods with a considerable n mber of expressions or the approach proposed [8] which involves complicated c culations that are not meant for a graphics system processor, GAP uses i tersection and tolerance which are very easy to associate with the concept of
When compared with the raster-scan method developed by Baker and
T rman, GAP is less likely to have storage problems. In order to implement the
OS3 DLM technology which has 13 mask layers, the raster-scan method has
occupy up to 104 Kilo-bytes of memory for storing valid windows or look-up t bles. This is not practical for the proposed implementation due to the limited
emory space on the hardware. Managing a large volume of information would
so restrict the performance of the hardware DRC. The window comparison in
t e raster-scan methods exercised by Seiler, Baker and Terman [3][5] will not f lly utilize the special features available in a graphics system processor.
Without trading off its simplicity for capability, GAP can examine more
d sign rules than LYRA or MAGIC. Its universal characteristic allows it to 41
a pt to any technology. In fact, the changes needed for different design
1) the distance values in the technology parameter array, and
2) the rule checking routine(s) which involve any additional layer(s).
A secondary attraction is accessibility. The source code of GAP was av ilable; therefore, the algorithm was ready for detail studied without any delay.
has been interfaced to the KIC layout editor which is also available in the
artment. Hence, it is convenient to examine its violation's highlighting on a
GAP can only handle Manhattan-style (orthogonal) mask geometry. This is n t a major limitation since the proposed ORC system is aimed toward university a lications where the Manhattan-style geometry is still widely used
This chapter has briefly described the primary categories of design rules
d the eight ORC algorithms examined in the research. Each ORC approach re resents a slightly different methodology to manage the complexity of design la out; to reduce the number of false/unchecked errors; and to optimize the run ti e. Their suitability for the proposed hardware ORC were evaluated based on 42
th ir simplicity and adaptability to a PC-graphics system processor system. The
G ometry Analysis Program (GAP) [10] was selected and will be described in Chapter 3
GEOMETRY ANALYSIS PROGRAM
3 .1. Introduction
As stated in the objective of the thesis, simplicity and generalization are tNO major factors in the selection of a ORC algorithm. GAP [10] was chosen a fter studying and evaluating several popular ORC methods.
This chapter presents a detailed study of the technicalities in GAP. At the beginning of this chapter, the basic GAP operations as well as the process p attem are depicted with the help of typical examples. The implementation of
GAP under the UNIX operating system and from within the KIC layout editor are then briefly described. That is followed by the CMOS3 design rules which have been implemented in GAP. The final section of this chapter will describe t re selection of the proper graphics system processor for the hardware ORe.
� .2. Geometric Operations
The GAP source code consists a set of geometric operations and a list of functions for data manipulation. Since this research is aimed at handling layouts made up of only orthogonal boxes, the operations which involve polygons are
43 44
n t mentioned here. The following subsections will focus on three general o rations: intersect, tolerance and error reporting.
3 2.1. Intersection
The intersection operation in GAP is the fmding of the intersecting regions o two specific layers. The function call is:
intersect(layer 1, layer 2, layer ii, layer oi)
layer 1 is the input layer 1,
layer 2 is the input layer 2,
layer ii is the II (inside-inside) output layer,
layer oi is the 01 (outside-inside) output layer.
e definitions of the two output layers are
II = {r IrE E (Sc(Ll) fl So(P)) 'V Pi E L2} (3.1)
01 = {r IrE E (Sc(Ll) fl So(P)) 'V Pi E L2} (3.2)
here:
{} represents a set,
represents such that,
fl represents intersection,
'V represents for each, and
E represents belongs to. 45
In the above definitions, L is defined as a set of polygons from an input
each polygon is defined by a set of edges which represent its
GAP defines the intersection operation precisely by declaring two
ind of space associated with a polygon P. namely the open space So(p) and c sed space Se(P). The only different between an open and a closed space of a p lygon is that a closed space represents the points enclosed by the boundary of p and including the boundary itself, while an open space represents the points e closed by the boundary of p only. The polygon boundaries on a set of points, s, are produced by the enclosure operation, E(s), These boundaries circumscribe
e points without cutting across the middle of s. The point-set intersection oration, n, groups all the points common to two set of points. With the given n tations, the definitions can be expressed as:
II layer is the result from intersecting the closed space on layer 1
and the open space of polygons on layer 2.
01 layer is the result from intersecting the area outside the closed
space on layer 1 and the open space of polygons on layer 2.
is considered as the open space of the merged polygons on layer 1, i.e. the p lygons which overlap or butt are replaced by a polygon which encloses the
e space as the original ones. Whereas, the polygons on layer 2 are handled
The significance of handling the input layers separately will be 46
intersection
- - I l I I I [J B c D I I I I I I Legend layer 1
L -- J r-' 2 L __ J layer
Figure 3.1 Intersection and label example.
Intersection also manipulates edge labels, such as the previous edge label, wl ich are attached to polygons and edges. These labels are used to trace back to the violating edges at the end of each design rule checking process. Each intersection output edge originates from an edge on the input layers. The input edge, which an output edge rooted from, is referred to as the parent edge and the output edge is therefore the child of that particular parent edge. Figure 3.1 shows the intersection of layer 1 (solid) and layer 2 (dashed). The edge CD is the child edge for the edge AB. After intersecting the input layers, the name of the parent's layer is assigned to the previous layer label of the corresponding output edge(s). This is illustrated by the combination of solid and dashed edges 47
o the output geometries. The originating edge label, which is initialized to the n e of the edge itself (i.e. edge AB), is also attached to the intersection output e ges. It is then passed onto the child edges after each operation.
A tolerance box is the result of tolerancing an edge. The function call for this operation is tolerance(layer, layer_name, dest, tol). Each tolerance box is
rectangle that contains all the area within a distance, tol, from an edge. The to erance distance can be either positive or negative. In case of a positive
a tolerance box extends outside the associated polygon, whereas for a
distance, the tolerance box extends in the opposite direction. The f nction can either tolerance on the edges from a particular layer or from an in ut layer. These are achieved by assigning the name of the layer or "ALL" to
argument layer_name, respectively. The examples of both cases are shown in
One special property of the tolerance operation is the relationship of the to erance box shape with its adjacent edges. As shown in Figure 3.3, the box is e tended past the end point of the edge by distance tol only if the adjacent edge is to be toleranced. In this way, diagonal spacing is covered. 48
,-l I I
tolerance "ALL-
Legend
D layer 1 r--, ,-l layer 2 L _ _j I I D tolerance
Figure 3.2 Tolerancing examples.
i
A extension T I I Legend i L 1 B layer extension Cl ,-, 2 L. _ _J layer T tolerance (a) (b)
Figure 3.3 Tolerance extensions (tolerance layer 1). 49
to the intersection operation, tolerancing also manipulates labels on
d edges for error identification. One of the labels is the tolerancing
hich is attached to each tolerance box. The name of the edge is
ssigned to this label in the corresponding box and passed on to its children.
Ano er label used in this operation is the projection label. For the edge
f the toler ce box which is the same as the original edge, its projection label i assigned to "original". Whereas, the label of the edge opposite to the original
For the rest of the edges which are not included
o conditions, their projection labels are left cleared. Same as the
projection label is propagated to the children in the
i tersection operation .
. 2.3. Erro Reporting
After performing the intersection and tolerance operations, GAP uses
nctions s ch as read_violationsO and reporu) to trace back to the violating
dges on t e input layers.
The unction read_violations(error_layer, previous_layer) looks through all
segments of each polygon on the error layer whose previous layer
e same as the argument previous_layer. For each such edge,
ad_violati nst) provides an error record consisting of the related original edge
1 bel and t lerance edge label. The function report(layerl, layer2, layer3, side, 50
delta) is a combination of intersectt), toleranceO and read_violationsi). This function reports all violations caused by layer 1 edges whose previous layer label ec uals layer 2, and are less than delta from the boundary of a layer 3 box.
3.3. DRC Oberations
The sequence of operations GAP uses for design rule checking falls into the followin pattern:
1) intersects the layers involved in the rule,
2) tolerances one of the resulting layers from (1),
3) produces an error layer by intersecting the tolerance boxes with one
of the input layers, and
4) studies the labels on the error layer to identify the violating edges.
In order to illustrate how GAP functions, the 5 urn polysilicon extension e} ample used by Mowchenko [10] is explained in full detail here. The function cs lIs for checking this example are as follows:
step 1 : intersect (pOLY, DIFF, TEMPI, TEMP2)
step 2 : tolerance (TEMPI, DIFF, 5, TEMP3)
step 3 : intersect (pOLY, TEMP3, NULL, ERROR)
step 4 : read_violations (ERROR, POLY)
Figure 3.4 depicts the layers involved in step 1. The polysilicon and diffusion layers are shown in dashed and solid outlines, respectively. These 51
la vers are intersected to generate two output layers, TEMPI and TEMP2. The previous layer label of each edge in TEMPI and TEMP2 is represented by its ccrresponding line type. In addition, the original edge label is marked on the or tputs. For simplicity in this example, new edge names are not assigned to the in ersection output. This step basically extracts all transistor gates from the la vout and stores them in TEMPI. All the edges with diffusion as their previous la ver label are toleranced by 5 microns in the next step.
TEMP3 in Figure 3.5 is the tolerance output layers. TEMP3 is then in ersected with the polysilicon layer to produce the 01 layer in ERROR as illustrated in Figure 3.6. The labels on the error polygon are studied in the final step. The tolerance edge label of the box in ERROR signifies that the edge CD is associated to the violation. To identify the error edge on polysilicon, read_violationsO goes through all the output edges looking for the edge whose previous layer label is polysilicon. In this example, the edges GH and CD are the violating edges from the input layers and are stored in an error record. 52
Input layers before intersection
A D
E H 1------, I I L _j r G
diffusion (DIFF)
- - - polysilicon (POLY)
B C
intersect (POLY, DIFF, TEMP1, TEMP2)
TEMPl
BC
TEMP2
Figure 3.4 Polysilicon extension rule check example (step 1). 53
tolerance(TEMP1, DIFF, 5, TEMP3)
TEMP3
projected original projected l---Jl---J AB CD
L .J I'"
5 microns 5 microns - - - tolerance (TEMP3)
Figure 3.5 Polysilicon extension rule check example (step 2).
E H 11--'- -1,-' I I I I I I AB I I c� I I I I I
L -'- _ __J __ ...L_j _.J F G
- - - tolerance (TENP3) - - polysilicon (POLY)
intersect(POLY, TEMP3, NULL, ERROR)
ERROR r' projected � : r �ICD:__; L.J
Figure 3.6 Polysilicon extension rule check example (step 3). 54
3 . Examining GAP
GAP consists of two commands: GAPDRC for the design rule checker and
for the error ennunicator. In order to gain a better idea how these c mmands work, GAP 3.1 was first run under the UNIX operating system. It
as then interfaced with the KIC layout editor so as to see the highlighting of
e violations on the graphics display.
3 4.1. Running GAP under UNIX
The two GAP executable commands (GAPDRC and EN) were generated u der the UNIX 4.0.1 operating system using the makefile in the GAP source
ectory. Multiply defined errors were encountered during this process. This p oblem was overcome by removing the two duplicated dependents in the
. o gina! makefile. After producing the executable commands, the CIF files in the
AP test directory were used to examine GAPDRC. However, GAPDRC failed
recognize two commands, namely OA and OS, in most of the test files.
T erefore, instead of using those files, simple test files were created using KIC.
fter running GAPDRC on the new test files, the rule violations are written in b nary files located in the working directory. EN was invoked to display the t pe and general location of the errors in the files, GAP reports only the mid pint of each violating edge. The result was then verified by locating the error pints in the KIC environment. 55
3.•2. Running GAP from within KIC
After retrieving the proper makefile and regenerating some executable files in KIC, the next process was to interface GAP with KIC to generate the new v sion which is named GAPKIC. The first interfacing attempt was to compile
into KIC as if it was one of the edit commands. But after learning that
creates a separate process to run GAPDRC at the background, the proper
KIC makefile was generated. "GAp" and "ENnunc" were then added to the
C edit menu. In GAPKIC, a window must be specified after invoking "GAp".
Ten, "ENnunc" has to be selected to view the highlighting and error message of e h individual violation. The performance of GAP was observed and the al orithm was proved to give promising results.
3.• Design Rules in GAP
A technology file is a file which lists all the technology dependent features o a particular rule set. According to the original paper [10], only the Northern
T lecom CMOS1B technology has been established A CMOS3 technology file w s found among the source files which implies it has also been implemented.
The GAP CMOS3 technology file in Appendix B consists of the function c Is for checking 27 design rules as listed below:
1) spacing on individual layers,
2) minimum dimensions on individual layers, 56
3) N+ to P+ spacing,
4) device well spacing (between device wells with different doping),
5) transistor rules (eg, properly formed gate),
6) gate overlap onto field oxide,
7) device well to polysilicon spacing,
8) P well oversize on active channel,
9) P well oversize on non-active device well,
10) P+ overlap of device well,
11) N+ to field spacing,
12) N+ to polysilicon spacing in device well,
13) device well overlap of contact cut,
14) device well contact to gate spacing,
15) metal overlap of contact cut,
16) polysilicon overlap of contact cut,
17) metal 1 enclosure of via,
18) metal 2 enclosure of via,
19) via to device well spacing,
20) via to polysilicon spacing,
21) maximum contact cut dimension,
22) P guard overlap of P well,
23) P guard to N guard spacing,
24) P well to P+ diffusion spacing, 57
25) P well to N+ diffusion spacing,
26) split contact cut to P+ spacing, and
27) split contact cut to N+ spacing.
3 6. Hardware Selection
Since the Texas Instruments TMS3401 0 Graphics System Processor (GSP)
already available in the Electrical Engineering Department, it was the first
aphics chip being considered to perform the hardware design rule checking.
T e TMS34010 belongs to the TMS340 family of computer graphics product
m Texas Instruments. It is a 32-bit CMOS microprocessor which can provide h gh-capability bit-mapped displays.
The graphics processor has a comprehensive general-purpose instruction set
d a set of graphics primitives which allow the user to construct efficient high
I vel graphics or non-graphics functions. The instruction set includes 22 Boolean
d arithmetic operations, data moves, conditional jumps, subroutine calls and r turns, and window clipping and checking. In addition to single pixel o rations, the TMS34010 also includes pixel block transfers (PIXBLTs) which
e a set of efficient two-dimensional data manipulation instructions. PIXBLTs i corporated with the pixel processing operations become a very powerful multi
In addition, the GSP also accepts interrupt requests 58
In addition to the broad sense of programmability, adaptability is also an a tractive attribute of the TMS34010. Its architecture supports a variety of pixel si es, frame buffer and screen sizes hence it is not tied to a particular display
Therefore, this enhances the portability of the graphics software and
TMS34010 to accommodate a wide range of industry and display
anagement standards [11].
Texas Instruments fabricates three models of TMS34010 (TMS34010-60,
S34010-50, and TMS34010-40) and the one available in the department is a
S34010-40. It has an instruction cycle time of 200 ns which is faster than
ost graphics controllers. The TMS34010 is inexpensive thus provides a cost e fective solution in applications that require efficient data manipulation [11]. It i well-supported by a full line of hardware and software development tools
hich come in the form of a full-speed emulator, a software simulator, an IBM
development board, a C compiler, predeveloped software libraries, and
The TMS3401 0 is a new generation of graphics microprocessor because it
capabilities far beyond other commercial general-purpose processors and
That is why it is becoming the industrial standard in c mmercial graphics applications. Since the TMS34010 is a graphics processor, o e can observe its operations through a display terminal. This becomes an ideal
:£ ature for the design rule checking implementation. With the programmability, 59
c pability and adaptability, the TMS34010 seems to be the ideal graphics p ocessor for the research. To avoid overlooking other options. the investigation
d not stop at the TMS34010. The NEC J.1PD7220A Video Graphics Controller
d the Intel 82720 Graphics Display Controller were examined Since these two
are virtually identical. only the NEC J.1PD7220A will be
The J.1PD7220A High-performance Graphics Display Controller (HGDC) is
work with a general-purpose microprocessor to establish a high
raster scan computer graphics and character display system.
graphics capabilities consist of figure drawing (including lines.
c/circles, and rectangles) and graphics characters. it does not include drawing s lid-filled geometries. A single pixel is processed individually at a rate of 500 n per pixel which make it slow for pixel manipulation. In addition. the c ntroller is restricted to 1024 by 1024 4-bit pixels (color or grayscale) display r solution. The J.1PD7220A performs a read-modify-write cycle similar to that of
e TMS34010. However. the graphics controller performs only four Boolean o rations (REPLACE. COMPLEMENT. SET. and CLEAR) and does not include
ithmetic operations which are so useful for manipulating color pixels. It does n t accept interrupt requests from external devices which makes it impossible to c mmunicate with hardware other than the ones it is designed to work with. 60
The difference between the TMS34010 and the )lPD7220A is analogous to
at between a fixed-function calculator and a computer. The calculator performs o y those commands that are built into it, while the computer can be p ogrammed to perform new tasks [12]. The TMS34010 is the obvious choice si ce it provides a large degree of flexibility required for the processor to p rform a task it does not intend to accomplish.
This chapter has presented a detailed description of GAP. The basic GAP f nctions - intersecu), tolerancet), read_violationsO and reporn) were described
d the associated labels were covered The operation of these functions were s mmarized by a step-by-step illustration of the polysilicon extension rule check.
T e performance and error reporting of GAP were observed under the UNIX and
C environment. The focus was then switched to hardware selection. The f atures of the Texas Instruments TMS34010 Graphics System Processor were b iefly described. Even though the TMS34010 provides attractive attributes such a programmability and adaptability, two other graphics chips were studied to e sure the most suitable chip was selected. The TMS340 1 0 was the final choice,
d it will be described in more detail in Chapter 4. Chapter 4
TMS34010 GRAPHICS SYSTEM PROCESSOR
4 1. Introduction
The TMS34010 Graphics System Processor (GSP) belongs to the TMS340
f ily of computer graphics products from Texas Instruments. It is an advanced
h gh-performance 32-bit CMOS microprocessor which combines the best features o general-purpose processors and graphics controllers into a powerful GSP that
is optimized for bit-mapped graphics systems. It has virtually unlimited p ogrammability which makes it suitable for many different graphics and non-
aphics applications. Therefore it may very well serve as the main processor of
a small computer and manage its graphics as well. A single TMS34010 provides
a cost-effective solution in applications that require efficient data manipulation
[ 1].
The TMS34010 has a fully programmable 32-bit general-purpose processor
128-Megabyte address range. With a full 6 million-instruction-per-second
S) general-purpose instruction set that supports high-level language, a
p werful set of graphics instructions (include 6 arithmetic and 16 Boolean pixel
p ocessing, xy addressing, window checking), a built-in 256-byte instruction
61 62
c he, the ability to simultaneously access memory and registers, the TMS34010 pr vides user-programmable control of the CRT interface as well as the memory in erface (both the conventional DRAMs and the multiport video RAMs).
U 'que among today's microprocessor, the 1 Giga-bit address space is completely bi -addressable on bit boundaries using variable width data fields rather than the c mmon byte or word addressing [12].
The main features of the GSP are its speed, programmability, and efficient
ipulation of hardware-supported data types such as pixels and two
pixel arrays. Portability is also an important characteristic of the
Its graphics addressing modes allow 1, 2, 4, 8, and 16-bit pixel
and screen , and the design architecture provides programmable frame buffer
In addition, the on-chip functions are selected carefully so that they do not
the GSP to a particular display resolution. The TMS34010 is well s pported by graphics software interface standards such as CGINDI, ooIS, and
S-Windows, and a full line of hardware and software development tools
1) C compiler,
2) macro assembler,
3) linker and archiver,
4) software application libraries,
5) XDS (Extended Development Support) in-circuit emulator, 63
6) Software Development Board (SOB),
7) ROM utility,
8) simulator, and
9) symbolic debugger.
This chapter begins by providing an overview of the architecture, i struction sets and applications of the TMS34010. Three graphical features of
in more t processor which will be used frequently in the research are described d tail. In the remaining of the chapter, the TMS34010 is addressed as the GAP
for h dware DRC processor. The important attributes which made it suitable i plementing GAP are discussed in detail.
4 2. Design Architecture
The TMS34010 used in the research is a TMS34010-40 with an instruction
c cle time of 200 ns which is housed in a 68-pin PLCC package. It is driven
a 40 MHz input clock and this frequency is divided by 8 inside the
icroprocessor to provide the machine state rate that execute more than 6 MIPS
Figure 4.1 illustrates the major internal functions and its
i terfaces to external devices. In addition to the on-chip graphics processor, the
S34010 has peripheral functions such as:
1) programmable CRT timing control (horizontal and vertical sync, and
blanking), 64
Pnlgram anc! Dale Sl«age � ,------1 hoBl- graphics .....--..... '.COnwalionlll grapbics I DRAIis interlace procellOl' I
I Frame Buffer
DlWI- SelneR- To CRT Re1nlh Refresh ConLrol Coalrol Control monilor L-l",-cmp_----
Figure 4.1 System block diagram (from [11]).
2) direct interfacing to conventional DRAMs and multiport video
RAMs,
3) automatic CRT display refresh, and
4) separate physical interfaces for direct communications with an
external (host) processor.
The internal architecture of the TMS34010 is summarized in Figure 4.2.
It core components are: 65
I����l------� JDteJTIIP\ 1 Repte... I I -l 1 I I
----ISt.a�1III I Repter -----II I lliA:racaatnli I ALU '- _.t I RON I 1.----..... 1 I
Repter...... I I
I Steak Painter 1 1 L J 1 BxeouUaa Ualt Clack Internal Claak Outputs Clrvultr7 Clack InplIUI
______J
Figure 4.2 Internal architecture block diagram (from [11]).
1) 28 16-bit programmable I/O registers that contain CRT control,
input/output control, and instruction parameters,
2) a 256-byte instruction cache that can contain up to 128 instruction
words,
3) microcontrol ROM (with 166 control outputs and 808 microstates)
that controls all of the hardware in the CPU, and
4) register files A and B.
The architecture is a combination of the RISC (reduced instruction set c mputer) and CISC (complex instruction set computer) approaches. Adopting the 66
ideas in the Berkeley RISe, the GSP has simple direct-instruction decoding, a la ge register file, low instruction pipelining for fast jumps, move-to-register instructions that either zero- or sign-extended to 32 bits, and fast register-to register operations. The else characteristics in the GSP are multiple-cycle instructions such as multiplication, division, and the very complex PIXBLT (pixel block transfer) instructions; pipelining writing to memory operations; memory-to memory move instructions; and a wider selection of addressing modes [12].
4.3. General-Purpose Instructions Overview
As mentioned earlier, the full set of general-purpose instructions of the
TMS34010 are designed to support a complete programming environment and the me of high-level language. Due to its bit-addressing feature, all memory
0] �erations involve field extraction and/or insertion. A field is defined by two parameters:
1) starting address which can begin on arbitrary bit boundaries within a
memory word, and
2) field size which can range from 1 to 32 bits.
II the memory-to-register operation, the field is right-justified and then either sign- or zero-extended to 32 bits. The time required to extract or insert a field depends on the way the field is aligned in the memory. If the field is stored in 67
a way that it does not cross word boundaries, the field manipulation is more r pid.
The TMS34010 supports a variety of MOVE instructions, allowing the user
move immediate values into registers, move data between registers, and move d ta between registers and memory. Its five addressing modes used in the i structions clearly show the register-based nature of the processor, the addressing
1) register indirect,
2) indirect predecrement (by the field size),
3) register indirect postincrement (by the field size),
4) register indirect with displacement, and
5) absolute addressing.
The TMS34010 also supports a full range of 32-bit or 64-bit integer
. thmetic, logical, and compare instructions. The arithmetic instructions include a dition, subtraction, add with carry, subtract with borrow, and signed and u signed multiplication and division. The 32-bit barrel shifter and sign control
utilized to perform several instructions that left-rotate, left-shift, or
the contents of the destination register by an amount specified in a s urce register or a constant. 68
The program flow in the TMS34010 is managed by the program control
d context switching instructions which allows:
1) the use of conditional jumps,
2) subroutine calls and returns,
3) hardware interrupt enabling/disabling,
4) control over 32 software interrupts using a TRAP instruction,
5) setting, saving, and restoring program counter (PC) and status
register (ST) information, and
6) setting of the field size and field extension control.
4. . Graphics Instructions Overview
The TMS34010 graphics instruction set is a set of graphics primitives
. ch can be used to construct customized and efficient high-level functions for
specific display configuration. The PIXBLT and FILL instructions
ipulate pixel arrays. The LINE instruction can draw one-pixel-width lines
The DRAV (draw and advance) instruction draws a pixel and
the pixel address by a certain amount. It also supports the i plementation of incremental algorithms for drawing circles, ellipses and other
The PIXT (pixel transfer) instruction transfers individual pixels 69
Several useful pixel processing operations are included in the TMS34010 in truction set. There are Boolean and arithmetic operations for combining the so rce and destination pixels, plane masking for masking the pixel read/write o erations, and transparency for permitting objects written onto the screen to h e transparent regions through which the background is visible. These o erations can be used in combination with any of the graphics drawing o erations mentioned above. The value of the source pixels will first go through
processing procedure and then transfer to the destination.
In the windowed graphics environments, the TMS34010 supports four
window checking features. The "window checking disabled" option ig ores the window boundaries and no pixels are protected. The "window cl pping" option clips a figure to fit a rectangular window. The "window miss d tection" option enables request of an interrupt when the TMS34010 attempts to w ite outside a window. The "window hit detection" option enables request of
interrupt when the TMS34010 attempts to write inside a window. The
S34010 also supports rapid detection of whether a point, or line, is inside or c mpletely outside of a window.
4. .1. Pixel Block Transfers
Pixel Block Transfers (PIXBLTs) is a powerful set of raster operations that m es the TMS34010 stands out from other graphics controllers. This feature 70
s ports an efficient way to manipulate two-dimensional arrays of pixels which
defined by four parameters:
1) a starting address in linear or XY addressing mode (the default
value is the lowest address of the array),
2) a width DX (the number of pixels per row),
3) a length DY (the number of rows of pixels), and
4) a pitch (the difference between the starting addresses of two
successive rows).
All PIXBLT instructions are two-operand operations which support c mbining two pixel arrays of the same dimensions (source and destination
ays) using operators such as the Boolean and arithmetic pixel processing,
sparency, plane masking and window clipping options. Figure 4.3 illustrates
read-modify-write operation of the PIXBLT instruction. An important feature o the PIXBLT instruction is that the two arrays may have different pitches.
ith this option, the processor can pack the bits differently in the source and d stination arrays to allow efficient storage of characters and objects off screen.
T e FILL instruction is a special type of PIXBLT that does not use a source pi el array. It fills a specified destination array with the pixel value assigned to
COLOR1 register. 71
operand 1 operand 2
source destination pixel pixel array array
result
Figure 4.3 Two-operand PIXBLT operation (from [12]).
4 .2. Boolean and Arithmetic Operations
The TMS34010 supports 16 Boolean operations and 6 arithmetic operations
. ch can be applied to either a single pixel or an array of pixels. They c mbine the corresponding bits of each pair of the source and destination arrays o a bit-by-bit basis according to the specified operator. The operator of a pixel p ocessing option is represented by a 5-bit PPOP code. Table 4.1 lists the 22
OP codes and their meanings.
The simple addition and subtraction (PPOP code 16 and 18) are different fr m those with saturate in PPOP code 17 and 19. The simple addition and 72
Table 4.1 PPOP Codes for Boolean and arithmetic operations (from [11])
Code Replace Destination Pixel with : Code Replace Destination Pixel wilh :
0 source 11 source AND destination
1 source AND destination 12 all Is
2 source AND destination 13 source OR destination
3 all as 14 source NAND destination
4 source OR destination 15 source
5 source XNOR destination 16 source + destination
8 destination 17 ADDS(source, destination)
7 source NOR destination 18 destination - source
8 source OR destination 19 SUBS(destination, source)
9 destination 20 :tlAX(source, destinalion)
10 source XOR destination 21 :tlIN(source, destinallon)
st btraction are complementary and reversible operations. By adding a source to a destination, then subtracting the same source, the original destination array can be recovered. When the sum of the two pixels exceeds the largest pixel value, the result overflows. Whereas, when the calculated difference is negative, the result underflows. In case of addition and subtraction with saturate, the overflow re sult is assigned to the maximum unsigned pixel value and the underflow result is assigned to zero.
During the MAX operation, two pixel values are compared and the destination is replaced by the larger value. It can be used to replace the pixels o the destination array whose values that are lower than those of the 73
esponding pixels in the source array. Conversely, the destination pixel is re laced by the smaller of the two pixel values in the MIN operation.
The plane mask is a hardware mechanism for protecting some or all of the bi s within a pixel from any alterations during graphics instructions. In order to d scribed the plane masking more precisely, bit planes (or color planes) have to
introduced. Figure 4.4 shows the organization of the TMS34010 screen m mory with 4-bit pixel size. The bits within each pixel are numbered 0-3
( om the LSb to the MSb) and belonged to plane 0-3, respectively. These
es are referred to as the bit planes.
The plane masking operation allows one or more planes to be manipulated in ividually without modifying other planes. For the example shown above,
ee of the planes can be used for eight-color graphics and the fourth plane can
saved for single-color text. With the plane mask, the graphics and text can
modified independently. To protect the specified planes, the corresponding bi s of the plane mask in the PMASK register have to be set to 1. For the u protected planes, the corresponding bits should be set to Os. The plane m sking applies in both read and write operation. In a pixel read cycle, those pi els from the protected plane are always read as Os. While during a pixel w ite cycle, the protected bits are not altered The TMS34010 does not have a 74
Organization of the screen memory with 4-bit pixel size (from [11]). c ntrol bit for enabling or disabling the plane masking. However, the operation c be disabled by simply setting PMASK to all Os,
4•• Applications
Since the TMS34010 has a complete set of general-purpose instructions and a powerful set of graphics operations, it can handle both graphics and non-
phics applications. These include display systems, imaging systems, mass st rage, communications, high-speed controllers, and peripheral processing. The hi h-performance bit manipulation of the TMS34010 allows it to manage tasks s ch as desktop publishing which requires high-quality, proportionally spaced 75
Table 4.2 Typical applications of the TMS34010 (from [11])
computers los1W1trial CQn�l
terminal and CRTs robotics
windowing systems process control
electronic publishing instrumentation laser printers motor control personal computers navigation printers and plot.ters engineering 'Workstations I;tgnlymgr �le�t.ronic9 copiers automotive displays
document readers information terminals
FAX cable TV
Imaging home control
data processing video games
Telecommunicayol!! video phones
PBX
As already mentioned, the processor provides a cost-effective performance f r color or black-and-white bit-mapped displays [11]. Table 4.2 lists the typical a plications of the TMS34010.
46. TMS34010 as the GAP Hardware DRC Processor
As already pointed out in Chapter 2, one of the driving forces behind the d velopment in DRC is to improve the run-time. In order to maintain reasonable seed while checking large layouts, a hardware DRC processor must be able to 76
dle a large volume of data efficiently. Since IC layouts are mostly composed o rectangles and polygons, the TMS340l0's PIXBLTs provides the efficient
eans to manipulate the layout geometries as arrays of pixels. Note that only r tangular boxes are considered in this research. The boxes in each mask layer
be drawn to the screen using the graphics function in the TMS34010
apbics function library called fill_rect(width, length, xleft, ytop). The four
guments specify the dimensions and the xy coordinates of the upper right
c mer of the box are referred as the TMS340l0 box data format in this thesis.
It solid-fills the specified rectangular area on the screen with the current color
c de in the COLORl register. The display is similar to that of an IC layout
. e tor. Since ClF stores box in form of its width, length, and xy coordinates of
t e box center, data translation routine is needed to convert them to the proper
In addition to PIXBLTs, bit plane is also a feature for implementing GAP.
T e bit planes in the display memory are analogous to the mask layers in an IC
d sign layout. In case of the CMOS3 DLM technology, there are a total of 13
ask layers. However, it is impractical to store all mask layers in separate bit
only a maximum of two layers are used for each geometric
o eration. With the increasing amount of layers in the latest IC technology, the
c nvenience of having the information of all mask layers at hand can only be
a hieved at the expense of more display memory or low display resolution. 77
Programmable pixel size provides the flexibility to select the number of bit
es required to carry out the design rule checking. For example, if the pixel
is set to four bits, two of the four planes can represent the two input layers
(1 yer 1 and layer 2) of intersecu) in GAP, while the remaining two can be used
planes for layer manipulation or output layers of the geometric
If one disregards that GAP treats the input layers of intersect() differently, la er ii is actually the result of logical-ANDing the input layers, and layer oi is th result of logical-ANDing NOT-layer 1 and layer 2. Along with plane m sking, the Boolean and arithmetic operations of the TMS34010 are the best fit fo this application. Since GAP uses the input layers more than once in a rule c ecking process, the output of intersect() and toleranceO must reside in other bit pl es so as to preserve the input planes. This can be achieved by a series of pi el processing operations with plane masking. With the output layer stored in a different plane, the generation of error boxes by intersecting the tolerance
xes and an input layer can be easily implemented Plane masking also allows
of information from the resulting layer(s) of the GAP geometric 78
4. .1. The TMS34010 Software Development Board
The implementation of GAP is made possible only with aid from the
S34010 Software Development Board (SOB). It is a high-performance, p rsonal computer based graphics card ideal for testing and developing
S34010-based graphics systems.
The graphics SOB consists of the TMS34010 GSP, the TMS34070 Video
ette, and the TMS4161 Multiport Video RAMs. The board and demo
monstration and tutorial) software are configured to support a 640-by-480
However, its 256 Kilo-bytes frame buffer is capable of s pporting a maximum resolution of 1024 by 512 pixels with 4 bits per pixel.
T e board also contains a 512 Kilo-bytes program RAM for the GSP to execute
awing functions and application programs. Both the program RAM and frame
accessible to the host through the memory-mapped host port. The
debugger software that comes with the SOB has more than 60 s ftware development commands such as display memory, software breakpoints,
d run-with-count. At the same time, the current machine status is displayed on
host monitor.
All ORe operations developed in this research are tested on the SOB. The
ard has direct interface to most digital and analog RGB raster-scan monitors.
this research, an AEO graphics terminal (which is an analog RGB monitor 79
a frame rate of 60 Hz) is interfaced with the SDB since it is also available in the department. Through the AED terminal, the DRC operations performed by th TMS34010 can be observed Since the TMS34010 C compiler does not
su port any standard I/O functions, the visual display is a crucial feature for
de ugging the software associated with the hardware DRC.
4.. Summary
This chapter has provided an overview of the TMS3401 O. The features
characteristics of the TMS34010 internal architecture were described. Both
general-purpose instructions and the graphics operations were briefly covered.
BLTs, Boolean and arithmetic operations, and plane masking are the
op rations which will be frequently used when implementing GAP. The typical
gr phics and non-graphics applications of the TMS34010 are then listed. This
to the brief discussion of the TMS34010 features which can be used to
i plement the steps in the GAP geometric operations. The chapter concludes
with the introduction of the TMS34010 Software Development Board. Chapter 5
SOFTWARE DEVELOPMENT
s. . Introduction
In order to investigate the feasibility of hardware design rule checking us ng the TMS34010, the GAP design rule checking operations were i plemented using the TMS34010 graphics instructions. GAP was customized d ring the incorporation of its geometric primitives with the TMS34010. The al erations eliminated unnecessary definitions in GAP, thus resulting in a simpler
The reasoning behind this alteration will be discussed using the p lysilicon extension rule example. The remainder of the chapter is addressed to th logic behind the software developed in the research. Since the software ro tine listings occupy approximately 85 pages, they are presented in a separate
s. . Implementation of the GAP Functions
Mowchenko listed the pseudo-code of several rule checks in the original
These rules include inter-layer and intra-layer spacing, o erlap, minimum dimension, and the polysilicon extension. The function call s uences for these rule checks are built with the four basic functions described
80 81
in Chapter 3. The actual call sequences for the design rules listed in Section
3. are contained in the CMOS3 technology file in Appendix B. The functions u ed in this file are more elegant than that in the pseudo-code. However, due to th ir simplicity, the sequences in the pseudo-code were first to be analyzed and i plemented. By using the basic building blocks created during the preliminary i plementation, other rules in the technology file were then created. In the
were developed with a set of general function calls.
1) minimum dimensions of composite structure i.e., transistor,
2) minimum dimensions on mask layers,
3) minimum polysilicon/diffusion extension past transistor gate,
4) intra-layer spacing,
5) inter-layer spacing, and
6) enclosure.
5. .1. Customization of GAP
Since neither GAP nor the TMS34010 is intended to perform hardware d sign rule checking, it is obvious that there was need for customizing the al orithm so that the resulting hardware DRC can benefit from the TMS34010
aphics features. On the other hand, the TMS34010 might require custom-made h dware to optimize its performance in some unconventional tasks. 82
The examination of the compatibility of the TMS34010 and GAP began by c nsidering the significance of handling the input layers of the intersection f nction differently. As pointed out before, GAP defines layer 1 as the merged la er of all the geometries from layer 1; while layer 2 is a set of individual g ometries which belongs to layer 2. Prior to the design rule checking, the i ormation of the input layers has to be loaded into the SDB display RAM.
T erefore, no matter how the layers are treated, the result will be two bit planes c ntaining the boxes from the corresponding layers. This clearly shows there
no need to differentiate between the inputs and both can be considered as
merged layers of all the boxes from the assigned mask layers. This also i dicated the hardware DRC is layer-oriented rather than object- or edge-oriented.
Mowchenko specifically stated the difference between the open space and
c osed space of a polygon in [10]. However, no clear explanation is given on
definitions are required The open space of a box can be
r garded as the outcome of shrinking the box by the amount taken up by its
Since the TMS34010 does not support such shrinking operation, it
h s to be performed by a software routine. Using a one-pixel box boundary, the
p ocessor can determine the open space by simply reducing the width and length
o the box by two pixels and repositioning its corner coordinates. Nevertheless,
t 0 difficulties arose from this notion. First, with the large volume of boxes
i volved in the design rule checking procedure, this software shrinking can be 83
dislorlion
1----, ----_j Il I I Legend I I D original I I - r- -, I shrinked LJ L __ J
Figure 5.1 Possible distortion due to box shrinking operation.
and time consuming. Second, this operation can distort the ori inal geometries. It is important to keep in mind that the TMS34010 is only
onsible for boxes, thus adjacent boxes are not merged and the common edges
these boxes are not removed as in the GAP enclosure operation. As an
pIe, Figure 5.1 shows two perpendicular boxes forming a wire with a 900 be d, By shrinking the boxes, the wire is split, leaving a two-pixel wide gap in be ween. This distortion can lead to false errors such as intra-layer spacing.
To fully understand how open space works on the screen, the polysilicon ex ension rule was studied once again and this time a graph paper was used.
T investigation can be broken down into two steps. First, the complete 84
operations was performed using one-grid boundary for all la ers, and each step is pictured in Figure 5.2. Note that the transistor gate st red in TEMPI does not have the correct width and the error box in ERROR d s not match with the missing chunk on the polysilicon layer. Second, the a ve process was repeated using the closed space of both input layers for the
Figure 5.3 illustrates all the steps in this trial. The vi lation on polysilicon can be identified as in the first case. In addition, this ap roach removes the ambiguousness in the output layer representation in the in ersection process. As shown in the figure, the transistor gate in TEMPI and th error box in ERROR are representing the true dimensions.
The analysis showed that there is no need to classify the input layers of
intersection function during the implementation. This modification overcame
difficulties mentioned earlier and resulted in a further simplified algorithm.
87
s. .2. Display and Intersection
Bit planes 0 and 1 of the SDB display were chosen to represent layer 1
layer 2 of the intersection process, respectively. The output layer which is us d as the input for the next procedure is stored in bit plane 2. If the bit pl es are treated as color planes, then layer 1 is represented by red (OOOl:z), la er 2 is represented by green (00 1 O:z), and the output layer (either II layer or o layer) is represented by blue (OlOO:z). A complete list of the SDB default c lors for analog RGB output is shown in Table 5.1.
Table 5.1 The SDB default colors for analog RGB output
Pixel Value Color Pixel Value Color
0 black B black
1 red 9 light red
2 green 10 light green
3 yellow 11 light yellow
4 blue 12 light blue
5 magenta 13 light magenta
6 cyan 14 light cyan
7 white 15 gray 88
Since the boxes from each input layer are loaded directly into the SDB sc een memory, the display routine is correlated to the first geometric operation - int rsection - for each rule check. In the implementation, the intersection op ration was embedded in two functions rather than having a single function as in GAP. The first function is the routine which displays the boxes on the input la ers based upon a set of box data. The second part is to move the required
ou ut layer to bit plane 2.
For the rules that involve only one layer such as the intra-layer spacing
minimum dimensions, the mask layer is treated as layer 2. It is important to
no ice that the Clf description generated from a layout created by a silicon
co piler consists of a large number of overlapping boxes. Therefore, instead of
us ng the large volume of the original box information, it is preferable to break
displayed geometries down into boxes and extract information from these
es for further use. The procedure is best described by the illustration shown
With this extra step, the number of boxes can be reduced
dr stically. This step is performed by a scanning routine developed for searching
es on bit plane 2. In order to move the boxes from bit plane 1 to 2, all
gr en pixels are changed into blue by doubling the pixel value at the beginning
of the rule check main routine. This procedure can be included in the display
this restricts the use of the display routine for other 89
t t box T b�x box 2 .t, 1 ...... Tbox t 3
box 2
- _l
Before scanning After scanning
Figure 5.4 Reduction of box number by re-scanning after display.
A second display routine was developed to handle two mask layers. The r utine displays the input layers and then converts the II layer into white (Ol ll).
F gure 5.5 shows the block diagram of this display routine. For those rules that u e the II layer, the MIN (minimum) pixel processing operation with the
register set to blue is used at the beginning of the rule check main
This converts the white pixels into blue which has a smaller pixel
A longer sequence of pixel processing operations is used to get the 01
I As shown in Figure 5.6, the procedure used a combination of pixel p ocessing operations to change the 01 layer to blue, keep layer 1 in red, and t e intersection in white. Minimum transistor dimensions is a special case of 90
draw layer 1 boxes (pixel value = 00012) draw Jayar 2 boxes (pixel _lue - 00102)
... U layer pixel _lue - 00I�
laytlr 1 pixel = 00012 - - - ... layer 2 pixel - 0010 screen result U layer pixel .. 0111:
Figure 5.5 Block diagram of the two-layer display routine.
miLialiae 1IGn_ ooDcliUaaa
Ia,.r 1 pi_I - 00012 layer a pi:ol .. 001� II layer pI:ol - 01112
double aU pl_t _1118.
- - - - -. layer 1 pi_I .. OOlla layer 2 pial = 01002 '1 II .. 1111 layer pixel 2 clear plane I I I - - - - -. layer 1 pi_I .. 00012 2 '"' layer pi:ol 01002 Icreen oheck .U pixel II layer pl:ul '"' 11012 reault. valu•• > 01112 to � Lo Mllf 01112 by I
- - - - -. Ia:rer 1 pi_I .. 00012 I layer 2 (O[ layer) plxel .. 01002 II layer pi:ol '"' 01l� )
F gure 5.6 Block diagram of the outside-inside intersection procedure. 91
m nimum dimensions rule since the input is a composite layer. In order to use th same routine for single-layer minimum dimension rule check, the transistors
( hich are the II layer of polysilicon and diffusion) have to be extracted and th n inputted to the minimum dimensions routine as layer 2. This is handled by a slightly different set of operations. Since the basic principle used is similar to th se described in Figure 5.6, the sequence of function calls is not presented here
(r fer to the listing of the main routine of the transistor dimensions rule check,
_sizeO, in the supplementary report [14] for a full description).
The final result of the display and intersection operations is summarized as fo lows: For single-layer rules, the boxes from the input mask layer are moved to bit plane 2 (blue). For two-layer rules that use the II layer, the boxes from la er 1 remain in bit plane 0 (red). the boxes from layer 2 remain in bit plane 1
( een) and the II layer is stored in bit plane 2. For the rules that use the 01 la er, the boxes from layer 1 remain in bit plane 0, the 01 layer is moved to bit pl e 2 and the II layer remains white.
A general screen scanning mechanism was developed to perform tasks such a :
1) re-collect input box information in single-layer rule checks,
2) extract box information on the II layer, 92
3) extract box information on the 01 layer, and
4) extract error box information.
A I boxes in each task have to be moved to a specific plane prior to the sc ning process. Since the boxes in the first three tasks are already in bit plane
2, blue is chosen to be the target pixel value for the screen scanning.
The scanning routine was first implemented by checking the screen from
to bottom, left to right, one pixel at a time. The process stopped when a bl e pixel was encountered. Then the adjacent pixels were checked to determine if the blue pixel represented the upper left comer of a box. The coordinates of
pixel were then recorded. The width and length of the box were determined b scanning along the top and right edges until a non-blue pixel was detected.
was then removed from bit plane 2 and the scanning process was
This proved an inefficient way to check the screen, especially when
Moreover, scanning along the top and right edges did not gather su ficient information to prove that the geometry encountered was indeed a box.
A typical screen is refreshed every 1/60 s for a non-interlaced scan and
s for an interlaced scan. Thus, the fastest way to check the screen is by m nitoring the pixel data stream on the SDB. With this in mind, an improved
screen scanning mechanism was developed to overcome the above
At the first phase, a scanning circuit is used to detect blue pixels in th data stream. An interrupt request is generated by the circuit when a blue 93
pixel is detected. By recording the horizontal line number at each interrupt, the portions of the screen which have blue pixels are known. This phase is referred to as the hardware scanning.
The screen scanning proceeds to the next phase only if blue pixels are fc undo The second phase is an improved version of the preliminary scanning rc utine and is referred to as the software scanning. With the line information obtained during the hardware scanning, the area to be scanned during this phase is reduced. The software scanning algorithm is capable of breaking down simple polygons (result from touching boxes) into their equivalent boxes. Both hardware and software scanning will be described in greater detail in the fc Uowing sections.
S.�.3.1. Hardware Scanning
The development of the hardware scanning involved the following steps:
1) development of the interrupt routine, and
2) design of the circuit.
T �s section focuses on the development of the software associated with the hardware scanning. The design of the hardware will be presented in Chapter 6.
Since the circuit is monitoring a continuous stream of pixel values, the sc ftware routine has to ensure that only one full screen of pixels are checked by the circuit. This process is achieved using the display interrupt (DI) available on 94
th TMS34010. The display interrupt request becomes active when a particular h rizontal display line is outputted to the screen. The line number is specified in the DPYINT register. At the beginning of each horizontal blanking period, th TMS34010 compares the current line number stored in the VCOUNT register w th the line number assigned to the DPYINT register. When the two values m tch, a display interrupt request is generated. One way to mark the start and
end of a full screen is by generating a DI at the first and the last line of the
To guarantee the interrupt requests from the circuit are only taken
tween the first and the last scan lines, the external interrupt (XI) is enabled
er the first DI and both the interrupts are disabled after the second DI.
According to the schematics of the SDB [15], the input pin LINT2 is the o ly free external interrupt line on the TMS34010. After the external interrupt is t en, the horizontal location of the blue pixel is recorded by setting an array el ment to 1 using the line number in the VCOUNT register as the array index.
A status flag and interrupt counters are used to report the current status and the fi al outcome of the hardware scanning. The logic of the interrupt routine is
and the program listing of the routine is included in 95
check - 1
enable DI at fint hon. line
r
n
to software scanning routine
Dl service routine XI service routine
read VCOUNT
n register
y check = 0 enable XI
enable DI disable sel array at. last. elemenl 01. XI hert, line
return with return with increment = 1 check = 0 check counter
return
Figure S.7 The block diagram of the hardware interrupt routine. 96
5. .3.2. Software Scanning
Knowing the existence of blue pixels, the software scanning routine refers to the line information stored in the array during the external interrupt and p rforms a pixel-by-pixel checking on the portion of the screen as illustrated in
Fi ure 5.8. This scanning procedure is best explained by an example. Consider th geometry in Figure 5.9 which lies between line a and b. The algorithm that
the polygon into three boxes (ABCL, KHIJ, GDEF) will be explained
If the blue pixels are near to the right edge of the screen, which means the eternal interrupts will occur close to the end of a horizontal scan interval, the li e number in the VCOUNT register might be incremented before it is recorded.
T e possibility for this to happen depends on the propagation delay in the h dware and the time required to execute the instructions. Therefore, the s anning starts at the line a-l to ensure the corner at A can be detected. After r ching A, the program scans along three edges of the polygon - edge AB, AJ
d BE. To determine if ABEJ forms a box, the 'edge' EJ has to be checked f r continuity. If the polygon is asymmetric with E and J on different lines, the
I' e which contains the end point of the shorter vertical edge is scanned from the
As shown in the figure, blue pixels do not exist
tween I and F, thus ABEJ is not a box and further scanning is needed. 97
screen
y
D regions for software scanning
Fi ure 5.8 An illustration of the portions of the screen needed to be scanned by the software scanning.
A B a-1
a },f-- N
o P
L c
c
K----"" D
H--- G
b
J E
I F
Figure 5.9 An example illustrating the software scanning procedure. 98
The above steps are repeated using an upside-down scanning order. Since e ge Jl was detected during the last horizontal scanning, only the edge JA and
are scanned. This time the length of the vertical edges are different, hence
edge KH is scanned Box KHU with four continuous edges is then detected.
T e comer coordinates and dimensions of the box are recorded and the edges are
Ued (the labelling process is presented in the next section). The final step is
change KHU from blue to a different color. If there is discontinuity along the e ge KH, the program will halt. Even though complicated polygons can be b oken down by reiterating the inverse of the previous scanning procedure, this
"U sacrifice the speed of the rule checking process. The whole process is r peated until all portions of the screen are checked.
The software scanning routine implemented only handles polygons up to a c rtain complexity. Figure 5.10 contains polygons for which can be handled by t e algorithm as well as those which can not be handled. The geometries in c nventional layouts seldom have complex geometries such the ones in the fi ure. If such polygons exist in the layout, more hardware should be introduced
t the screen scanning process.
5 2.4. Labelling and Tolerancing
After the software scanning routine detects a box, the next step is to label
I the edges. Only the GAP previous layer label is used in the implementation. 99
- -
- I -
(a) (b)
F gure S.10 Examples of polygons which the software scanning algorithm (a) can handle, (b) cannot handle.
scanned on the boundary and outside the boundary to determine
. w ch input layers the edge belongs to. The label is then tagged to the box
ormation stored in the SDB RAM. Coincident edges are marked with a value o er than 1 (for layer 1) or 2 (for layer 2). Consider edge LC of box ABCL in
F gure 5.9. Since LO is touching KH and PC is touching GD, only the segment
is a real edge on the screen. In cases like this, the complete box edge is st 11 labelled with the edge type of MN.
Like GAP, the tolerance routine implemented allows positive and negative t erance distance. Based on the information of the box under tolerance, the 100
lolerancing all layer 1 edges
r I
I Legenci I 1 L D layer r--, layer 2 L_...J D tolerance example II example 112
F gure 5.11 Tolerancing in the GAP implementation using the TMS34010. t lerance boxes are generated only for those edges whose label matches the layer
As mentioned in Chapter 3, the tolerance box of an edge has to
e tend pass the endpoints whose adjacent edge has to be toleranced as well.
the edges are processed in a clockwise direction (starting from the top
in the tolerance routine, there is no need to check the label of both
It is adequate to check the label of the next edge and determine
extension is needed. Figure 5.11 shows two examples of the operation
a positive tolerance distance. There is no extension required in the
o eration with negative tolerance distance. 101
5. .5. Error Detecting and Reporting
Tolerance boxes are drawn on top of the input geometries and by similar pi el processing operations described in Section 5.2.2, error boxes (if any) are
sferred to the bit plane 2. This prepares the display for screen scanning.
eng this scanning, information regarding the error boxes is obtained. Since
edge label is manipulated in the implementation, the
S34010 can not trace back to the original edges on the input layers as in
to the . Instead, a graphical error detection approach was developed identify e or edges on input layer 1 and/or layer 2. The approach is composed of two di ferent error detecting routines which identify:
1) error edges adjacent to the related error boxes, and
2) error edges away from the related error boxes.
polysilicon extension rule is a good example to illustrate both situations.
tolerance boxes are intersected with the polysilicon and an error box a peared at the end of the polysilicon box indicating the extra extension required as shown in Figure 5.12. The error edge HG on polysilicon is therefore adjacent to the error box. On the other hand, the related error edge DC on the diffusion la er is a distance away from the error box. Not all rule checks comprise for
th the circumstances, in fact, single-layer rule checks use only one of the two e or detecting routines. 102
D
I H
L � ... Legend 'l. ... ______/ K 0 diffusion G r·, polysilican J ..... � eJTOl" C
F gure S.12 The relationship of the error box and error edges on layers and 2 in the polysilicon extension rule check.
The recognition of an error edge (from a specific input layer) which is
ching a known error box can be easily performed by scanning around the
o tside of the error box. The error edge is then stored in the form of the
c ordinates of its two end points.
One way to capture the error edge DC in the figure is to find out which
erance box is the parent of the error box. Knowing the error box comes from
tolerance box ILKJ, the routine can scan the outside of the tolerance box and
ieve the locations of point C and D. The "window hit detection" feature of
TMS34010 window violation interrupt is used to find the parent of each error 103
box, This is achieved by setting each error box as the window and re-drawing
t] e tolerance boxes. Each tolerance box that hits the window is scanned using
tl e routine described in the last paragraph.
Error boxes appear as part of the original boxes in some rules like inter-
h yer spacing rule shown in Figure 5.13. The error edge on the diffusion layer
can be detected by the routine using the window violation interrupt. To detect
tl e error edge on the polysilicon layer, the edges are scanned on the boundary
n ther than the outside of the box.
r· • I � � I Legend I � � I � diffusion I � D I r·., polysilicon I I L." I I tolerance L .... D � error
Figure 5.13 Inter-layer spacing rule check with error boxes. 104
The error edges are highlighted at the end of each rule check. A flashing ef ect was achieved using a loop to draw each edge in red and green. alternately.
T e error information is also written to an error file on the PC simultaneously.
T e file lists the error type and the end points of each error edge in their CIF x coordinates. Examples of the error message are shown below.
(0) transistor size on CF : (-850, 400) -> (-550, 400)
(1) oversize from active channel on CP : (650, 2125) -c- (850, 2125)
(2) enclosure on CC : (-1550, -900) -> (1450, -900)
T e data transfer between the PC and the SDB involved in this process will be p sented later in the chapter.
5. . Layout Clipping
The design rule checking resolution was chosen to be a quarter of a m cron. This is a resolution accepted by most of the IC fabrication houses.
ith four pixels representing one micron, one full screen can represent a 160 by
1 0 microns area To accommodate a design with the largest layout size (7518 m crons by 7518 microns) available in the Canadian Microelectronics Corporation
( MC), 14 Giga-bits of screen memory is required Obviously, it is impractical to process a large layout as a whole. Therefore, in order to manage larger d signs, the layouts must be clipped into pieces then loaded to the SDB screen m mory for design rule checking. 105
A line clipping program written by Dr. R. Bolton was utilized to clip the
This program was used as a clipping routine for pen pl tting layouts or drawings. It implements the clipping algorithm described in
]. It accepts a line and returns only the segment of the line that falls inside
specified window. Since the clipping program accepts end points of lines, a ro tine is required to convert each box in the CIF file into four edges which are
st red in an intermediate data file, This intermediate data file serves as the input
the clipping program. Since the line clipping program is designated to
h die lines, another routine is necessary to reconstruct the new box based on
clipped lines. Dr. Bolton's program has been modified to include the ability
to project the edges that fall completely outside the window back to the related
ed es within the window so as to form a complete clipped box. Figure 5.14
ill strates the outcome of the edge projection.
s. .1. Edge Clearance and Overlapping of Clipping Windows
It is almost certain that there will be layout boxes along the edges of the
sc een, especially when clipping is required. Difficulty arose when the tolerance
xes extended outside the screen boundary. The tolerance box would not
ap ear on the screen and the rule checking could not be performed properly.
E ge clearance was introduced to allow enough room to accommodate the
to erance box with the largest tolerance distance in that particular technology.
F r CMOS3 DLM technology, the largest value involved in the rules is 7 106
L
K A B
Legend
--- clipped edge - - - projected edge box edge
Figure 5.14 Edge projection in the customized clipping program. microns, therefore a 10-micron edge clearance was chosen. The screen with the ed �e clearance represents a 140 by 100 microns area.
As pointed out in the last paragraph, clipping will result in a number of
sp it boxes along the screen boundary. It is also true that these boxes cause errors such as minimum dimensions errors. In order to check these boxes co rrectly, the adjacent windows have to be overlapped by a certain amount.
However, the overlapping of windows can not eliminate the numerous false en ors reported along the screen boundary due to the incomplete boxes. This problem was overcome by disregarding the errors reported within a certain
dis tance all around the screen boundary. To ensure no true errors are neglected,
I 107
(O,O) (639,O) ( 40,40) (599,40) (68,68) (571.68)
10 microns-_
7 microns - __
(68,411) (571,41l) (40,439) (599.439) (O,479) (639,479)
position of r:-- I I --:-1 two adjacent windows I I I I I I I I I I I I I I L..: __ __ :.J
F gure S.lS Overlapping and error neglecting zones of clipping windows.
t e overlap amount must be double the neglect amount as shown in Figure 5.15.
T e error neglecting distance was chosen to be 7 microns, hence the overlapping
ount is 14 microns. The screen is finally reduced to present an area of 126
86 microns. 108
5 4. Data Translation
For simplicity in this implementation, only layouts without hierarchy are
This means all Clf layout descriptions have to be flattened before the d sign rule checking. The flattening process is to move the entities in all higher h erarchical levels to the lowest level where all geometries are represented by the b sic elements - boxes and polygons. Such task can be efficiently handled by e isting programs.
Since most Clf files use the default one-to-one scaling, the commands in t e Clf that are important for the data translation are:
1) box (B) command which is followed by the length, width, x and y
center coordinates, x and y direction vector coordinates of a box,
2) layer (L) command which is followed by the shortname of a mask
layer, and
3) end (E) command which indicates the end of the Clf me.
efore passing the layout to the clipping routine, the flattened Clf file is c nverted into an intermediate me which uses three specific plotting commands:
ove (M), draw (D) and pen (1). A box is represented by one move command t at moves to a starting comer, then four consecutive draw commands that draw t the four comers. The pen command is analogous to the layer command in 109
e In addition to the original commands, an end command same as that in e is put at the end of the intermediate file.
The clipped edges are then reconstructed into a box form in the TMS340 1 0 xy pixel coordinates. It uses an extension of the TMS34010 box format which in ludes the width, length, and the upper left comer coordinates of a box. The ex ension to this format is an input layer identifier attached to each box.
After each window is checked, the error edges information (if any) is
. w tten into an error file. Since the end points of the error edges are in the pi el coordinates, they have to be re-converted back to the Clf xy coordinates.
A the data translation involved in input preparation and output conversion de cribed above is performed by the host processor.
s.. Data Transfer Between the PC and the SDB
The TMS34010 e compiler does not support any standard I/O functions, th refore it is impossible to read in the layout directly from a data file. At the
inning of the implementation, the input data was compiled into the software.
N vertheless, this is not a long term solution to the I/O inefficiency.
There are two ways to execute a program on the SOB. One can load and
a program from within the software debugger or by using the SOB loader.
T e SOB loader was investigated because it is more appropriate to execute the 110
sof ware in the PC environment. According to the loader source file, it copies the program into the SDB memory through the host interface bus, then redirects the execution flow of the TMS34010 processing to a non-maskable interrupt
(N ) routine. In this case, the beginning address of the program is assigned to the vector location of the NMI. With this setup, it is feasible to load the layout inf rmation into the desired memory location prior to the NMI request.
The source file of the SDB loader was modified in order to be adaptable by the Turbo C compiler. The host control (HSTCTL) register is set to perform the write (with automatic address increment) instruction and it is reset after the co e is written to the SDB. Before resetting the HSTCTL register, the modified
10 er prompts back to the user for instructions. The loader is capable of
nloading and uploading information from the specified memory locations.
downloading procedure is identical to that used in loading the program
The uploading option is essential because it is the only way to obtain the
rule errors from the SDB. This is achieved by using the read (with au omatic address increment) instruction.
Box and error edge information in the software is stored in the form of gl bal data structure array. For every window, the layout information is written to the input box array and errors are read from the error array. Hence, the host pr cessor has to know when and where to download/upload the data It also has to sign the software to skip the screen initialization if the screen has already 111
previous execution. An efficient scheme is required to re ulate the data flow.
Since the addresses of all global variables are listed in the map file (which is created during the compilation), the array addresses required for data transfers ar available. Other conditions such as when the software finishes checking one window, when there are errors to be uploaded, and when the screen initialization
not required can be decided by either establishing a handshaking pattern
ween the host processor and the graphics processor or monitoring status flags
. w ch are accessible by both processors. The address of the status flags can be m de accessible by declaring them as global variables in the programs. To be c nsistent with the method used to determine the location of the data arrays, the la ter method was chosen. Three status flags are used in the final version of the
S B loader to reflect the conditions mentioned above.
A detailed description of the core work of the research was presented in
chapter. The development of the software routines started with the m dification required to integrate GAP and the TMS34010. Two specifications in GAP were removed due to the different method used to manipulate layers in th TMS34010. The reasoning behind the modification was presented. The re ationship between the display and intersection routine was discussed, and the 112
aphics instructions used to achieve these two steps were given in the form of a
Only the software associated with the evolution of the screen s anning was included. The conditions considered in the analysis of the layout c ipping were presented The chapter concluded with the data translation and d ta transfer control between the host processor on the PC and the graphics
Chapter 6 will elaborate on the development of the eternal circuit used in the scanning process. Chapter 6
HARDWARE DEVELOPMENT
6. . Introduction
Although the TMS34010 consists of the best features from both a general p rpose processor and a graphics controller, it does not support efficient screen sc ning feature required in detecting intersection outputs. Investigation showed th t it was feasible to implement the detection by hardware, and the related in errupt routine was presented in the last chapter. Using the hardware scanning c ncept described in Section 5.2.3.1 as a base, this chapter will deal with the d velopment and verification of this additional circuit.
6. . Purpose of the Additional Hardware
The purpose of the additional hardware is to speed up the detection of
1 ersection output geometries by reducing the screen area for the software
full screen to the horizontal section(s) that contain the g ometries. This can be achieved by monitoring the pixel data that goes from
SDB to the AED graphics terminal with an add-on circuit. The pixels are
sferred from the video RAMs to the TMS34070 Color Palette through two
7 ALS157 multiplexers as shown in Figure 6.1 [17][18]. The TMS34070
113 114
DOTCLK
video RAM DOTCLK R -- -
- 128 Kilo-bytes -- - -
- to - � DAO-DA3 T1IS G - - -
III - - CRT Jl 34070 monitor U DBO-DB3 B X - - - • - -
-
video RAM - - II1II""" 128 Kilo- bytes
Figure 6.1 Video signals block diagram (from [15]). receives two 4-bit pixels (DAO-DA3 and DBO-DB3) from the multiplexers and converts them into the R-G-B signals. This organization indicates that the external circuit has to compare two 4-bit pixel values to a reference value and re Iect the result back to the TMS34010 through a set/reset device, e.g. a flip- flop.
An interrupt request is sent to the TMS34010 by asserting LINT2 low w nenever the desired pixel value is detected. The horizontal line number of each in errupt is recorded; hence, the horizontal section(s) of the screen that contains the desired pixels is known. Notice that though the horizontal position of a pixel on a scan line is accessible through the HCOUNT register, the interrupt 115
ro tine cannot act fast enough to read the correct value. In order to keep the cir uit inside the PC, the printed circuit board (PCB) has to be relatively small.
6. . Preliminary Design
The pixel comparison can be implemented using two 4-bit comparators or a si le 8-bit comparator. There are two separate comparisons in the first case,
efore, the circuit is capable of detecting a single pixel. Unfortunately, this ap roach requires a logic gate to combine the comparator outputs into a single in ut for the flip-flop. On the other hand, if an 8-bit comparator is used, the
pixels become the upper and lower nibbles of an 8-bit value and are pr cessed at the same time. Thus, this choice can only detect pixel pairs. Since ch p count was a main concern, circuit simplicity was achieved at the expense of de ection resolution. Another reason that an 8-bit comparator was used is that it is nlikely to have single-pixel-wide geometries as the intersection output.
In order to be consistent with the SDB components, the comparator and
from the ALS series. The preliminary circuit design is
The reference value (QO-Q7) and the comparator enable bi were set by 9 jumpers, and a 10 Kilo-ohms pull-up resistor network was
us d By setting the reference to the screen background pixel value, any non
ba kground pixel pair that passed to the AED terminal would cause the output
P Q to go high. The negative-edge triggered JK flip-flop was clocked by the 116
?4ALS888 DOTCLK iiSYiiC
OM - DA3 OAG PO OM Pl OA2 P2 OA3 P3 OBO - DB3 DBO P4 OBl P5 OB2 +- PI ov_JRQ OB3 P? ex P-Q K - '10 :. '11 : :. '12 '13 :. - '14 - '15 :. 'Ie :. - '17
-
- G
5V
. • .> • ' " , .> " . ' ' . " . . '. . s : . .� . .� •
Figure 6.2 Preliminary screen scanning circuit. s MHz clock signal (DOTCLK) used by the TMS34070. This allowed
comparison result at input K to settle within half the DOTCLK period. At
end of each scan line, the flip-flop was preset for the next line by the active
horizontal sync pulse (HSYNC).
To avoid the risk of damaging the color palette chip, only the DOTCLK si nal was taken from the TMS34070. The pixel data, power, and ground were t en from the 74ALS157 multiplexers. Figure 6.3 is the simplified diagram of
As indicated in the figure, neither the 74ALS157 multiplexers (U28
nor the TMS34070 (U32) is located close to the TMS34010 (Ul).
T e PCB has to be closed to the majority of the signals; therefore, it was placed 117
O[]!]nrm D[][] DI u281msn I U33 I O[]!]O[§[] O[]E] 01 U291O[]![] 0 []E] W J4 a��ID u42101 Ull I O[]!] O[][]nl :'l � OD§] m:m I RP21 DO I U39 D .....I�::��r D[]E]-OrnJ O[]ll] [][]l!]Q� J3 Ol£] L:...J CE10 O[]ID DOiO-m U2 II U40 I t::::J
P1
F gure 6.3 The TMS34010 Software Development Board with component unit number and relative locations (from [15]).
component U25, U26, U28, and U29. With this arrangement, the
als from the TMS34010 must be connected to the circuit by jumper wires.
socket mechanism was developed to integrate the PCB to the SDB. Two
solder-tail sockets were joined to the pixel data pins on the multiplexers from
a vee These sockets provided an outlet for bridging data to the circuit through
t 0 wire-wrap sockets on the PCB as illustrated in Figure 6.4.
A considerable amount of time was spent in preparing the PCB layout.
S nee the PCB was tailored for the SDB, accurate measurements were taken to
e sure proper socket alignments. orCAD, a newly available PCB software 118
- wire wrap - socket additional circuit
--I solder tail - I� � socket I
r{_ SDB multiplexer )- (U28/U29)
F gure 6.4 The preliminary socket mechanism for connecting the circuit to the SOB. p ckage in the department, was used to generate the PCB artwork. Due to the
emory shortage on the network drive where the software was installed, the o CAD auto-router could not be activated, hence the board was manually routed.
addition, new cells had to be created because the OrCAD library did not s pport the cells for some selected components.
Both LINT2 and HOLD were connected together and tied to high through
inverter on the SOB. In order to free LINT2, the track joining LINT2,
OLD, and the inverter was cut. The connection between LINT2 and HOLD
as not found on the bottom side of the SOB. Since there is no sign of a 119
m lti-Iayer SDB, the track was believed to be under the TMS34010 socket on
top side of the board. A hole was drilled between the pads to cut the track
a jumper wire was used to tie HOLD back to the inverter output. After the
6 m by 3 em circuit board was made and installed onto the SDB, the pixel si nals on the circuit were checked by an oscilloscope. Most of the signals were un ble to reach the circuit due to poor socket and solder connections.
6. . Final Design
While searching for a better connecting mechanism, the circuit design was re ised. It was not realized until then that it is more advantageous if the circuit de ects a specified color. The preliminary design can detect more than one co or, hence the intersection output had to be the only layer displayed on the sc een. This means that the input layers must be removed from the screen te porarily. To avoid this extra step, the circuit was modified to detect a se ected color and will be presented shortly.
In the new socket mechanism, the TMS34070 was moved to the circuit and
empty 22-pin TMS34070 socket on the SDB became the PCB outlet. The
S34070 signals were connected to two rows of jumper headers that were so dered to the bottom side of the PCB. The headers were plugged into the o tlet through a 22-pin solder-tail socket. With this connection, all TMS34070 si nals were redirected back to the SDB. 120
14 horizontal interval "'1 U L HSYNC L HBLNK
VCOUNT-O
VC\3YNC
VEBLNK
IItart. acti.". ';;j new C.I diaplay , me :;::l time ... II!
VSBLNK
vroTAL
0 :::,.:: :.:: ..J u -< � 3 3 � II I� � fI.I r:tI a:I ::I r.:I r.:I fI.I 0 = :c :c � � � I start new line
Figure 6.S Horizontal and vertical timing relationship (from [11])
The schematic of the revised circuit design is in Appendix C. The extra
J flip-flop in the package was used to latch and invert the comparator output.
ANK instead of HSYNC, was used to reset the flip-flops at the end of each
line. This can be explained with the SDB horizontal and vertical timing
re ationship in Figure 6.5. Besides being inactive high during the display time,
H YNC remains inactive during the horizontal front porch (which is the interval
be ween the beginning of horizontal blanking and the beginning of the horizontal
sy c signal) and the horizontal back porch (which is the interval between the end 121
o the horizontal sync signal and the end of horizontal blanking). Whereas,
is the result of logical-Oking the internal horizontal and vertical
. ng signals (HBLNK and VBLNK). Therefore, BLANK provides a better
. in cation of the start and end of a horizontal display line.
The PCB layout of the final circuit was produced by TANGO. This s ftware package is more flexible than OrCAO, thus the layout was created in a
ch shorter period of time. It was predicted that moving the color palette off
SOB might result a degraded graphics quality. To observe the effects on the g aphics quality, the new (6.5 em by 5 ern) circuit board was first tested without c nnecting to BLANK and LINT2. The TMS34010 demonstration was i spected, and there was no visible alteration to the graphics quality. With the r ference value set to the blue color code, the circuit was then tested using the i terrupt routine. As pointed out in Chapter 5, the element of an array whose i dex corresponds to the line number was set to 1 by the routine. After
one full screen, the array was displayed vertically using the element
the corresponding pixel value. The red (OOO1J vertical segment was
splayed in the horizontal area where blue pixels were found. The functionality
o both the circuit and the interrupt routine were established; the PCB was then
lted to the SOB for better support. 122
6.. Summary
This chapter has focused on the development of the screen scanning circuit.
T e preliminary circuit which detects pixel values that are not the reference value
described. The first socket mechanism used to integrate the printed circuit
ard to the SDB failed due to bad connections. To retain the input layer
ormation on the screen, the circuit was adjusted to detect pixels of a particular c lor. A more efficient socket mechanism was developed and both the modified ci cuit and socket mechanism were proven functional. Chapter 7
TESTING AND LIMITATIONS
7. • Introduction
In Chapters 5 and 6, the software and hardware developed during the GAP
i lementation on the SDB were discussed Six categories of design rule were
es ablished using building block routines such as displayt), tolerancet), labelt),
0, and reporu). They are named as follows:
1) min_dimO for minimum dimensions,
2) lyrextO for polysilicon/diffusion extension pass transistor gate,
3) tran_sizeO for minimum transistor size,
4) interjpacingt) for inter-layer spacing,
5) intraspacingf) for intra-layer spacing, and
6) enclosureO for enclosure.
T ese functions were assembled into a prototypical technology file (included in
A pendix D) with a structure similar to that of the GAP CMOS3 technology file.
E cept the intra-layer spacing, proper transistor gate formation and maximum
di ensions rule, the remaining 24 rules listed in Section 3.5 use the function re orn) for design rule checking. The variations in reportO among these rules
ar the input layers and the choice of IT or 01 layer. The polysilicon-diffusion
123 124
and enclosure rule at contact cuts, which use II and 01 layer
are included in the trial technology file to illustrate the
1 lementation of similar rules. The only step required to perform other rules is
preparation of the input layers. Rules such as the split contact cut and the de ice well (with different doping) spacing rules which involve more than two m sk layers require slightly more complicated routines to obtain the desired input la ers for reportt). The trial technology file checks eight design rules:
1) transistor size,
2) polysilicon extension past transistor gate,
3) diffusion extension past transistor gate,
4) spacing on individual layers,
5) device well to polysilicon spacing,
6) minimum dimensions on individual layers,
7) metal enclosure at contact cut, and
8) polysilicon enclosure at contact cut.
T e rules in the GAP CMOS3 technology file which can be implemented by the pr sent software routines are listed in Table 7.1. This chapter will begin by de cribing the preliminary testing on the trial technology file and the customized
The implementation was examined using the Queen's University
In eractive Silicon Compiler (QUISC) standard library cells available in the de artment. The performance and limitations of the system will be addressed 125
T ble 7.1 The GAP CMOS3 design rules which can be implemented by the function calls of the six design rule categories
by Implemented can be this funcUon GAP CMOS3 Rules Implemented by Design In the trial Lbill function technolalY file
(1) spacing on incllvidual lay.rs InlraJpacing()
(2) minimum dimensions on Individual layers mllLdim() (3) N+ to P+ spacini encIOllure() (4) device _11 (different eloping) spacing (5) transistor rule. (properly formed gate) (8) late overlap onto rield oxlde lyrext() (7) device well to polysilicon spacing inler_spacing()
(8) P _II (9) p _II ow!'llize on non-aeUw clevice well enclosure() (10) P+ overlap of device well enclosure() (11) N+ to fi.ld .pacini lyrexl() (12) N+ to polysilicon spacing In clevice 11811 inter_spacingO (13) cleYioe _11 owrlap of eonlact. out. enclosure() (14) device well contact to aate spacing inter_spacing() (15) metal overlap of contact cut enclosureO (16) polysilicon owrlap of contact cut. enclosure() (17) metal 1 enclosure of via enclosure() (18) metal 2 enolOllure 01 via encIOllure() (19) via to device _11 spacing inter_'pacingO (20) via to polysilicon spacing inter_Ipacing{) (21) maximum contact dimensions (22) P guard o'Verlap 01 P well encIOBure() (23) P guard lo N guard spacing enclosure() (24) P well to P+ diffusion spaoing inter_spaclngO (25) P well to N+ dlttuslon spaclnl inter_spacing{) (28) split contact to P+ spacing (2'7) split contact to N+ spacing Additional Rule. (28) diffusion exlension past gale Iyrext() 126 7.. Testing Simple test patterns were used during the development of the design rule c ecks to verify their functionality. Since these patterns consisted of only one or t 0 boxes, they were directly displayed to the screen using the TMS34010 As mentioned earlier, the TMS34010 does not support st dard I/O; therefore, visual debugging was frequently used. For example, the s ftware scanning routine was inspected by simultaneously displaying the outline o the extracted boxes on the unused screen portion. The testing conducted in t e research can be broken into two stages as will be discussed in the following .1. Preliminary Testing Slightly complex test patterns were used to check the trial technology file d the data clipping/transfer operations integrated in the customized SDB loader. test file which included the violations for all accomplished rules was generated the KIC layout editor. Both the pattern and reported violations were plotted graph paper to confirm the accuracy of the screen-to-CIF coordinates c nversion. All rule checks were capable of detecting the associated errors, and t e locations written to the output file matched with the original edges in the test Therefore, the functionality of the layout clipping and communication tween the PC and the SDB were verified. 127 In order to verify that the technology file can handle the CMOS3 DLM d sign rules, a test file based upon the pattern used for illustrating the CMOS3 D M design rules [19] was created by KIC. Both the pattern and design rule d scription are included in Appendix A. The specified design rules were di obeyed intentionally to obtain a file that consists of all possible faults. All ei ht rule checks were able to recognize the related violations but false intra la er spacing errors were also reported at some polygons which were broken d wn by the software scanning routine. Investigation of the cause of the false e ors was conducted, and the result will be presented after the next subsection. 7..2. Testing of the QUISC Library Cells The test patterns described so far consist of mostly unconnected geometries t t do not resemble a circuit. They are not adequate to confirm the system p acticality for real life applications. Therefore, small circuit layouts were used f r the second stage of the testing. Standard cells from the QUISC library were used for the analysis because t ey have reasonable sizes and are free from design rule errors. Three cells of . fferent size and complexity were selected and they are listed below: 1) the inverter (inv) , 2) the two-input exclusive OR gate (xor2), and 3) the D flip-flop with reset (rdft), 128 an their layouts are included in Appendix E. The cells were checked in the a ve order, and the number of false errors reported were 10, 56, and 153, Besides the expected intra-layer spacing errors, minimum di ensions violations were also reported in the D flip-flop circuit. Since the ca se of the newly discovered false error was not known, one of the violating g metries from the flip-flop layout was studied. The investigation concluded cause of these false errors is identical to that of the false intra-layer spacing To observe the speed of the established DRC system, the time needed to c eck each window of a cell was evaluated. The measurement did not take the ti e used in error highlighting and the data communications into consideration. T e results were compared against the run-time required to check the three la outs using GAPDRC. According to the timing results shown in Table 7.2, the h dware implementation which checks only eight rules, is much slower that the o gina! GAP which checks a total of twenty-seven rules. As will be seen in the next subsection, the cause of the false errors re orted in the testing originated from the screen scanning algorithm. Solutions f this problem are also proposed. Other minor limitations encountered in the re earch will be discussed in a separate subsection. 129 T� ble 7.2 Time required to check the selected QUISC library cells using GAPDRC and the GAP implementation using the TMS34010 SDB GAP-SDB ImplemantaUan CAPDHC! on UNIX QUISC cell windo.. run total run Ave. no. of Trial nama locaUon Uma run Uma Uma run UmB box•• no. (x.y) (••c) (-) (Me) (.ac) 84 62 1 0.6 iny (0.0) (0,1) 38 58 2 0.6 area 138 0.7 6708 :3 0.7 mioron aq. 4 0.7 278 118 1 3.& xor2 (0,0) (1,0) 180 103 2 3.1 area 357 3.2 25800 (0,1) 107 67 3 3.2 micron .q. (1,1) al ala "" 3.0 (0.0) 32g 109 1 5.7 rdff (1,0) 399 117 2 5.4 5.6 area (2,0) lla7 100 3 5.6 "1022 551 (0.1) 126 70 "" 5.7 mioron aq. (1.1) 17" 79 (2,1) '76 78 7. 1.1. The Cause of False Errors To return to the problem of false intra-layer spacing error, consider the metal layer at a contact cut in Figure 7.1. The software scanning routine breaks the polygons into two boxes, ABCD and EFGH, where each box satisfies the minimum width criterion. It is important to note that the labelling function as signs a label as long as a segment of an edge satisfies one of the edge conditions. That is why the label of edge DC is metal although the segment N � is not defined explicitly on the screen. When the edge DC is toleranced, a fa se error box EFJI results. After tracing back to the parent tolerance box using the window hit feature, the original edge DC is scanned from left to right. The 130 D C Le,and B F E:::il'DAUlk layer tolerance bOll: J c::J � error box H G lllustration of the cause of false intra-layer spacing error on the metal layer at a contact cut. e ge detecting routine halts when it reaches an inner/outer comer thus only the e ge DK was highlighted and recorded in the output file. A metal WIre from the flip-flop layout which subjected to false minimum ensions error is included in Figure 7.2. The dashed lines indicate the hidden e ges of the equivalent boxes. When the edge DC is toleranced (note that n gative tolerance distance is used in this rule check), a portion of the tolerance x EFCD, falls outside the polygon and creates the top error box. Similarly, th bottom error box results from the tolerance box ABGH originating from the 131 Legend I:J muk layer D loleranc:e box fLZI error box g A D C B C Illustration of the cause of false minimum dimensions error on the metal2 wire in the D flip-flop layout. The error edges JK and DI which originating from these boxes are th n reported. The cause of these two false errors corresponds to the figure pathology di cussed by Baird, McGrath and Whitney [9][8]. That is to say, the errors are in uced by edge/segment existence within the boundary of geometries. Note that DRC implementation treats the polygons on the screen as a group of u elated boxes which happen to be adjacent to one another. One suggestion gi en in these papers for eliminating the common edges is to logical-OR the i ut boxes of the same mask layer and represent the results in their boundary 132 se ments as exercised in GAP. Similar representation can be achieved by using th polygon functions available in the TMS34010 graphics library. One such fu ctions is fill_polygonO which fills a polygon given a list of vertex coordinates re resenting the edges of the polygon. In order to locate the vertices, the scanning routine has to inspect the perimeter of each geometry. The with this approach is that the extra software scanning will further le gthen the run-time of the design rule checking process. Besides, the polygon ipulation is beyond the target of this research. Another solution for this problem is a more thorough error edge searching p ocedure and is demonstrated by reconsidering the case in Figure 7.1. Instead o stopping at point N, the process can continue to check pixels until it reaches pint C. The end points of each segment (DK, NM, and LC) can be obtained d ring this process. After examining the entire edge, the end points are c mpared against a list of input layer edges. The error can be regarded as false if all segment end points satisfy both of these conditions: 1) collinear with a pair of end points from the list (such as point C and D in the figure), and 2) within one pixel, in x or y directions, from another input box edge (edge EF in the figure). additional steps simply determine if a false error box is generated by t lerancing an edge which attaches to another input box. This software 133 m dification can avoid both false intra-layer spacing and minimum dimensions rs; however, it is impractical to conduct the end points comparison with a I memory overhead The reason for false violations was determined but of the adjustments were fulfilled because the two workable approaches di cussed so far are neither sophisticated nor efficient. The ultimate resolution to . t s problem is the introduction of more hardware to the ORC system. . 2. Performance of the Software Scanning The performance of the trial ORC on the QUISC cells was compared to of GAPORC. The timing result summarized in Table 7.2 shows that G ORC runs faster than the ORC prototype by a significant amount. Software sc ning was believed to be the cause of the poor run-time. To estimate the pe centage of scanning with respect to the run-time, a single design rule check of a ypical QUISC standard library cell was analyzed Two major steps in the software scanning routine are listed below: 1) read a pixel value from the screen memory using the graphics function get_pixelO which is implemented by 9 instructions, and 2) compare the value obtained in (1) with a specific value using a single CMP instruction. T ese instructions were grouped as the pixel check (or 'check') operation, and its e ecution time was calculated. Note that the instruction execution time depends 134 on conditions such as field alignment. The timing of the move field (MOVE) ins ction used in get_pixelO is influenced by components such as field size and These components define the field alignment which in turn de mes the number of memory states needed to insert or extract the field from m ory [11]. In order to consider the extreme field alignment cases, both the m imum and minimum MOVE execution time was determined in the analysis. machine state duration of a 40 MHz TMS34010 is 200 ns, therefore the pi el check execution time is as below: best case timing = 35 machine states / check x 200 ns / machine state (7.1) = 7.0 J.1s / check worst case timing = 55 machine states / check x 200 ns / machine state (7.2) = 11.0 J.1s / check were: best case is when all fields involved in the MOVE instructions are aligned on word boundaries, worst case is when all fields (range from 18 to 32 bits) straddle two word boundaries in all the MOVE instructions. The minimum transistor dimensions rule and the inverter layout were se ected for the investigation due to their simplicity. Since no error box was 135 ge erated in this combination, only the time used in scanning the transistor gate ha to be considered. By knowing the screen location of the transistor gates in ea h window, the number of pixel check operations was obtained. Note that to de ect the top right comer of a box, three pixel check operations are performed at each pixel location. The number of operations along a horizontal edge equals to the width (in pixels) of the box, and the number of operations along a vertical ed e is twice the length (in pixels) of the box. The complete pull-down transistor (5 microns by 5 microns) and a portion of the pull-up transistor (5 microns by 6 microns) were in the first window. The co plete pull-up transistor (5 microns by 15 microns) was located in the second wi dow and the accumulative run-time was 3 seconds. These values were used to perform the following calculation of the software scanning time and the run ti e proportion. 5 ansistor ch for top right comer: 21 lines x 640 pixels/line x 3 checks/pixel (7.3) = 40,320 checks h rizontal edge scan: 2 x 20 pixels x 1 check/pixel (7.4) = 40 checks 2 x 20 pixels x 2 checks/pixel (7.5) = 80 checks 136 5 se ch for top right comer: 25 lines x 640 pixels/line x 3 checks/pixel (7.3a) = 48,000 checks 2 x 20 pixels x 1 check/pixel (7.4a) = 40 checks 2 x 24 pixels x 2 checks/pixel (7.5a) = 96 checks 61 lines x 640 pixels/line x 3 checks/pixel (7.3b) = 117,400 checks h rizontal edge scan: 2 x 20 pixels x 1 check/pixel (7.4b) = 40 checks 2 x 60 pixels x 2 checks/pixel (7.5b) = 240 checks T tal pixel check operations in the layout = 205,976 checks (7.6) The best case scanning time was 1.44 seconds which is about 50% of the r n-time and the worst case scanning time was 2.27 seconds which is about 80% o the run-time. The percentages obtained in this investigation are merely rough e timates because other overheads were not considered However, they provide 137 su ficient information to verify that the software scanning dominates the run-time. T e amount of pixel checking depends on the quantity, complexity, and ensions of the geometries, this becomes a major drawback of the software ning routine. 7. .3. Other Limitations The enclosure rule check routine has difficulty in examining additional en losure in the direction of the metal wire at a contact cut (see Figure 1.7). G has this deficiency as well because there is no indication of asymmetrical CMOS3 technology file, This rule can be properly ch eked by inspecting metal existence around a contact cut and then determining . w ch edge requires the extra tolerancing. A number of global data structure arrays were used throughout the software ro tines to store geometrical box or edge information. Since the size of the S B program RAMs is a dependence of the array size, the number of boxes al ows in a window is limited The array dimension was set to 500 currently d there was no indication of memory overflow. However, one should aware th possibility of data collision if the array size has to be increased to handle m re complicated layouts or technologies. 138 74. Summary Test files of different complexity were examined by the DRC system to c nfmn its functionality. The result of these tests were briefly described at the Since false intra-layer spacing and minimum dimensions an extensive study was conducted. The analysis indicated due to the common edges at adjacent boxes, and two s ftware solutions were presented. Another analysis was conducted to verify the e feet of software scanning on the performance of the DRC model. The sistor dimensions rule check on the inverter shows that the scanning the sistor gates consumed 50% to 80% of the execution time. The chapter c ncluded with the minor limitations encountered in the research. Chapter 8 MMARY, CONCLUSIONS AND RECOMMENDATIONS This thesis has described the investigation on the suitability of the Texas In truments TMS34010 Graphics System Processor for integrated circuit hardware de ign rule checking. A prototypical design rule checker (DRC) was developed an its functionality has confirmed this hardware approach. The system consists of five hardware/software components: 1) a Commodore PC10 unit, 2) an AED graphics terminal, 3) the TMS34010 Software Development Board (SDB), 4) a scanning circuit, and 5) a DRC software package. The analysis was made possible only with the TMS34010 dware/software development tools, the TMS34010 Software Development B ard and C Compiler in particular. The high-capability TMS34010 is equipped with all the graphical instructions required to carry out the design rule checking o erations. However, it encounters a speed deficiency in certain areas such as 139 140 scanning where numerous reiterations of operations are required. A investigation has proven that the software scanning procedure takes ap roximately 50% to 80% of the total execution time. The introduction of the sc ning circuit was the first step towards the ultimate solution for this The present ORC software package is practically a duplicate of the concept pr sented in GAP [10] using a 1/4 J.Un vertical checking resolution and 1/2 urn . ho zontal resolution. The files (including the basic operations, rule checks, the SOB loader, and conversion programs etc.) in the package occupy ap roximately 4000 lines of C code. The present technology file implements categories of general design rules as listed in Chapter 7. The variable esses required for uploading from and/or downloading to the SOB is acted spontaneously and stored in an address file during the main program pilation. The default variables for the extraction procedure are the main pr gram status flags (INITIAL, ERR, FINISH), input box array (IN_BOX) and e or edge array (ERR_EDGE). The only preparation for the ORC process is to tr sform the non-hierarchical layout from CalTech Intermediate Form (CIF) to an acceptable data format by the command called 'flt2mdj'. The design rule checking begins by invoking the SOB loader, which is The loader will ask for downloading/uploading indications an associated input/output data filename for each variable listed in the address 141 fil. After the downloading procedure, all DRC activities can be observed on the A D terminal. Information regarding the current window limits, number of input xes, number of error edges and processing time are outputted to the PC All error information of the current window will be . w tten to the specified output file. The error file includes precise description of th violations, in fact for each two-layer rule violation, the error edges on both The TMS34010-GAP hardware DRC prototype reported in this thesis . in cates that this method of combining commercial graphics chip and efficient D C algorithm is a potential solution to some of the problems (such as CPU in ensity, complexity, and costly) encountered by existing DRCs. The prototype verified by performing design rule check on three Queen's University I eractive Silicon Compiler (QUISC) standard library cells, and deficiencies were u covered. It is strongly believed that the run-time (summarized in Table 7.2) be enhanced significantly by replacing cumbersome software routines with The analysis on the false errors, reported at polygons formed by to ching/overlapping layout geometries, has identified the cause as the software i erpretation of these geometries. Both long-term and short-term solutions to . t s problem were proposed. 142 The interface between host computer system and the TMS34010 is not ited to the Software Development Board installed in a personal computer In fact, by moving the TMS34010 and additional hardware onto a c stom printed circuit board, it can be connected to faster computer system such The study presented in this thesis confirmed that with some enhancements o the present ORC software and introduction of additional hardware, the S34010 can serve as the main processor of an efficient and versatile hardware C. 8. • Recommendations for Further Study The system developed in this research is merely the earliest model of the d sired hardware ORC. In this thesis, enhancements for several shortcomings in t e prototype have been remarked and they are summarized along with some odifications for further study as below: • Revise the model to properly perform the Northern Telecom CMOS3 OLM enclosure rule. It can be achieved by adding extra detection feature in the labelling routine to determine the direction of the metal wire with respect to the contact cut. • Replace the present software screen scanning routine by hardware. The video RAMs on the SOB are dual-port dynamic RAMs. Therefore, the 143 new hardware should be able to scan the memory when the SDB is not accessing the video information and then return the on-screen geometries to the TMS34010 by means of their vertex locations. An intelligent routine can reconstruct the polygons from these comers. This will not only eliminate the cause of the false errors, but also lead the DRC model from box-based towards polygon-based. • Revise the two routines used in detecting error edges. The amount of pixel checking involved can be reduced by a more efficient algorithm. • Improve the speed of the software using data structure pointers as call arguments instead of the data structures. • Switch to a faster computer system to speed up the data uploading/downloading process. Note that with the TMS34010 host address register programmed to auto-increment, the maximum data rate through the host interface can be expected to approach the bandwidth of the TMS34010's memory [11]. (Bandwidth is the number of bits per second that can be transferred through the host interface during a block transfer of data to or from the TMS34010 memory). Texas Instruments supports TMS34010 C Compiler for the UNIX system; therefore, it is possible to interface the TMS34010 with UNIX. This can be done using the new SUN Microsystems SBus on a SUN SPARCstation. The SBus is a chip-level bus which requires minimum hardware interface to connect custom hardware (or chip) to the UNIX operating system. REFERENCES 1. Mukherjee, A., Introduction to nMOS & CMOS VLSI Systems Design, Prentice-Hall, New Jersey, 1986. 2. Mead, C. and Conway, L., Introduction to VLSI Systems, Addison-Wesley Publishing Co. Inc., Massachusetts, 1980. 3. Seiler, L., "Special Purpose Hardware for Design Rule Checking", Proceedings of the CalTech Conference of VLSI, 1981, pp. 197-216. 4. Dillinger, T., VLSI Engineering, Prentice-Hall, New Jersey, 1988. 5. Baker, C. and Terman, C., "Tools for Verifying Integrated Circuit Designs", Lambda: the Magazine of VLSI Design, Vol. 1, No.3, Fourth Quarter, 1980, pp. 22-30. 6. Arnold, M.H. and Ousterhout, J.K., "Lyra: A New Approach to Geometric Layout Rule Checking", Proceedings of the 19th Design Automation Conference, June, 1982, pp. 530-536. 7. Taylor, G.S. and Ousterhout, J.K., "Magic's Incremental Design Rule Checker", ACM IEEE 21st Design Automation Conference, New Mexico, June, 1984, pp. 160-165. 8. McGrath, E.l and Whitney, T., "Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking", Proceedings of the 17th Design Automation Conference, Minneapolis, June, 1980, pp. 263-268. 9. Baird, H.S., "Fast Algorithms for LSI Artwork Analysis", Proceedings of the 14th Design Automation Conference, June, 1977, pp. 303-311. 1. Mowchenko, IT., "GAP: A Geometry Analysis Program for IC Design Rule Checking", 1986 Canadian Conference on VLSI, Montreal, October, 1986, pp. 279-284. 11. The TMS34010 User's Guide (literature number SPVU001), Texas Instruments, Dallas, Texas, 1988. 144 145 12 Guttag, K., Van Aken, J., and Asal, M., "Requirements for a VLSI Graphics Processor", IEEE Computer Graphics and Applications, VoL 6, No.1, January 1986, pp. 32-47. 13 Asal, M., Short, G., Preston, T., Simpson, R., Roskell, D., and Guttag, K., "The Texas Instruments 34010 Graphics System Processor", IEEE Computer and Graphics Applications, Vol. 6, No. 10, 1986, pp. 24-38. 14 Lau, A., "An Investigation of Integrated Circuit Hardware Design Rule Checking using the TMS34010" (Supplementary Report), University of Saskatchewan, Saskatoon, Saskatchewan, Canada, 1990. 15 The TMS34010 Software Development Board User's Guide (literature number SPVUOO2), Texas Instruments, Dallas, Texas, 1986. 16 Newman, W.M. and Sproull, R.F., Principles of Interactive Computer Graphics, Second Edition (International Student Edition), McGraw-Hill, Japan, 1979. 17 The TMS34010 Applications Guide (literature number SPVA007), Texas Instruments, Dallas, Texas, 1988. 18 The TMS34010 Software Development Board Schematics (literature number SPUV003), Texas Instruments, Dallas, Texas, 1986. 19 Canadian Microelectronics Corporation, Guide to the Integrated Circuit Implementation Services of the Canadian Microelectronics Corporation, Version 4:0, March, 1989, Kingston, Canada. APPENDIX A NORTHERN TELECOM CMOS3 DOUBLE LAYER METAL (DLM) DESIGN RULES 146 147 A duplication of a section from [18] is included in this appendix (with It includes the CMOS3 Double Layer Metal (DLM) design rules d a general description of the fabrication process. the present time, prototype integrated circuit fabrication is available through CMC using one process: 083 DLM - a 3-micron single polysilicon, double metal P-well CMOS process Al. CMOS DLM A 2.1. CMOS DLM Process C OS3 DLM is a 3-micron P-well CMOS process with single-level polysilicon and dubIe-level metal. Because of the 3-micron minimum feature size, the supply v ltages of the finished devices are limited to 5 volts. Capacitors are supported and ar formed using a highly doped P+ device well as the bottom plate and polysilicon as the upper plate. T e following description outlines the process flow. A simple inverter and capacitor ar used in Figure C.I to illustrate the sequence of patterning and processing steps. Process Description P well The first photolithographic operation defines the P-well regions in the N substrate. These correspond to the regions which will contain NMOS devices and N-diffusion interconnects. At this stage, the N-substrate is covered with thin silicon dioxide Si02 where the P-wells are to be formed, and thick oxide elsewhere. Following the P-well implant and subsequent oxide removal and regrowth, the section of wafer will appear as shown in Figure C.l{a). N well The N-well mask is used to define the regions which are to receive an N-implant to set the threshold for the parasitic (non-active) regions in the N substrate. The P-well regions are protected from the implant by photoresist (PR), as shown in Figure C.l(b). D vice well The photoresist is removed and a layer of silicon nitride Si3N4 is de posited on the thin Si02 and patterned using the device well mask. This pho tolithographic step leaves the nitride only in regions which will become drains, sources, channel regions, diffusion interconnects, and capacitors if present. 148 The nitride is used to mask these regions from the next processing step, a P implant into the Pvwells. It also defines the regions of subsequent field oxide growth. The result is shown in Figure C.l(c). P-guard Photoresist is deposited and patterned in the next photolithographic step using the P-guard mask. The P-guard is used to accomplish a P-implant into P-well regions which will eventually be covered by field oxide. The purpose of this step, shown in Figure C.l(d), is to set the threshold voltage of the silicon under the field oxide to be greater than the threshold voltage of the silicon under the gate oxide. Following this step, thick oxide is grown and the nitride is removed as shown in Figure C.l(e). Thin gate oxide is grown over the device well regions, and after a photolithographic operation involving a copy of the N-well mask, an implant is performed to adjust the threshold voltage of the P-channel transistors. Capacitor P-doping If capacitors are to be created, the device wells which form the bottom plates of capacitors are now heavily doped P+ using the capacitor mask in the next photolithographic operation. Polysilicon With a thin Si02 gate insulator layer over all active regions, the gate polysiJicon layer is deposited over the entire surface and doped N+. The next photolithographic operation, shown in Figure C.l(f), uses the polysilicon mask to define the gate regions, poly interconnections, and the upper plates of capacitors if present. N+ Following a poly oxide growth step, the N+ mask is used to prevent the N+ doping and subsequent drive-in from getting into P+ areas. Figure C.l(g} shows three N+ regions formed by this photolithographic operation: the source and drain regions of the N-channel device within the P-well, and a contact region in the N-substrate. As in most MOS processes, the silicon gate regions ensure properly aligned source, drain, and gate structures. P+ This mask is used to define the P+ doping and subsequent drive-in to the N-device regions, the P-well contact points, and the capacitors if present. The result is illustrated in Figure C.l(h). The P+ and N+ doped regions which are directly adjacent to each other will be used to form a split contact in subsequent steps. Any polysilicon included in the P + areas is partially compensated but remains N-type. Contact A moderately thick layer of SiOl is deposited over the entire surface and the contact mask is used in a photolithographic operation to etch out the contact regions. Metall A layer of aluminum is deposited over the entire surface and the metall mask is used in a photolithographic operation to define the metallization lines. The result is shown in Figure C.l{i). 149 A second layer of Si02 is deposited over the entire surface and the via mask is used in a photolithographic operation to etch out the via regions. Vias are used to connect metall to metal2. eta12 Another layer of aluminum is evaporated over the wafer and the metal2 mask is used in a photolithographic operation to define the metallization lines. Bonding and probe pads must be made with metal2. assivation A passivation layer is deposited over the entire surface and the pas sivation mask is used to etch out regions over the metal bonding pads and probe pads. The complete structure for a CMOS inverter and capacitor is shown in Figure C.IU). A.l.2. CMOS DLM Mask Levels and CIF Layer Assignments able C.I contains CIF short names and associated colours for the various CMOS ayers. The CIF short names are those recognized by the CMOS compatible CIF-to ALMA conversion software used by the CMC, and must be used for the conversion o proceed. or a design to be processed properly, the correct design file name syntax MUST e used. Refer to Appendix B for details on submitting designs for implementation nd Appendix F for submitting designs for design rule checks. he plotting colours listed are a suggested standard colour scheme, and although hey are standard only at CMC, it is hoped that all universities will use them ince it will greatly aid any exchange of graphical information concerned with this rocess. The mask levels associated with the various CMOS layers are also included or reference purposes and correspond to the Northern Telecom Electronics CMOS3 LM technology. For this process, levels 020, 070, and 130 denote exclusion regions hile all other levels describe inclusion regions . . 2.3. CMOS3 DLM Design Rules he CMOS3 DLM rules are summarized in Figures C.2 and C.3. The layers inboth gures are represented according to a grey scale to allow duplication on a standard hotocopier. he design rules for the Northern Telecom Electronics 3-micron CMOS process are pecified using a 5-micron scale (design scale microns) for the minimum feature size. esigns submitted to CMC must be defined using the 5-micron scale. The designs ill be scaled down at Northern Telecom to 60% of the specified dimensions prior o the creation of the pattern generator (PG) tapes. This procedure is similar to he design methods internal to Northern Telecom. he pad rules in this section are oversized to compensate for the mask shrinking rocess. All bonding and probe pads must be on metal2. Refer to Appendix D for ore information about pad frames. 150 (0) c - ..___ N lubltrote ___;_P=-"_"�_)��___JI/'O'. PR Si� ,N I ,N ./ P-..II ) (b) N - lub.t rate I , I , , N (c) l_---.;__;;.;p-..u�) N- eub.lrote (d) N- lub.trate (e) N- ...bllrole Fi ure A.1 CMOS3 DLM process for a simple inverter and capacitor. 151 (f) 11- lV.trol. It (9) 11- .u.trol. II (h) N- IV.I'DI. "'DID I 1 (i) 11- 1V.lral. (j) N- ....Irat. and F gure A.I CMOS3 DLM process for a simple inverter capacitor continued 152 Table A.I Clf layer names and colours. Layer Mask CIF Colour Description Level Name P-well 010 CPW Brown - defines P-well N-well 020 CNG Green - implant for enhancement of (exclusion) N-substrate outside of P-well Device Well 030 CF Blue - interior defines active regions - exterior regions covered with field oxide (Field) - also referred to as dif- fusion or thinox P-guard 040 CPG Yellow - implant for enhancement of P-well surface doping to prevent inversion under field oxide Capacitor P-doping 055 CCP Brown - defines area of P+ doping (optional) in a device well to form bottom plate of capacitor Polysilicon 060 CP Orange - defines polysilicon lines and transistor gates N+ Doping 070 CNP Red - defines regions excluded (exclusion) from N+ doping - substrate doping will occur only in device well regions P+ Doping 080 CPP Dotted- - defines regions of P + doping Blue - substrate doping will occur only in device well regions Contact 090 CC Green - defines contacts from metal to polysilicon or diffusion Metall 100 CM Black - defines the first metal lines Via 110 CV Yellow - defines the vias or con- tacts between metall and meta12 Metal2 120 CM2 Dotted - defines the second metal2 Black lines Passivation Window 130 CG Blue - defines openings in passi- vation layer for bonding or probe pads 153 o avoid confusion in determining the interior and exterior of inclusion and exclusion the asks, descriptions treat the mask layers mainly as geometrical shapes and the terior is defined as the central region of the polygons . . 2.3.1. Minimum Dimensions he minimum dimension is the minimum feature size for each layer. Layer Size Comments (design scale microns) .1 P-well CPW 10 .2 Device WeI) CF 5 .3 Polysilicon CP 5 .4 N+ Mask CNP 5 - in device well .5 P+ Mask CPP 5 - in device well .6 Contact - CC 5 maximum length = 20 .7 Metall CM 5 .8 - Via CV 5 all vias 5 x 5 .9 MetaJ2 CM2 5 .2.3.2. Minimum Spacing T e minimum is the spacing spacing between features of the same layer. Layer Spacing Comments (design scale microns) B.1 N-well CNG 5 B.2 Device Well CF - 7 same doping in same su bstrate B.3 Polysilicon CP 5 B.4 N+ Mask CNP 5 - in device well B.5 P+ Mask CPP 5 - in device well B.6 Contact CC 5 B.7 Metall CM 5 8.8 Via CV 5 B.9 Metal2 CM2 5 154 A.2.3.3. Enclosures Enclosures occur when geometry of one layer complet.ely surrounds the geometry of another layer. The dimension refers to the amount the geometry of the outer layer is oversized from the inner layer. Overlaps, where permitted, are identified with references to the overlap rules in this section Layers Enclosure Comments Inner Outer (design scale microns) C.I P-well to P-guard S - minimum and maximum C.2 P-guard to N-well 3 - minimum dimension is to be used as standard practice C.3 Dev. Well to P-well 3 C.4 Gate - to P-well 7 gate is poly over device well C.S Contact to Metall 2 C.6 Contact to Device Well 2 C.7 Contact to Poly 2 - use 3 in direction of metal C.S Dev. - Well to P+ Mask 4 see split contacts under Overlaps in this section C.9 - Dev. Well to N+ Mask 4 see split contacts under Overlaps in this section C.IO - P+ Mask to N+ Mask 0 both layers can be created simultaneously C.Il Via to Metall 3 C.12 Via to Metal2 3 155 A.2.3.4. Minimum Separations inimum separation refers to the separation between geometry of diflerent layers. Layers Separation Comments (design scale microns) 0.1 P-well to P+ Diff. 14 - P+ diffusion is in N-substrate 0.2 P-well to N+ Diff. 9 - N+ diffusion is in N-substrate 0.3 P+ Diff. to N+ oiff. 8 - in same su bstrate 0.4 - Poly to Device Well 4 poly is on field 0.5 Poly to P+/N+ 5 - both layers in device well 0.6 P+/N+ to Field 5 - both layers in device well 0.7 Contact to - Gate 5 gate is poly over device well 0.8 Via to Device Well 5 - via MUST be over field 0.9 Via - to Poly 5 via must NOT be over poly 0.10 P-guard to P+ Diff 9 - P+ diffusion is in N-substrate 0.11 P-guard to N+ Diff 4 - N + diffusion is in N-substrate .2.3.5. Overlaps n overlap is defined as one layer crossing over the boundary of another layer. The imension refers to the amount the inner layer extends beyond the edge of the sur r unding outer layer. Layers Overlap Comments Inner Outer (design scale microns) E.l Poly over Device Well 5 - poly overlap of gate E.2 Contact over P+ Mask 6 - extension of split contact into N + region - exception to the P + enclosing device well rule ...... 3 Contact over N Mask 6 - extension of split contact into P + region - exception to the N + enclosing device well rule 156 ·2.3.6. Pad Rules onding pad rules are required if pad frames cannot be used for an area-efficient I yout. Although the minimum allowed pad spacing is 125 microns, it is strongly r commended that the spacing between pads be as great as possible within the s lected project boundary. A maximum of 10 pads to anyone side of a 40-pin chip e sures the project is bondable. For the 68-pin PGA package, the limit is 17 pads p r side. Other packaging and assembly considerations are described in Appendix . The following is a summary of the rules related to bonding and probe pads. Minimum size bonding pad glass opening ------190 design Metal2 over glass enclosure ------10 scale Minimum bonding pad to pad metal2 spacing ------125 microns " Minimum bonding pad to unconnected circuitry separation - 67 Probe pad rules are recommendations ONLY and are a function of the type of p obing facilities and the skill of the operator. Probe pads should be dimensioned f r convenient probing. A typical size of glass opening (for operators of moderate e perience) is 100 microns by 100 microns. Probe pads are created on metal2. F .5 Recommended minimum size probe pad glass opening - - - 35 design F 6 Recommended centre to centre spacing of probe pads scale to be probed simultaneously ------215 microns There are additional via and metal rules specific to the connection of the first metall I yer to the pad on metal2 in the vicinity of the bonding pad. These mainly affect sembly yield and reliability. F 7 Minimum metal2 width connection to bonding pad - - - - - 100 design F 8 Minimum meta12 to bonding pad corner separation - - - - - 34 scale F 9 Minimum metall (eM) to glass opening separation - - - - - 44 microns 157 A.1.3.7. Capacitor Rules rules are Capacitor required only for analogue design. Capacit.ors are formed by poly over a heavily doped P+ device well in the N-substrate. The poly is the top plate, and the bottom plate is a device well covered by both the P+ mask (with associated N + exclusion mask) and the capacitor P-doping mask. A capacitor can be formed in the P-well provided that the P-doped device well of the capacitor is at the same potential as the P-well. In both cases the previous poly-contact-device well rules apply, with the following additions: G.t - Capacitor P-doping (CCP) enclosure of device well - - - - 4 design G.2 ------Capacitor P-doping enclosure of N+/P+ - - - - 0 scale G.3 Capacitor P-doped device well separation from P-well - - - 16 microns G.4 Capacitor P-doped device well separation from other ------" ------diffusions ------_ _ _ 9 " G.S ------Capacitor P-doped device well spacing - - - - 10 A.2.4. CMOSJ DLM Parameters he following list of parameters are to be used as guidelines only. There has not been ny calibration of the SPICE models with measured results. Physical dimensions, ot design-scale dimensions, are applicable to the parameters and their use. 158 .2.4.1. SPICE Transistor Parameters NMOS PMOS Units Source Description 0.7 -O.S V (1) - zero bias threshold voltage 40E-6 12E-6 (A/V') (S) - transconductance parameter 1.1 0.6 (V0'S) (1) - bulk threshold parameter 0.6 0.6 V (3) - surface potential 0.01 0.03 I/V (S) - channel-length modulation (40) (100) ohms (2) - drain ohmic resistance(w=6u) " (40) (100) ohms (2) - source ohmic resistance( ) F (2) - zero bias B-D junction cap. F (2) - zero bias B-S junction cap. A (2) - bulk junction sat. current 0.7 0.6 V (I) - bulk junction potential 3.0E-IO 2.SE-IO F/m (1) - G-S overlap capacitance 3.0E-IO 2.SE-IO F/m (1) - G-D overlap capacitance 5.0E-IO 5.0E-IO F/m (I) - G-bulk overlap capacitance 25 SO ohms/sq. (1) - diffusion sheet resistance 4.4E-4 I.SE-4 (F/m2) (I) - zero bias bulk junction cap. 0.5 0.6 (I) - bulk junction grading coef. 4.0E-IO 4.0E-IO Ffm (I) - bulk junction sidewall cap. 0.3 0.6 (I) - sidewall cap. grading coef. 1.0E-s 1.0E-5 (A/m') (I) - bulk junction sat. current 5.0E-S S.0E-8 m (1) - oxide thickness !SUB 1.7EI6 5.0E15 (1/cm3) (1) - substrate doping SS 0 0 (l/cm') (3) - surface state density FS 0 0 (l/cm2) (3) - fast surface state density PG 1 1 (3) - type of gate material J 6.0E-7 5.0E-7 m (1) - metallurgical junction depth D 3.5E-7 2.SE-7 m (I) - lateral diffusion 0 775 250 (em'/V s) (1) - surface mobility 1.0E5 0.7ES m] s (I) - maximum drift velocity ICE Level 3 Parameters NMOS PMOS Units Source Description 0.11 0.13 I/V (1) - mobility modulation 1.0 1.0 (1) - saturation field factor 0.05 0.3 (1) - static feedback 159 A.2.4.1. Other Electrical Parameters Capacitance Edge Component Source (pFlum') (pFlum) Gate (Cox) 6.9E-4 0.SE-4 (1) Metall - Field 2.7E-S 0.4E-4 (1) Metall - Poly 5.0E-S (1) Metall - Diffusion 5.0E-S (1) Poly - Field 6.0E-S 0.2E-4 (1) Metal2 - Field 1.4E-S 2.0E-5 (4) Metal2 - Diffusion I.6E-S (4) Metal2 - Poly 2.0E-5 (4) Metal2 - Metall 2.5E-5 (4) Capacitor P + - Poly 6.9E-4 0.SE-4 (*) (O.I%/V linearity) (1) Resistance (ohmsIsq.) Source N + Diffusion 2S (1) P+ Diffusion 80 (1) N+ Poly 18 (5) Capacitor P + 300 (1) P-well 4K (1) Metall 0.035 (4) Metal2 0.030 (4) 3 x 3 Metall - P+ Diffusion Contact 121 (5) 3 x 3 Metall - N+ Diffusion Contact 44 (5) 3 x 3 Metall - N+ Poly Contact 2S (S) Maximum operating voltage: 5 volts. sources:(l) - D. Smith of NTE, presented at CMC Workshop June 6-7, 1985. (2) - Calculated by SPICE: e.g.- RSH is used to calculate RD & RS. (3) - SPICE default. (4) - D. Smith of NTE, April 1986. (S) - Typical measured DC result. (*) - Estimate - Capacitors assumed to be equal to gate capacitance. 160 ....·· .... r-············ D ···l P-WELL - - - I I lllllllllllllllllllll .... I I T I t _ , : N-WELL 2:: :: t._ _j ...... '¥{I.\'.,"""'0,0 DIfF r--, I I I I L __ � P-GUARO POLY J ______ N+ p+ • CONTACT IoIETAL1 • VIA METAL2 Figure A.2 CMOS3 DLM design rules. 161 f.4 67 D P-WELL '/'� '/.-_, //, //",//. ,'"-/,,,'//"'�'//--' /1' //////_"//I' ///// //// 1.-; : " N-WELL H :.!:. li.iii.J OIF'F' '� F.3 c� � v,� 125 VI ..., P-GUARO ".; / ./ c········, <. I : L ... :.:J CAP P+ m till POLY f.467 ...... ,., ... N+ ...... :::::::::::::::::::::;::::1 p+ II CONTACT METAL1 II D �ETAL2 D GLASS Figure A.3 CMOS3 DLM pad and capacitor design rules. APPENDIX B THE GAP CMOS3 TECHNOLOGY FILE 162 163 The CMOS3 technology file (cmos3.c) in the GAP source directory IS i eluded in this appendix. include "GAP.h" include "errrep.h" / Defining Symbolic layer numbers */ define INF 0 defme PWELL 1 defme DVWELL 2 define PGUARD 3 define NGUARD 4 define CAPPOLY 5 define POLY 6 define NPLUS 7 define PPLUS 8 define CONTACT 9 define METAL 10 define VIA 11 defme METAL2 12 define GLASS 13 / Merged Layers */ define PWELLM 14 define DVWELLM 15 define PGUARDM 16 define NGUARDM 17 define CAPPOLYM 18 define POLYM 19 define NPLUSM 20 define PPLUSM 21 define CONTACTM 22 define METALM 23 define VIAM 24 define METAL2M 25 define GLASSM 26 TEMPI MAXCHIP-l TEMP2 MAXCHIP-2 TEMP3 MAXCHIP-3 TEMP4 MAXCHIP-4 l� TEMP5 MAXCHIP-9 TEMP6 MAXCHIP-IO GATE MAXCHIP-ll *define the correspondence between cif layer names and internal layer records I trcpy(lay_name[lNF].cif, ""); trcpy(lay_name[PWELL].cif, "CPW"); trcpy(lay_name[DVWELL].cif, "CF"); trcpy(lay_name[PGUARD].cif, "CPG"); trcpy(lay_name[NGUARD].cif, "CNG"); trcpy{lay_name[CAPPOLY].cif, "CCP"); trcpy{lay_name[POLY].cif, "CP"); trcpy{lay_name[NPLUS].cif, "CNP"); trcpy(lay_name[PPLUS].cif, "CPP"); trcpy(lay_name[CONTACT].cif, "CC"); trcpy(lay_name[METAL].cif, "CM"); trcpy(lay_name[VIA].cif, "CV"); trcpy(lay_name[METAL2].cif, "CM2"); trcpy(lay_name[GLASS].cif, "CG"); trcpy(lay_name[lNF].name, "infinite"); trcpy{lay_name[PWELL].name, top well"); trcpy{lay_name[DVWELL].name, "device well"); trcpy(lay_name[PGUARD].name, top guard"); trcpy(lay_name[NGUARD].name, ton well"); trcpy(lay_name[CAPPOLY].name, "capacitor poly"); trcpy(lay_name[POLY].name, "poly"); trcpy{lay_name[NPLUS].name, "N+to); trcpy(lay_name[PPLUS].name, "P+"); trcpy(lay_name[CONTACT].name, "contact"); trcpy{lay_name[METAL].name, "metal 1 to); trcpy{lay_name[VIA].name, "via"); trcpy(lay_name[METAL2].name, "metal2"); trcpy{lay_name[GLASS].name, "glass"); onvertt); c_cmos30; 165 c3_spacing[] = {O,700,O,500,500,5oo,500,O,500,500,5oo,5oo,500} ; c3_dimens[] = { -1000,-5oo,O,O,-500,-500,-5oo,-5oo,-500,-500,-5oo,-5oo,O}; dr _cmos30 /* Function : checkrules Parameters : none Operation : Checks the cmos3 rules */ ( struct polyrec *pp,*pp2; int ij,k; long ppid; char ppid_str[20]; int err_no; /*error number */ char err_string[ERRLEN]; ppid = getppidt); sprintf(ppid_str, "%ld", ppid); strcat(ppid_str, "unserrs"); if (fd = creat(ppid_str,0755» < 0) printf("*****ERROR*****\n"); printf("Unable to create error file\n"); return; r Merge all input layers */ for(i=PWELL; i <= GLASS; i++) ( intersect(i,INF,i+GLASS,NULL); kill_layer(i); 166 pp = LAYER_NO[i+GLASS].frrst; while (Pp!=NULL) ( set_origin(pp); pp = pp->next; } } kill_layerCTEMPI ); kill_layer(TEMP3); kill_layerCTEMP4); kill_layer(TEMPS); kill_layer(TEMP6); '* Check the spacing on individual layers *' for(i=PWELLM; k= GLASSM; i++)( if (c3_spacing[i-PWELLM] != 0) ( /*Only layers whose spacing is not 0 have the spacing rule checked *' pp=LAYER_NO[i].frrst; while(pp!=NULL) ( pp2 = pp->next; kill_layerCTEMPI); kill_layer(TEMP2); mv_poly(pp,TEMPI); make_tolerances(pp,-2,TEMP2,c3_spacing[i-PWELLM]); intersect(TEMPI,TEMP2,TEMP3,TEMP4); mv_layerCTEMPI,TEMPS); pp = pp2; } mv_layerCTEMPS,i); kill_layerCTEMPS); '* notch errors•••• *' SEMI(Notch too small on %s, i-PWELLM+I); read;violationsCTEMP3,err_no,TEMPI); kill_layer(TEMPI ); kill_layer(TEMP2); kill_layer(TEMP3); intersect(i,TEMP4,TEMPI,NULL); 167 1*·spacmg errors.•.••. *1 SEMI(Spacing on %s, i-PWELLM+1); read,.violations(TEMP1,err_no,i); kill_layer(TEMP1 ); kill_layer(TEMP4); } } I*Check minimum dimension rules*1 for (i=PWELLM; i<=GLASSM; i++) ( if (c3_dimens[i-PWELLM] != 0) ( I*Only layers whose minimum dimension is not 0 have this rule checked *1 SEMI(Minimum dimension on %s, i-PWELLM+1); report(-2,i,i,c3_dimens[i-PWELLM],OUTSIDE,err_no); } } 1* N+ to P+ spacing *1 SEM(N+ to P+ spacing over device well); report(-1 ,PPLUSM,NPLUSM,-EPS,OUTSIDE,err_no); kill_layer(TEMP1 ); kill_layer(TEMP2); kill_layer(TEMP3); kill_layer(TEMP4); 1* Device well spacing *1 intersect(pWELLM,DVWELLM,TEMP1,TEMP2); intersect(pPLUSM,TEMP1,TEMP3,TEMP4); intersect(PPLUSM,TEMP2,TEMPS,TEMP6); SEM(spacing between device wells with different doping); report(TEMP1,TEMP3,TEMP4,800,INSIDE,err_no); report(TEMP2,TEMPS,TEMP6,800,INSIDE,err_no); kill_layer(TEMPl ); kill_layer(TEMP2); kill_layer(TEMP3); kill_layer(TEMP4); kill_layer(TEMPS); kill_layer(TEMP6); 168 , 1* Transistor rules *1 ) kill_layer(GATE); I intersect(POLYM,DVWELLM,GATE,TEMP2); Ii SEM(Improperly formed gate); rep_trans(GATE,err_no); I, 1* Gate overlap onto field oxide is 5 *1 SEM(Gate overlap onto field); report(DVWELLM,GATE,POLYM,500,OUTSIDE,err_no); 1* Device well to poly spacing *1 SEM(Device well to poly spacing); report(DVWELLM,TEMP2,POLYM,400,INSIDE,err_no); intersect(GATE,PWELLM,TEMP3,NULL); 1* P well oversize from active channel *1 SEM(p well oversize on active channel); report(GATE,TEMP3,PWELLM,700,OUTSIDE,err_no); 1* P well oversize on non active device well *1 intersect(TEMP2,PWELLM,TEMP5,NULL); SEM(p well oversize on non-active device well); report(TEMP2,TEMP5�PWELLM,300,OUTSIDE,err_no); kill_layer(TEMPl); kill_layer(TEMP2); kill_layer(TEMP3); kill_layer(TEMP4); kill_layer(TEMP5); 1* P+ and device well overlap *1 intersect(pPLUSM,DVWELLM,TEMP1,NULL); SEM(p+ overlap of device well); report(DVWELLM,TEMPl,PPLUSM,400,OUTSIDE,err_no); kill_layer(TEMP1 ); I*P+IN+ to field spacing *1 intersect(NPLUSM,DVWELLM,TEMP2,NULL); SEM(N+ to field spacing); report(NPLUSM,TEMP2,DVWELLM,500,OUTSIDE,err_no); 1* N+ or P+ to poly spacing in device well*1 SEM(N+ to poly spacing in device well); 169 report(NPLUSM,TEMP2,GATE,500,INSIDE,err_no); kill_layer(TEMP2); 1* DVWELL Contact *1 intersect(DVWELLM,CONTACfM,TEMPl,NULL); SEM(Device well overlap of contact); report(-I,TEMPl,DVWELLM,200,OUTSIDE,err_no); SEM(Device well contact to gate spacing); report(-1,TEMPl,GATE,500,INSIDE,err_no); kill_layer(TEMPl» 1* Metal Oversize on Contact *1 SEM(Metal overlap of contact); report(-I,CONTACTM,METALM,200,OUTSIDE,err_no); 1* Poly Oversize on Contact *1 intersect(POLYM,CONTACTM,TEMPl,NULL); SEM(poly overlap of contact); report(-I,TEMPl,POLYM,200,OUTSIDE,err_no); kill_layer(TEMPl); I*Via enclosure of metal! and metal2 *1 SEM(Metal 1 enclosure of Via); report(-I,VIAM,METALM,300,OUTSIDE,err_no); SEM(Metal 2 enclosure of Via); report(-I,VIAM,METAL2M,300,OUTSIDE,err_no); I*Via to device well and poly spacing *1 SEM(Via to device well spacing); report(-I,VIAM,DVWELLM,500,INSIDE,err_no); SEM(Via to poly spacing); report(-I,VIAM,POLYM,500,INSIDE,err_no); 1* MAX Contact dimension *1 pp=LAYER_NO[CONTACTM].frrst; while(pp!=NULL) ( pp2 = pp-o-next; mv_poly(pp,TEMPl); make_tolerances(pp,-I.TEMP2,-2000-EPS); intersect(TEMPl,TEMP2,TEMP3,NULL); mv_layer(TEMPl ,TEMP4); kill_layer(TEMPl); kill_layer(TEMP2); pp = pp2; 170 } mv_layer(TEMP4,CONTACTM); SEM(Maximum contact dimension); max_dim(TEMP3,err_no); kill_layer(TEMP3); kill_layer(TEMP4); kill_layer(TEMP5); 1* P Guard *1 SEM(p guard overlap of P well); report(-1,PWELLM,PGUARDM,500,OUTSIDE,err_no); SEM(p guard to N guard spacing); report(-1,PGUARDM,NGUARDM,300,OUTSIDE,err_no); 1* P well to P+IN+ diffusion*1 intersect(pWELLM,DVWELLM,NULL,TEMP4); intersect(TEMP4,PPLUSM,TEMPI ,NULL); SEM(p well to P+ diffusion spacing); report(-1,TEMPl,PWELLM, 1400,INSIDE,err_no); intersect(NPLUSM,TEMP4,NULL,TEMP5); SEM(p well to N+ diffusion spacing); report(-I,TEMP5,PWELLM,900,INSIDE,err_no); kill_layer(TEMPI ); kill_layer(TEMP2); kill_layer(TEMP4); kill_layer(TEMP5); 1* Split Contact *1 intersect(DVWELLM,PPLUSM,TEMP3,NULL); intersect(NPLUSM,DVWELLM,NULL,TEMP4); intersect(TEMP3,CONTACTM,TEMPl,NULL); intersect(TEMP4,CONTACTM,TEMP2,NULL); SEM(Split contact to P+ overlap); report(TEMP3,TEMPI ,CONTACTM,600,OUTSIDE,err_no); SEM(Split contact to N+ overlap); report(TEMP4,TEMP2,CONTACTM,600,OUTSIDE,err_no); kill_layer(TEMPI ); kill_layer(TEMP2); close(fd); sort_errO; } APPENDIX C H RDWARE SCREEN SCANNING CIRCUIT SCHEMATICS AND RELATED EXTERNAL INTERRUPT ROUTINE 171 I i ! I 1721 I I I I This appendix includes the external interrupt routine used for hardware I I canning. It is followed by the external circuit schematic generated from *******************************************************************/ function : scan_screen */ *******************************************************************/ */ date : Aug 17, 1989 */ */ purpose : (external hardware screen scanning) */ scan for hardware-set color on the active screen */ region and record the line number of the color */ pixels in an array (line), return an non-zero */ value if particular pixels are found */ */ / *******************************************************************/ include "header.h" i t LINE[1024]; i t CHECK, COUNTERI = 0, COUNTER2 = 0, COUNTER3 = 0; i t NUM = -1, CLEAR = 0, ACfIVE = 1, DONE = 0; oid c_intOl0, c_int020; int 10w16 = Oxffff, first_line = 0; int i, temp, offset; int x = 40; int debug; debug = FALSE; /* initialize array LINE */ for(i = 0; i < 1024; i++) LINE[i] = 0; /* set CHECK flag and enable shadow RAM */ CHECK = ACfIVE; 1 poke(SHADOW_RAM, SHADOW_EN); /* load interrupt vectors */ poke(DI_VECfOR, «long)c_intOl) & lowI6); poke(DI_VECfOR + OxOOl0, «(long)c_intOl) » 16) & lowI6); poke(LINT2_VECfOR, «long)c_int02) & lowI6); poke(LINT2_VECfOR + OxOOlO, «(long)c_int02) » 16) & lowI6); /* DI at first line */ poke(DPYINT, first.Iine); /* clear any possible interrupt enable and pending */ poke(INTENB, CLEAR); poke(lNTPEND, CLEAR); /* enable global and display interrupt */ asmt" EINT If); temp = peek(INTENB); poke(INTENB, temp I DSPLY_EN); . /* scanmng ... */ while(CHECK != DONE) (;} /* disable global interrupt */ asmt" DINT If); if(COUNTER2 > 0) ( /* display interrupt line array */ offset = peek(VEBLNK) + 1; /* clear the bit_set array line on screen */ if(debug) ( set_color 1 (BLACK); draw_line(x, 0, x, Y_MAX); /* display array with current result */ for(i = 0; i < Y_MAX; i++) put_pixel(LINE[i], x, i-offset); } } retum(COUNTER2); 1 oid c_intOlO int temp; /* check if LINT2 is enabled */ temp = peek(INTENB); if(temp & LINT2_EN) ( /* SECOND display interrupt */ CHECK = DONE; !* disable DI and LINT2 */ poke(INTENB, temp & -DSPLY_LINT2_EN); COUNTER3++; } else ( /* FIRST display interrupt */ poke(INTPEND, CLEAR); r enable LINT2 */ poke(INTENB, temp I LINT2_EN); /* next DI at last line */ poke(DPYINT, Y_MAX); COUNTER1 ++; } oid c_int020 int temp; !* increment array element that corresponds to the interrupt */ temp = peek(VCOUNT); if(NUM != temp) ( LINE[temp]++; COUNTER2++; NUM = temp; ) 1 I Z 3 I 4 HI H-DIP22 � PZ PI" A """"-I ft •• '" A u. -tt1Kn� D. .. e--!! � -In�u DB2 D"7 -. .!.l.a .. � I t .___ � U3 TMS34878 ...'tH--+-t a II N 'LUW�..a." 1"1L_� IIcca II ED PI .,_-._--_...... --;n 1155 I 115521-1-ji:M:J;t I "=--oH 11111 T D II J--;�--II-II� PI" • I,���-_�DIII. H':;---II-I'H- I I',_ril.....---;M DIll gU .. B D 1112 0.) H-r--II-"'lLI. r, DIIIJ --!dT r>;:::G!tt:==!� __--' ._-,._--__�._.;.... 11551 g�����H�UT��-��-�---_J :'lJH--H:...t "DDt IICCI ����L- '_� 7 ·���"'""IDU"I' Dill TEN I--''-.:...w..... UI 74ALSSZ8 • � I _...... ---L T a I 1" 1'1 I __ • _ ... 1'2 1" I 1'4 c JI �: c JMP9 1'1 ?WbU PIMHIT ' _I�II .. � __,..,_ 01 � 02 _,..,_ DJ _,...,_ • 04 ...... t""'\- I 06 __,...,_ I 06 I-- • II Q1 �� J � 7 D �. D TMS34818 SDI ADD-O" .. '.r .. en 151..III I" III. LIIIU 1··"I 2 ••• -� - I D.' ,.-Ju[ .••• __ t I l1l'i' Irlr., ]4818'1 ""lI�... n .U!··'-:-'ULTDlf I Z I 3 1 • ..... I C.I Hardware screen schematic...... ,J I Figure scanning Ul I i i I APPENDIX D THE PROTOTYPICAL TECHNOLOGY FILE 176 i 17i ! ! I I ********************************************************************{* function: main *1 :******************************************************************:�i * purpose: this is the CMOS3 technology file. It calls *� all the rule checking functions. *t *) ********************************************************************t include "header.h" include "global.h" include "function.h" include "cmos3.h" ainO int n; int num_colors = 16; int flashing = 1; int see_layout = 1; int transistor_size = 1; int layerl_extension = 1; int layer2_extension = 1; int intra_layer_spacing = 1; int inter_layer_spacing = 1; int minimum_dimension = 1; int enclosure_check = 1; /* reset for each execution */ FINISH = FALSE; ERR = 0; LASTERR = 0; if(!INITIAL)initO; clr_structl(SOURCE); clr_structl (ERROR); clr_struct 1 (TOLER); clr_structl (TEMP); clr_struct2(ERR_EDGE); /* display the complete layout in the window */ if(see_layout) ( displayat); delay(500); clean); } /* check transistor size */ if(transistor_size) { cleart); ERR_CODE = TSlZE_ERR; if(extract(CP, CF) { displayto; tran_size(tsize); if(flashing)reportO; } } ->, /* check poly extension over gate */ if(layerl_extension) ( clean); ERR_CODE = EXTEN_ERR; if(extract(CP, CF» { displayto; lyrext(_RED, lyrl_exten); if(flashing)reportO; } } /* check diffusion extension over gate */ if(layer2_extension) { cleart); ERR_CODE = EXTEN_ERR; if(extract(CP, CF) { displayto; lyrext(_GREEN, lyr2_exten); if(flashing)reportO; } } 179 * /* check minimum spacing of the same layer / if(intra_layer_spacing) ( ERR_CODE = INTRA_ERR; for(n = 0; n < num_colors; n++) ( clean); if(c3_spacing[n]) ( if(extract(NO. n)) ( displayt); intra_spacing(c3_spacing[n]); if(flashingjreporn); } } } } 1* check minimum spacing of poly and diffusion */ if(inter_layer_spacing) ( cleart); ERR_CODE = INTER_ERR; if(extract(CP. CF)) ( displayto; inter_spacing(CP_CF_spacing); if(flashing)reportO; } } /* check minimum dimension of all cif layers */ if(minimum_dimension) ( ERR_CODE = MINDI_ERR; for(n = 0; n < num_colors; n++) ( clean); if(c3_dimens[n]) ( if(extract(NO. n)) 180 ( displayt); min_dim(c3_dimens[nD; if(flashingjreporn); } } } } /* check enclosure of poly and metal over contact */ if(enclosure_check) ( cleart); ERR_CODE = ENCLS_ERR; if(extract(CC, CM» ( displayto; enclosure(CC_CM_encls); if(flashingjreporu); } clean): if(extract(CC, CP» ( displayto; enclosure(CC_CP_encls); if(flashingjreporn); } } clean); ERR_EDGE[ERR].startx = END_TAG; FINISH = TRUE; } v id clean) ( /* clear whole screen with black */ set_ppop(REPLACE); set_pmaskCUNPROTECT); set_colorl (BLACK); 181 fIll_rect(X_MAX, Y_MAX, 0, 0); return; } v id reportO { int delay = 3; int times = 15; flash_errors(LASTERR, ERR, delay, times); LASTERR = ERR; } APPENDIX E THE LAYOUTS OF THE CHOSEN QUISC STANDARD CELLS 182 1 ,...:,. > z - -- � u > c - - . � u ... = 1 ...... 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