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United States Patent (19) 11 Patent Number: 5,809,336 Moore Et Al

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United States Patent (19) 11 Patent Number: 5,809,336 Moore Et Al USOO5809336A United States Patent (19) 11 Patent Number: 5,809,336 MOOre et al. (45) Date of Patent: Sep. 15, 1998 54 HIGH PERFORMANCE MICROPROCESSOR 4.338,675 7/1982 Palmer .................................... 364/748 HAVING WARIABLE SPEED SYSTEM 4,398,265 8/1983 Puhl et al. 395/882 CLOCK 4,453,229 6/1984 Schaire ... ... 395/250 4,503,500 3/1985 Magan ........ ... 395/800 (75) Inventors: Charles H. Moore, Woodside; Russell 4539,655 9/1985 Trussell et al. - - - - - - - - - - - - - - - - - - - - - - - - - 395/280 H. Fish, III, Mt. View, both of Calif. 4,553,201 11/1985 Pollack ............................... 395/183.22 4,627,082 12/1986 Pelgrom et al. .......................... 377/63 O O 4,670,837 6/1987 Sheets ............ ... 395/550 73 ASSignee: Patriot Scientific Corporation, San 4,680,698 7/1987 Edwards et al. 395/800 Diego, Calif. 4,761,763 8/1988 Hicks ...................................... 395/286 5,414,862 5/1995 Suzuki et al. ........................... 395/750 21 Appl. No.: 484,918 Primary Examiner David Y. Eng 22 Filed: Jun. 7, 1995 Attorney, Agent, or Firm-Cooley Godward LLP Related U.S. Application Data 57 ABSTRACT 62 Division of Ser. No. 389,334, Aug. 3, 1989, Pat. No. A high performance, low cost microprocessor System having 5,440,749. a variable speed System clock is disclosed herein. The microprocessor System includes an integrated circuit having 51) Int. Cl. 6 ........................................................ G06F 1/04 a central processing unit and a ring oscillator variable Speed 52) U.S. Cl. .............................................................. 395/845 System clock for clocking the microprocessor. The central 58 Field of Search ..................................... 395/500, 551, processing unit and ring oscillator variable Speed System 395/555,845 clock each include a plurality of electronic devices of like type, which allows the central processing unit to operate at 56) References Cited a variable processing frequency dependent upon a variable U.S. PATENT DOCUMENTS Speed of the ring oscillator variable Speed System clock. The microprocessor System may also include an input/output 3,967,104 6/1976 Brantingham ... ... 364/709.09 interface connected to exchange coupling control Signals, 3,980,993 9/1976 Bredart et al. ... ... 395/550 address and data with the central processing unit. The s: 2. Fo st al ...... 395/742395389 input/output interface is independently clocked by a Second 4,050,0962 - . 12 9/1977 BennettC. C............. a. ...O.,- - - clock connected thereto. 4,112,490 9/1978 Pohlman et al. ........................ 395/287 4,315,308 2/1982 Jackson ................................... 395/853 10 Claims, 19 Drawing Sheets R NGOSCILLATOR -430 CRYSTAL CLOCK VARIABLE SPEED CLOCK 434 432 REOUEST DATA / ADDRESS INTERFACE EXTERNAL MEMORY BUS U.S. Patent Sep. 15, 1998 Sheet 1 of 19 5,809,336 54 Z -N- 2 H C/D (2 CD CO CO S S O CO to c) C C C C CO L S U , S in CS di CS S C 3 CS 52 52 . D30 D14 D29 D13 52-K D28 SH-BOOM D12 X52 D27 MICROPROCESSOR D11 D26 D10 VDD 50 VDD D25 D9 D24 D8 44-PIN PLCC 52 - D23 D7 X52 D22 D6 D21 D5 & 2 2 2 3 3 S 3 S O C) ?) O D 52 FIG.1 U.S. Patent Sep. 15, 1998 Sheet 2 of 19 5,809,336 146 144 INCREMENTER 122 84 PARAMETER X REGISTER CO STACK 741 16 DEEP 124 CO 130 14O 90 ESERAMUNTER CC 94 itLOOP * 108 COUNTER Z O STACK f O 2 YN 70 POINTER f 12 RSTACK y 1041 POINTER 14 1 Y REGISTER MODE f36 106 1 REGISTER ff 6 72 108 NSTRUCTION RETURN REGISTER STACK & LOCAL VARABLES 16 DEEP MEMORY CONTROLLER 151 ADDRESS/ CONTROL Y-so DATA LINES FIG.2 U.S. Patent Sep. 15, 1998 Sheet 3 of 19 5,809,336 RAS DECODE LOGIC FIG.3 U.S. Patent Sep. 15, 1998 Sheet 4 of 19 5,809,336 130 PROGRAM COUNTER r INTERNAL SIGNALS REGUEST INSTRUCTION f36 FETCH-AHEAD f 18 MEMORY CONTROLLER 198 2OO ADDRESS/ CONTROL DATA LINES FIG.4 U.S. Patent Sep. 15, 1998 Sheet 5 of 19 5,809,336 246 SYSTEM CLOCK 2.TRANSFER SIZE 250 COUNTER 248 22O 236 MEMORY CYCLE 222 ACKNOWLEDGE - 1 2.TRANSFER SIZE 240 COUNTER 238 216 2 DMA INSTRUCTION DONE 242 12 24 DMA PROGRAM COUNTER 232 90 212 DMA I/O & DMA I/O & RAMADDRESS RAMADDRESS 136 2 REGISTER REGISTER MEMORY CYCLE 23O RECQUEST 228 f 18 32 MEMORY CONTROLLER 32 6 ADDRESS/ CONTROL DATA LINES FIG.5 U.S. Patent Sep. 15, 1998 Sheet 6 of 19 5,809,336 DRAMRAS 26O EPROM SH-BOOM 274 FIG.6 U.S. Patent Sep. 15, 1998 Sheet 7 of 19 5,809,336 U2 U3 296 U 284 -1 292 296 SH-BOOM 28O U1 U6 296 264 )/ 292 282 296 FIG.7 U.S. Patent Sep. 15, 1998 Sheet 8 of 19 5,809,336 28O FIG.8 U.S. Patent Sep. 15, 1998 Sheet 9 of 19 5,809,336 32K BYTES 32K BYTES 312 316 RSTACK CLOCK/TIMING ISS. NSTRUCTION 316 DECODE 316 DMA CPU 314 32K BYTES 32K BYTES 3ff 311 FIG.9 U.S. Patent Sep. 15, 1998 Sheet 10 of 19 5,809,336 U.S. Patent Sep. 15, 1998 Sheet 11 of 19 5,809,336 % 2-BITS OF DATA FROM SH-B OOM al M Y 2 N DRAM CASN N ADDRESS N Z LOETES S_LIE EXTERNAL ADDRESS / DATABUS U.S. Patent Sep. 15, 1998 Sheet 12 of 19 5,809,336 ETO U.S. Patent Sep. 15, 1998 Sheet 13 of 19 5,809,336 REGISTER ARRAY COMPUTATION STACK DATABUS TOP OF STACK NEXT ITEM REGISTER ADDRESS BUS FIG. 13 U.S. Patent Sep. 15, 1998 Sheet 14 of 19 5,809,336 ON CHIP ON CIRCUIT BOARD 150 OUTPUT ENABLE 50 FIG, 14 OE-BAR VOLS FEW MEMORY CHIPS MANY MEMORY CHIPS O 5 TIME (NANOSECONDS) FIG.15 U.S. Patent Sep. 15, 1998 Sheet 15 of 19 5,809,336 32-BIT INSTRUCTION REGISTER 8 BITS 8 BITS 8 BITS 8 BITS 1 O8 180 2-BIT MULTIPLEXER COUNTER INSTRUCTION RESET COUNTER DECODE LOGIC INCREMENT COUNTER LATCH NEXT INSTRUCTION GROUP CONTROL SIGNALS FIG 16 PHASE O PHASE 1 PHASE 2 PHASE 3 FIG. 18 U.S. Patent Sep. 15, 1998 Sheet 16 of 19 5,809,336 RING OSCILLATOR 430 CRYSTAL CLOCK VARABLE SPEED CLOCK 434 432 REGUEST CPU READY I/O DATA / ADDRESS INTERFACE EXTERNAL MEMORY BUS FIG. 17 PHASE 433 O TIME FIG. 19 U.S. Patent Sep. 15, 1998 Sheet 17 of 19 5,809,336 32-BIT INSTRUCTION REGISTER 8 BITS 8 BITS 8 BITS 8 BITS 108 O 442 3 SELECTS DECODER 18O 2-BIT MULTIPLEXER COUNTER INSTRUCTION DECODE LOGIC CONTROL SIGNALS FIG20 U.S. Patent Sep. 15, 1998 Sheet 18 of 19 5,809,336 ON-CHIP 2 ADDRESS LINES LATCHES 2-BIT CACHE 450 - 1 POINTER 4 ADDRESS LINES READ 4-BIT ON-CHIP WRITE STACK POINTER ON-CHIP RAM 452 -- O s LL s s 20 ADDRESS LINES EXTERNAL READ 20-BIT EXTERNAL 454RAM - WRITE STACK POINTER FIG.21 U.S. Patent Sep. 15, 1998 Sheet 19 of 19 5,809,336 DOWN COUNT 472 ZERO DETECT 474 478 A REGISTER SHIFTER 470 C REGISTER XOR 476 48 O B REGISTER SHIFTER LEAST SIGNIFICANT BIT FIG.22 DOWN COUNTER COUNT 472 ZERO DETECT 474 482 470 SHIFT C REGISTER LEFT ADD 476 48O LEAST SIGNIFICANT BIT FIG.23 5,809,336 1 2 HIGH PERFORMANCE MCROPROCESSOR It is a further object of the invention to provide a high HAVING WARIABLE SPEED SYSTEM performance microprocessor in which DMA does not CLOCK require use of the main CPU during DMA requests and responses and which provides very rapid DMA response CROSS REFERENCE TO RELATED with predictable response times. APPLICATIONS The attainment of these and related objects may be This application is a division of U.S. application Ser. No. achieved through use of the novel high performance, low 07/389,334, filed Aug. 3, 1989, now U.S. Pat. No. 5,440, cost microprocessor herein disclosed. In accordance with 749. one aspect of the invention, a microprocessor System in accordance with this invention has a central processing unit, BACKGROUND OF THE INVENTION a dynamic random access memory and a bus connecting the central processing unit to the dynamic random acceSS 1. Field of the Invention memory. There is a multiplexing means on the bus between The present invention relates generally to a simplified, the central processing unit and the dynamic random access reduced instruction set computer (RISC) microprocessor. 15 memory. The multiplexing means is connected and config More particularly, it relates to Such a microprocessor which ured to provide row addresses, column addresses and data on is capable of performance levels of, for example, 20 million the bus. instructions per second (MIPS) at a price of, for example, 20 In accordance with another aspect of the invention, the dollars. microprocessor System has a means connected to the bus for 2. Description of the Prior Art fetching instructions for the central processing unit on the Since the invention of the microprocessor, improvements bus. The means for fetching instructions is configured to in its design have taken two different approaches. In the first fetch multiple Sequential instructions in a Single memory approach, a brute force gain in performance has been cycle. In a variation of this aspect of the invention, a programmable read only memory containing instructions for achieved through the provision of greater numbers of faster 25 transistors in the microprocessor integrated circuit and an the central processing unit is connected to the bus.
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