DOCSLIB.ORG

United States Patent (19) 11 Patent Number: 5,440,749 Moore Et Al

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
United States Patent (19) 11 Patent Number: 5,440,749 Moore Et Al USOO544O749A United States Patent (19) 11 Patent Number: 5,440,749 Moore et al. 45 Date of Patent: Aug. 8, 1995 54 HIGH PERFORMANCE, LOW COST 4,713,749 12/1987 Magar et al. ........................ 395/375 MCROPROCESSOR ARCHITECTURE 4,714,994 12/1987 Oklobdzija et al. ................ 395/375 4,720,812 1/1988 Kao et al. ............................ 395/700 75 Inventors: Charles H. Moore, Woodside; 4,772,888 9/1988 Kimura .......... ... 340/825.5 Russell H. Fish, III, Mt. View, both 4,777,591 10/1988 Chang et al. ........................ 395/800 of Calif. 4,787,032 11/1988 Culley et al. ........................ 364/200 - 4,803,621 2/1989 Kelly ................................... 395/400 (73) Assignee: Nanotronics Corporation, Eagle 4,860,198 8/1989 Takenaka ... ... 364/DIG. Point, Oreg. 4,870,562 9/1989 Kimoto ...... ... 364/DIG. 1 4,931,986 6/1990 Daniel et al. ........................ 395/550 21 Appl. No.: 389,334 5,036,460 7/1991 Takahira ............................. 395/425 22 Filed: Aug. 3, 1989 5,070,451 12/1991 Moore et al. ....................... 395/375 5,127,091 6/1992 Bonfarah ............................. 395/375 511 Int. Cl'................................................ GO6F 9/22 52 U.S. Cl. .................................... 395/800; 364/931; OTHER PUBLICATIONS 364/925.6; 364/937.1; 364/965.4; (2. Intel 80386 Programmer's Reference Manual, 1986. 58) Field of Search ................ 395/425,725,775, 800 Attorney,Primary ExaminerAgent, or Firm-CooleyDavid Y. Eng Godward Castro 56) References Cited Huddleson & Tatum U.S. PATENT DOCUMENTS 57 ABSTRACT 3,603,934 9/1971 Heath ........................... 364/DIG. 4,003,033 1/1977 O'Keefe et al. ..................... 364/200 A microprocessor (50) includes a main central process 4,037,090 7/1977 Raymond............................ 364/200 ing unit (CPU) (70) and a separate direct memory access 4,042,972 8/1977 Grunes et al. ...................... 364/200 (DMA) CPU (72) in a single integrated circuit making 4,050,058 9/1977 Garlic .................................. 395/800 up the microprocessor (50). The main CPU (70) has a 4,067,059 1/1978 Derchak 364/TDIG. 1 first 16 deep push down tack (74), which has a to item 4,079,455 3/1978 Ozga ................................... 395/800 register (76) and a next item register (78), respectively 4,110,822 8/1978 Porter ................................. 364/200 connected to provide inputs to an arithmetic logic unit 4,125,871 11/1978 Martin ... 364/TDIG. 2 (ALU) (80) by lines (82) and (84). An output of the 4,128,873 12/1978 Lamiaux .............................. 364/200 4,255,785 3/1981 Chamberlin ... ... 395/375 ALU (80) is connected to the top item register at (82) is 4,354,228 10/1982 Moore et al. ....................... 364/200 also connected by line (88) to an internal data bus (90). 4,376,977 3/1983 Brunshorst ... ... 364/DIG. 1 CPU (70) is pipeline free. The simplified CPU (70) re 4,382,279 5/1983 Mgon ................................. 364/200 quires fewer transistors to implement than pipelined 4,403,303 9/1983 Howes et al. ....................... 364/900 architectures, yet produces performance which 4,450,519 5/1984 Guttaget al. ....................... 364/200 matches or exceeds existing techniques. The DMA 4,463,421 7/1984 Laws ................................... 395/325 CPU (72) provides inputs to the memory controller 4,538,239 8/1985 Magar ................................. 364/759 (118) on line (148). The memory controller (118) is 4,541,045 9/1985 Kromer ............................... 395/375 connected to a RAM by address/data bus (150) and 4,562,537 12/1985 Barnett et al. ...................... 395/375 4,577,282 3/1986 Caudel et al...... ... 395/800 control lines (152). The DMA CPU (72) enables the 4,607,332 8/1986 Goldberg .......... ... 364/900 CPU (70) to execute instructions four times faster than 4,626,988 12/1986 George et al. ... 364/200 the RAM speed by fetching four instructions in a single 4,649,471 3/1987 Briggs ................................. 395/325 memory cycle. 4,665,495 5/1987 Thaden ............................... 345/85 4,709,329 li/1987 Hecker ................................ 395/275 29 Claims, 19 Drawing Sheets U.S. Patent Aug. 8, 1995 Sheet 1 of 19 5,440,749 52 SH-BOOM D12 X52 MICROPROCESSOR 44-PIN PLCC 52 52 FIG.1 U.S. Patent Aug. 8, 1995 Sheet 2 of 19 5,440,749 INTERNALDATABUS 146 144 120 82 76 INCREMENTER TOP OF SACK 2 86 2 128 138 NEXT TEM 78 84 PARAMETER XREGISTER SACK 741 16DEEP 24. 130 140 90 92 PROGRAM COUNTER LOOP COUNTER STACK iO2 70 POINTER 112 RSACK N 104 POINTER f f 4. Y REGISTER MODE O6 136 REGISTER f f 6 -.72 O3 NSTRUCTION RETURN REGISTER DMA CPU SACK LOCAL VARABLES 6 DEEP 118 MEMORY CONTROLLER 151 32 7 ADDRESS/ CONTROL DATA LINES FIG.2 U.S. Patent Aug. 8, 1995 Sheet 3 of 19 5,440,749 RAS DECODE LOGIC U.S. Patent Aug. 8, 1995 Sheet 4 of 19 5,440,749 130 PROGRAM COUNTER as a ra as NTERNAL SIGNALS REGUEST INSTRUCTION 136 FETCH-AHEAD 118 MEMORY CONTROLLER 198 200 ADDRESS/ CONTROL DATA LNES FIG.4 U.S. Patent Aug. 8, 1995 Sheet 5 of 19 5,440,749 cf) CO 2 246 o. SYSTEM CLOCK 2. O g TRANSFER SIZE 2. 250 COUNTER G f 248 220 2 He 236 2 ACKNOWLEDGEMEMORY CYCLE as 222 -1 TRANSFER SIZE 240 COUNTER 238 216-1 2 2 DMA INSTRUCTION DONE N242 f 24 DMA PROGRAM COUNTER - 232 90 22 u1 DMA I/O & DMA I/O & 72 RAMADDRESS RAMADDRESS 136 REGISTER REGISTER MEMORY CYCLE 230 REGUEST 228 118 32 MEMORY CONTROLLER 32 6 ADDRESS/ CONTROL DATA LINES FIG.5 U.S. Patent Aug. 8, 1995 Sheet 6 of 19 5,440,749 DRAMRAS SH-BOOM 274 FIG.6 U.S. Patent Aug. 8, 1995 Sheet 7 of 19 5,440,749 296 4. 286 288 290 CN - 296 284 1. 292 296 SH-BOOM 280 U U6 296 292 284 )/ 282 C2 296 294 U7 X1 298 O \ J6 300 O 3 FIG.7 U.S. Patent Aug. 8, 1995 Sheet 8 of 19 5,440,749 280 FIG.8 U.S. Patent Aug. 8, 1995 Sheet 9 of 19 5,440,749 32K BYTES 32K BYTES 316 RSTACK HEHE H SACK CLOCK/TIMING ISS. INSTRUCTION 316 DECODE 316 DMA CPU 314 32K BYTES 32K BYTES 3ff 311 FIG.9 U.S. Patent Aug. 8, 1995 Sheet 10 of 19 5,440,749 TESWOHc] WO?ld LOETES SV?TVOI/WHOWE'W EGIOOEG --- s: HEICTHOH?IH SLIKESSEHCJCIV U.S. Patent Aug. 8, 1995 Sheet 11 of 19 5,440,749 ll •No. 26 --,?•-s=- U.S. Patent Aug. 8, 1995 Sheet 13 of 19 5,440,749 REGISTERARRAY COMPUTATION STACK DATABUS REGISTER O TOP OF STACK REGISTER 1 NEXT TEM REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 REGISTER ADDRESS BUS FIG. 13 U.S. Patent Aug. 8, 1995 Sheet 14 of 19 5,440,749 ON CHIP ON CIRCUIT BOARD 150 OUTPUTENABLE 50 FIG 14 OE-BAR VOLTS FEW MEMORY CHiPS MANY MEMORY CHIPS O 5 TIME (NANOSECONDS) FIG.15 U.S. Patent Aug. 8, 1995 Sheet 15 of 19 5,440,749 32-BIT INSTRUCTION REGISTER 8 BITS 8 BITS 8 BITS 8 BITS 108 2-BIT MULTIPLEXER COUNTER INSTRUCTION RESET COUNTER DECODE LOGIC INCREMENT COUNTER LATCH NEXT INSTRUCTION GROUP CONTROL SIGNALS FIG 16 PHASE O PHASE PHASE 2 PHASE 3 U.S. Patent Aug. 8, 1995 Sheet 16 of 19 5,440,749 RING COUNTER 430 CRYSTAL CLOCK VARABLE SPEED CLOCK 434 7O 432 REGUEST CPU READY I/O - DATA/ ADDRESS INTERFACE EXTERNAL MEMORY BUS FIG.17 PHASE 3 L -439 2 1 433 O TIME FIG. 19 U.S. Patent Aug. 8, 1995 Sheet 17 of 19 5,440,749 32-BIT INSTRUCTION REGISTER 8 BTS 8 BITS 8 BITS 8 BITS 108 O 442 3 SELECTS DECODER 180 2-BIT MULTIPLEXER COUNTER INSTRUCTION — DECODE LOGIC CONTROLSIGNALS FIG20 U.S. Patent Aug. 8, 1995 Sheet 18 of 19 5,440,749 SNSE 2-BT CACHE 450 - POINTER 456 O - - c Na N1 C O 458 4-BIT ON-CHIP SACK POINTER 458 ON-CHIP RAM 452 -- 458 P N1 N1 Sl 9. ot 20 ADDRESS LINES EXTERNAL READ 20-BIT EXTERNA 454RAM -1 WRITE SACK POINTER FIG.21 U.S. Patent Aug. 8, 1995 Sheet 19 of 19 5,440,749 DOWN COUNTER COUNT 472 ZERO DETECT 474 478 80 A REGISTER SHIFTER 470 C REGISTER 476 B REGISTER LEAST SIGNIFICANT BIT FIG.22 DOWN COUNTER COUNT 472 ZERO DETECT 474 A REGISTER 470 SHIFT C REGISTER LEFT 476 B REGISTER LEAST SIGNIFICANT BIT FIG.23 5,440,749 1 2 The attainment of these and related objects may be HIGH PERFORMANCE, LOW COST achieved through use of the novel high performance, MICROPROCESSOR ARCHITECTURE low cost microprocessor herein disclosed. In accor dance with one aspect of the invention, a microproces BACKGROUND OF THE INVENTION 5 sor system in accordance with this invention has a cen 1. Field of the Invention tral processing unit, a dynamic random access memory The present invention relates generally to a simpli and a bus connecting the central processing unit to the fied, reduced instruction set computer (RISC) micro dynamic random access memory. There is a multiplex processor. More particularly, it relates to such a micro ing means on the bus between the central processing processor which is capable of performance levels of, for O unit and the dynamic random access memory. The mul example, 20 million instructions per second (MIPS) at a tiplexing means is connected and configured to provide price of, for example, 20 dollars. row addresses, column addresses and data on the bus.
Load more

Recommended publications
  • Emerging Technologies Multi/Parallel Processing
    Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ...........
    [Show full text]
  • I TMS34010 I Development ~ I Board : User's Guide
    SPVU002A j ~ 1 r l I TMS34010 ~ I S £ ~ i Oltware i Development ~ I Board 0. 1 ~ :I User's Guide .., TEXAS INSTRUMENTS TMS34010 Software Developtnent Board User's Guide ~ TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes in the devices or the device specifications identified in this publication without notice. TI advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. In the absence of written agreement to the contrary, TI assumes no liability for TI applications assistance, customer's product design, or infringement of pat­ ents or copyrights of third parties by or arising from use of semiconduct9r devices described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of TI covering or relating to any combination, ma­ chine, or process in which such semiconductor devices might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits for computing devices persuant to Sub­ part J of Part 15 of FCC rules, which are designed to provide reasonable pro­ tection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications. In which case the user at this own expense will be required to take whatever measures may be required to correct the interference.
    [Show full text]
  • Supercomputers: Current Status and Future Trends
    Supercomputers: Current Status and Future Trends Presentation to Melbourne PC Users Group, Inc. August 2nd, 2016 http://levlafayette.com 0.0 About Your Speaker 0.1 Lev works as the HPC and Training Officer at the University of Melbourne, and do the day-to-day administration of the Spartan HPC/Cloud hybrid and the Edward HPC. 0.2 Prior to that he worked for several years at the Victorian Partnership for Advanced Computing, which he looked after the Tango and Trifid systems and taught researchers at 17 different universities and research institutions. Prior to that he worked for the East Timorese government, and prior to that the Parliament of Victoria. 0.3 He is involved in various community organisations, collect degrees, learns languages, designs games, and writes books for fun. 0.4 You can stalk him at: http://levlafayette.com or https://www.linkedin.com/in/levlafayette 1.0 What is a Supercomputer anyway? 1.1 A supercomputer is a rather nebulous term for any computer system that is at the frontline of current processing capacity. 1.2 The Top500 metric (http://top500.org) measures pure speed of floating point operations with LINPACK. The HPC Challenge uses a variety of metrics (floating point calculation speed, matrix calculations, sustainable memory bandwidth, paired processor communications, random memory updates, discrete Fourier transforms, and communication bandwidth and latency). 1.3 The term supercomputer is not quite the same as "high performance computer", and not quite the same as "cluster computing", and not quite the same as "scientific (or research) computing". 2.0 What are they used for? 2.1 Typically used for complex calculations where many cores are required to operate in a tightly coupled fashion, or for extremely large collections datasets where many cores are required to carry out the analysis simultaneously.
    [Show full text]
  • STK-6401 the Affordable Mini-Supercomputer with Muscle
    STK-6401 The Affordable Mini-Supercomputer with Muscle I I II ~~. STKIII SUPERTEK COMPUTERS STK-6401 - The Affordable Mini-Supercomputer with Muscle The STK-6401 is a high-performance design supports two vector reads, one more than 300 third-party and public mini-supercomputer which is fully vector write, and one I/O transfer domain applications developed for compatible with the Cray X-MP/ 48™ with an aggregate bandwidth of the Cray 1 ™ and Cray X-MP instruction set, including some 640 MB/s. Bank conflicts are reduced architectures. important operations not found to a minimum by a 16-way, fully A UNIX™ environment is also in the low-end Cray machines. interleaved structure. available under CTSS. The system design combines Coupled with the multi-ported vec­ advanced TTL/CMOS technologies tor register file and a built-in vector Concurrent Interactive and with a highly optimized architecture. chaining capability, the Memory Unit Batch Processing By taking advantage of mature, makes most vector operations run as CTSS accommodates the differing multiple-sourced off-the-shelf devices, if they were efficient memory-to­ requirements of applications develop­ the STK-6401 offers performance memory operations. This important ment and long-running, computa­ equal to or better than comparable feature is not offered in most of the tionally intensive codes. As a result, mini-supers at approximately half machines on the market today. concurrent interactive and batch their cost. 110 Subsystem access to the STK-6401 is supported Additional benefits of this design with no degradation in system per­ The I/O subsystem of the STK-6401 approach are much smaller size, formance.
    [Show full text]
  • Desktop Cyber 2.1 Operator\S and User\S Guide
    čťťťĘĘťť DPOUSPMGSFBLT PSH '(6.723&<%(5 23(5$725¶6$1'86(5¶6*8,'( &'&23(5$7,1*6<67(06 0(&&126365 90001100 2 i INDEX OF CONSOLE COMMANDS Command Mode Page Command Mode Page * DSD 2-15 LOCK DSD 2-13 Account Management DSD 2-22 LOGOFF DSD 2-13 ASSIGN DSD 2-12 MESSAGE DSD 2-13 AUTO DSD 2-12 MOVE O26 2-21 BLITZ DSD 2-12 O26 DIS 2-18 CFO DSD 2-12 O26 Special Keys O26 2-19 CHECK POINT SYSTEM DSD 2-12 OFF DSD 2-14 CKP DSD 2-12 OFFSW DSD 2-14 COMMENT DSD 2-12 ON DSD 2-14 COPY O26 2-21 ONSW DSD 2-14 D O26 2-21 OUT O26 2-21 DCP DIS 2-18 OVERRIDE DSD 2-14 DEBUG DSD 2-12 P O26 2-21 DIAL DSD 2-13 PURGE DSD 2-14 DIS DSD 2-13 RCP DIS 2-18 DIS O26 2-20 READ O26 2-20 DIS Displays DIS 2-16 REWIND O26 2-20 DISABLE DSD 2-13 RNR O26 2-21 DROP DSD 2-13 RNS DIS 2-18 DROP DIS 2-18 ROLLIN DSD 2-14 DROP O26 2-20 ROLLOUT DSD 2-14 DSD Displays DSD 2-9 ROLLOUT DIS 2-19 ELS DIS 2-18 RS O26 2-21 ENA DIS 2-18 STEP DSD 2-14 ENABLE DSD 2-13 SUI DIS 2-19 ENB DIS 2-18 SUN DIS 2-19 ENP DIS 2-18 UCC O26 2-21 ENS DIS 2-18 UNLOAD DSD 2-15 ENX DIS 2-18 UNLOCK DSD 2-15 FILE O26 2-20 UNSTEP DSD 2-15 FORM DSD 2-13 VSN DSD 2-15 GO DSD 2-13 WARN DSD 2-15 HOLD DIS 2-18 WRITE O26 2-21 IDLE DSD 2-13 X DSD 2-15 KILL DSD 2-13 XDIS O26 2-20 L O26 2-21 XDROP O26 2-20 LOAD Operator 2-41 Interface 90001100 A REVISION RECORD REVISION DESCRIPTION 1 Change bars will be made in the text to reflect edits made before the first production (1-1-2005) release.
    [Show full text]
  • DE86 006665 Comparison of the CRAY X-MP-4, Fujitsu VP-200, And
    Distribution Category: Mathematics and Computers General (UC-32) ANL--85-1 9 DE86 006665 ARGONNE NATIONAL LABORATORY 9700 South Cass Avenue Argonne, Illinois 60439 Comparison of the CRAY X-MP-4, Fujitsu VP-200, and Hitachi S-810/20: An Argonne Perspcctive Jack J. Dongarra Mathematics and Computer Science Division and Alan Hinds Computing Services October 1985 DISCLAIMER This report was prepared as an account of work sponsored by an agency o h ntdSae Government. Neither the United States Government nor any agency of the United States employees, makes any warranty, express or implied, or assumes ancy thereof, nor any of their bility for the accuracy, completeness, or usefulness of any informany legal liability or responsi- process disclosed, or represents that its use would nyinformation, apparatus, product, or ence enceherinherein tooay any specificcomriseii commercial rdt not infringe privately owned rights. Refer- product, process, or service by trade name, trademak manufacturer, or otherwise does not necessarily constitute or imply itsenrme, r ark, mendation, or favoring by the United States Government or any ag endorsement, recom- and opinions of authors expressed herein do not necessarily st agency thereof. The views United States Government or any agency thereof.ry to or reflect those of the DISTRIBUTION OF THIS DOCUMENT IS UNLIMITE Table of Contents List of Tables v List of Figures v Abstract 1 1. Introduction 1 2. Architectures 1 2.1 CRAY X-MP 2 2.2 Fujitsu VP-200 4 2.3 Hitachi S-810/20 6 3. Comparison of Computers 8 3.1 IBM Compatibility
    [Show full text]
  • CLIPPER™ C100 32-Bit Compute Engine
    INTErG?RH CLIPPER™ C100 32-Bit Compute Engine Dec. 1987 Advanced Processor Division Data Sheet Intergraph is a registered trademark and CLIPPER is a trademark of Intergraph Corporation. UNIX is a trademark of AT&T Bell Laboratories. Copyright © 1987 Intergraph Corporation. Printed in U.S.A. T CLIPPER !! C100 32-Bit Compute Engine Advance Information Table of Contents 7. Cache and MMU .......................... 40 7.1. Functional Overview ...................... 40 1. Introduction ............................... 1 7.2. Memory Management Unit (MMU) ........... 43 1.1. CPU .................................... 3 7.2.1. Translation Lookaside Buffer (TLB) .... 43 1 .1.1. Pipelining and Concurrency ............ 3 7.2.2. Fixed Address Translation ........... 46 1.1.2. Integer Execution Unit ................ 4 7.2.3. Dynamic Translation Unit (DTU) ....... 48 1.1.3. Floating-Point Execution Unit (FPU) ..... 4 7.3. Cache ................................. 51 1.1.4. Macro Instruction Unit ................ 5 7.3.1. Cache Une Description .............. 51 1.2. CAMMU ................................. 6 7.3.2. Cache Data Selection ............... 52 1.2.1. Instruction and Data Caches ........... 6 7.3.3. Prefetch .......................... 52 1.2.2. Memory Management Unit (MMU) ...... 6 7.3.4. Quadword Data Transfers ............ 53 1.3. Clock Control Unit ......................... 6 7.4. System Tag ............................ 53 2. Memory Organization ....................... 6 7.4.1. System Tags 0 - 5 .................. 53 2.1. Data Types .............................. 8 7.4.2. System Tag 6-Cache Purge ......... 54 3. Programming Model ........................ 8 7.4.3. System Tag 7-Slave 110 ........... 54 3.1. Register Sets ........................... 10 7.5. Bus Watch Modes ....................... 55 3.1.1. User and Supervisor Registers ........ 11 7.6. Internal Registers ........................ 56 3.1.2.
    [Show full text]
  • "TMS340 Family C Source Debugger User's Guide"
    TMS340 Family C Source Debugger User’s Guide SPVU021A 2564010–9721 Rev. A September 1991 Printed on Recycled Paper Running Title 1-2 Chapter Title TMS340 Family C Source Debugger Reference Card Phone Numbers TI Customer Response Center (CRC) Hotline: (800) 336–5236 Graphics Hotline: (713) 274–2340 Debugging TIGA Applications Before invoking the debugger, install the TIGA communication driver: Development Board: TIGACD / D2 Execute TIGACOM on the target system. Execute DEBUGCOM on the host system. Emulator: TIGACD / D1 Invoking the Debugger Development Board: db340 [filename][–options] Emulator: db340emu [filename][–options] Debugger Options Option Description –b[bbbb] Screen size options. Option Chars./Lines Notes none 80 X 25 Default display –b 80 X 43† Use any EGA 80 X 50‡ or VGA card –bb 120 X 43 –bbb 132 X 43 Supported on a –bbbb 80 X 60 Video Seven –bbbbb 100 X 60 VEGA Deluxe card –i pathname Identifies additional directories that con- tain source files. –mc Tells the debugger to provide ’34082 support. –mf Tells the debugger to expect IEEE floa- ting–point format. –mi Tells the debugger not to initialize the program counter (PC) or the stack point- er (SP). †† † EGA card ‡ VGA card †† Development Board Version only 1 Debugger Options Option Description –p port address Emulator only. If you used nondefault switch settings, you must use –p. Switch 1 Switch 2 Option on on –p 220 on off none needed off on –p 300 off off –p 3E0 –s Tells the debugger to load filename’s symbol table only. –t filename Specifies an initialization command file to be used instead of init.cmd.
    [Show full text]
  • Sistemas Operacionais
    Sistemas Operacionais Introdução Informações Gerais Site http://www.inf.ufes.br/~rgomes/so.htm Email [email protected] Sistemas Operacionais Objetivo do Curso Apresentar os fundamentos teóricos dos sistemas operacionais modernos, enfatizando os seus aspectos de organização interna (arquitetura conceitual) e de estruturas e mecanismos de implementação. Sistemas Operacionais Sistema de Computação Hardware Provê os recursos básicos de computação (UCP, memória, dispositivos de E/S). Programas de aplicação Definem as maneiras pelas quais os recursos do sistema são usados para resolver os problemas computacionais dos usuários (compiladores, sistemas de banco de dados, video games, programas financeiros, etc.). Usuários Pessoas, máquinas, outros computadores. Sistemas Operacionais Visão Abstrata (1) Visão Abstrata (2) Fato O hardware de um computador, sozinho, não fornece um ambiente simples, flexível e adequado para o desenvolvimento e uso dos programas de aplicação dos usuários. Sistemas Operacionais Um Sistema Operacional... ... possibilita o uso eficiente e controlado dos diversos componentes de hardware do computador (unidade central de processamento, memória, dispositivos de entrada e saída). ... implementa políticas e estruturas de software de modo a assegurar um melhor desempenho do sistema de computação como um todo. Sistemas Operacionais Definição (1) Nome dado a um conjunto de programas que trabalham de modo cooperativo com o objetivo de prover uma máquina mais flexível e adequada ao programador do que aquela apresentada pelo hardware sozinho. Interface de programação Gerenciamento de recursos Sistemas Operacionais Definição (2) “A program that controls the execution of application programs.” “An interface between applications and hardware.” “Programa que age como um intermediário entre o usuário de um computador e o hardware deste computador”.
    [Show full text]
  • Chippewa Operating System
    Chippewa Operating System The Chippewa Operating System often called COS was the operating system for the CDC 6600 supercomputer, generally considered the first super computer in the world. The Chippewa was initially developed as an experimental system, but was then also deployed on other CDC 6000 machines. The Chippewa Operating System often called COS is the discontinued operating system for the CDC 6600 supercomputer, generally considered the first super computer in the world. The Chippewa was initially developed as an experimental system, but was then also deployed on other CDC 6000 machines. The Chippewa was a rather simple job control oriented system derived from the earlier CDC 3000 which later influenced Kronos and SCOPE. The name of the system was based on the Chippewa Falls research and The Chippewa Operating System often called COS was the operating system for the CDC 6600 supercomputer, generally considered the first super computer in the world.[1] The Chippewa was initially developed as an experimental system, but was then also deployed on other CDC 6000 machines.[2]. Bibliography. Peterson, J. B. (1969). CDC 6600 control cards, Chippewa Operating System. U.S. Dept. of the Interior. Categories: Operating systems. Supercomputing. Wikimedia Foundation. 2010. The Chippewa Operating System often called COS was the operating system for the CDC 6600 supercomputer, generally considered the first super computer in the world.[1] The Chippewa was initially developed as an experimental system, but was then also deployed on other CDC 6000 machines.[2]. This operating system at Control Data Corporation was distinct from and preceded the Cray Operating System (also called COS) at Cray.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • A Rapid and Scalable Approach to Planetary Defense Against Asteroid Impactors
    THE LEAGUE OF EXTRAORDINARY MACHINES: A RAPID AND SCALABLE APPROACH TO PLANETARY DEFENSE AGAINST ASTEROID IMPACTORS Version 1.0 NASA INSTITUTE FOR ADVANCED CONCEPTS (NIAC) PHASE I FINAL REPORT THE LEAGUE OF EXTRAORDINARY MACHINES: A RAPID AND SCALABLE APPROACH TO PLANETARY DEFENSE AGAINST ASTEROID IMPACTORS Prepared by J. OLDS, A. CHARANIA, M. GRAHAM, AND J. WALLACE SPACEWORKS ENGINEERING, INC. (SEI) 1200 Ashwood Parkway, Suite 506 Atlanta, GA 30338 (770) 379-8000, (770)379-8001 Fax www.sei.aero [email protected] 30 April 2004 Version 1.0 Prepared for ROBERT A. CASSANOVA NASA INSTITUTE FOR ADVANCED CONCEPTS (NIAC) UNIVERSITIES SPACE RESEARCH ASSOCIATION (USRA) 75 5th Street, N.W. Suite 318 Atlanta, GA 30308 (404) 347-9633, (404) 347-9638 Fax www.niac.usra.edu [email protected] NIAC CALL FOR PROPOSALS CP-NIAC 02-02 PUBLIC RELEASE IS AUTHORIZED The League of Extraordinary Machines: NIAC CP-NIAC 02-02 Phase I Final Report A Rapid and Scalable Approach to Planetary Defense Against Asteroid Impactors Table of Contents List of Acronyms ________________________________________________________________________________________ iv Foreword and Acknowledgements___________________________________________________________________________ v Executive Summary______________________________________________________________________________________ vi 1.0 Introduction _________________________________________________________________________________________ 1 2.0 Background _________________________________________________________________________________________
    [Show full text]