FlexRay Communications System Electrical Physical Layer Conformance Test Specification Version 2.1 Revision B
FlexRay Physical Layer Conformance Test Specification Disclaimer
Disclaimer
This Specification as released by the FlexRay Consortium is intended for the purpose of information only. The FlexRay Consortium will not be liable for any use of this Specification for other purposes. The material contained in this Specification document is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material in this specification may require a license to such Intellectual Property Rights. A license can be obtained by becoming a member of the FlexRay consortium. Licenses for commercial exploitation will be made available to non- members by way of a separate written License Agreement following the completion of the development of the FlexRay Communications System Specifications. Such licenses shall be contingent upon Licensees granting reciprocal licenses to all Core Partners and non-assertions in favor of all Premium Associate Members and Associate Members.
This Specification document may be reproduced in electronic or paper form or utilized for informational purposes only. Reproduction or utilization for any other purposes as well as any modification of the Specification document, in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the FlexRay Consortium is explicitly forbidden.
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Copyright © 2006 - 2008 FlexRay Consortium. All rights reserved.
The Core Partners of the FlexRay Consortium are Daimler AG, BMW AG, Adam Opel GmbH, Freescale Semiconductor, Inc., NXP B.V., Robert Bosch GmbH and Volkswagen AG.
Version 2.1 Revision B June 2008 Page 2 of 553 FlexRay Physical Layer Conformance Test Specification Table of Contents Table of Contents
1 Introduction ...... 11 1.1 Scope...... 11 1.2 References...... 11 1.3 Terms and definitions...... 11 1.4 Acronyms and abbreviations...... 12 1.5 Notational conventions...... 13 2 Test Environment...... 14 2.1 Test case architecture...... 14 2.2 Test method...... 14 2.2.1 Upper tester...... 15 2.2.2 Lower tester...... 17 2.2.3 Supervisor...... 17 2.3 Test environment ...... 17 2.4 Test topology ...... 18 2.4.1 Cable overview of the test topology ...... 22 2.4.2 Shield...... 24 2.4.3 ESD protection...... 25 2.4.4 Termination...... 26 2.4.5 Common mode chokes...... 28 2.4.6 Active star...... 29 2.4.7 Passive star ...... 30 2.4.8 Passive bus ...... 32 2.4.9 Cables...... 33 2.4.10 Connectors ...... 34 2.5 Test equipment ...... 34 2.5.1 General...... 34
2.5.2 Power supply V BAT ...... 35
2.5.3 Power supply V CC ...... 36
2.5.4 Power supply V IO ...... 36
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2.5.5 Ground shift generator...... 37 2.5.6 Low battery generator...... 38 2.5.7 Signal generator ...... 38 2.5.8 Analog signal measurement ...... 39 2.5.9 Digital signal measurement...... 39 2.5.10 Data acquisition unit ...... 40 2.5.11 Broadband amplifier...... 40 2.5.12 Arbitrary function generator ...... 41 3 Stress Conditions...... 42 3.1 Ground shift ...... 42 3.2 Low battery voltage inside operational range...... 43 3.3 Undervoltage...... 44 3.4 Dynamic low battery voltage ...... 45 3.5 Failures ...... 46 3.6 Babbling idiot ...... 51 3.7 Dynamic ground shift ...... 52 3.8 EMC...... 53 3.9 ESD ...... 53 3.10 Temperature tests...... 53 4 Parameter List...... 54 4.1 Static test cases...... 55 4.2 Communication...... 55 4.2.1 Delay...... 55 4.2.2 Signal shape...... 56 4.2.3 Threshold...... 57 4.2.4 Timing...... 58 4.2.5 Truncation...... 59 4.3 Mode...... 60 4.3.1 Active star...... 62 4.3.2 Bus driver...... 62
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4.4 Power supply ...... 63 4.5 Environment...... 64 4.6 Dynamic low battery voltage ...... 64 4.7 Ground shift ...... 64 4.8 Failure...... 64 4.8.1 Babbling idiot ...... 65 4.8.2 Loss ...... 65 4.8.3 Short circuit...... 66 4.8.4 Termination...... 66 4.9 Functional class ...... 67 5 Test Cases for Bus Drivers ...... 68 5.1 Configuration...... 68 5.1.1 Topology...... 68 5.1.2 Test planes ...... 68 5.1.3 Test Patterns ...... 72 5.1.4 Observation windows...... 76 5.1.5 Operation modes of the bus driver...... 79 5.1.6 Power supplies ...... 79 5.1.7 Stress...... 80 5.1.8 Failures...... 80 5.1.9 Optional features ...... 80 5.1.10 Definition of communication and control ...... 81 5.1.11 Standard preamble ...... 89 5.1.12 Standby preamble...... 89 5.1.13 Sleep preamble...... 90 5.1.14 ReceiveOnly preamble...... 91 5.1.15 Standard postamble...... 91 5.1.16 Receiver masks ...... 91 5.1.17 Services...... 92 5.2 Static test cases...... 99
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5.3 Test Cases...... 104 5.3.1 Communication.Delay. dBDTx01 ...... 104 5.3.2 Communication.Delay. dBDTx10 ...... 106 5.3.3 Communication.Delay. dTxAsym ...... 108 5.3.4 Communication.Delay. dBDRx01 ...... 110 5.3.5 Communication.Delay. dBDRx10 ...... 112 5.3.6 Communication.Delay. dRxAsym ...... 114 5.3.7 Mode.Bus Driver.Low Power.Standby ...... 116 5.3.8 Mode.Bus Driver.Normal...... 162 5.3.9 Mode.Bus Driver.Low Power.Sleep ...... 169 5.3.10 Mode.Bus Driver.ReceiveOnly...... 196 5.3.11 Failure.Loss ...... 247 5.3.12 Failure.Short Circuits ...... 273
5.3.13 Power Supply.Undervoltage V BAT ...... 275
5.3.14 Power Supply.Undervoltage V CC ...... 283
5.3.15 Power Supply.Undervoltage V IO ...... 291 5.3.16 Dynamic Low Battery Voltage...... 293 5.3.17 Communication.Timing.Masks...... 303 5.3.18 Communication.Truncation...... 305 5.3.19 Failure.Short Circuit Bus Wires...... 307 5.3.20 Communication.Shortened Bit Times...... 321 5.3.21 Dynamic Ground Shift...... 325 5.3.22 Eye Diagram ...... 329 5.4 Test procedures...... 331 5.4.1 Signal shape, timing, delay...... 331 5.4.2 Truncation, masks ...... 332 5.4.3 Mode...... 333 5.4.4 Failure...... 334 5.4.5 Undervoltage ...... 335 5.4.6 Dynamic low battery...... 336
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6 Test Cases for Active Stars ...... 337 6.1 Configuration...... 337 6.1.1 Topology...... 337 6.1.2 Test planes ...... 337 6.1.3 Test patterns...... 341 6.1.4 Observation windows...... 342 6.1.5 Operation modes of the AS...... 345 6.1.6 Power supplies ...... 346 6.1.7 Stress...... 346 6.1.8 Failures...... 346 6.1.9 Optional features ...... 346 6.1.10 Definition of communication...... 347 6.1.11 Standard preamble ...... 349 6.1.12 Sleep preamble...... 350 6.1.13 Standard postamble...... 350 6.1.14 Services...... 350 6.2 Static test cases...... 351 6.3 Test cases...... 355 6.3.1 Communication.Delay. dStarDelay ...... 355
6.3.2 Communication.Delay. dStarDelay 0...... 357 6.3.3 Communication.Delay.dStarAsym ...... 359 6.3.4 Communication.Delay. dStarSetUpDelay ...... 361
6.3.5 Communication.Truncation. dFrameTSSTruncation M,N ...... 363 6.3.6 Communication.Truncation. dStarTruncation ...... 365 6.3.7 Mode.Active Star.Normal...... 367 6.3.8 Mode.Active Star.Normal.GoToSleep...... 375 6.3.9 Mode.Active Star.Normal.GoToSleep_Fail ...... 378 6.3.10 Mode.Active Star.Low Power.Sleep...... 380 6.3.11 Mode.Active Star.Low Power.Sleep.Wake-up ...... 386 6.3.12 Mode.Active Star.Branch.Active ...... 394
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6.3.13 Mode.Active Star.Branch.Idle ...... 396 6.3.14 Mode.Active Star.Branch.FailSilent ...... 400 6.3.15 Failure.Loss ...... 402 6.3.16 Dynamic Low Battery Voltage...... 424 6.3.17 Failure.Short Circuit Bus Wires...... 428 6.3.18 Dynamic Ground Shift...... 439 6.3.19 Eye Diagram ...... 445 6.4 Test procedures...... 447 6.4.1 Delay...... 447 6.4.2 Truncation...... 448 6.4.3 Mode...... 449 6.4.4 Failure...... 450 6.4.5 Dynamic low battery...... 451 7 Test Cases for Active Stars with CC Interface ...... 452 7.1 Configuration...... 452 7.1.1 Topology...... 452 7.1.2 Test planes ...... 452 7.1.3 Test patterns...... 454 7.1.4 Observation windows...... 454 7.1.5 Operation modes of the AS...... 454 7.1.6 Power supplies ...... 454 7.1.7 Stress...... 454 7.1.8 Failures...... 454 7.1.9 Optional features ...... 454 7.1.10 Definition of communication...... 455 7.1.11 Standard preamble ...... 458 7.1.12 Sleep preamble...... 459 7.1.13 Services...... 459 7.2 Static test cases...... 459 7.3 Test cases...... 462
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7.3.1 Communication.Delay. dStarTx01 ...... 462 7.3.2 Communication.Delay. dStarTx10 ...... 464 7.3.3 Communication.Delay. dTxAsym ...... 466 7.3.4 Communication.Delay. dStarRx01 ...... 468 7.3.5 Communication.Delay. dStarRx10 ...... 470 7.3.6 Communication.Delay. dRxAsym ...... 472 7.3.7 Mode.Active Star.Normal...... 474 7.3.8 Mode.Active Star.Normal.GoToSleep...... 483 7.3.9 Mode.Active Star.Normal.GoToSleep_Fail ...... 485 7.3.10 Mode.Active Star.Low Power.Sleep...... 488 7.3.11 Mode.Active Star.Low Power.Sleep.Wake-up ...... 495 7.3.12 Mode.Active Star.Branch.Idle ...... 499 7.3.13 Mode.Active Star.Branch.Active ...... 503 7.3.14 Mode.Active Star.Branch.FailSilent ...... 505 7.3.15 Failure.Loss ...... 507 7.3.16 Failure.Short Circuits ...... 515 7.3.17 Dynamic Low Battery Voltage...... 517 7.3.18 Communication.Truncation...... 520 7.3.19 Dynamic Ground Shift...... 522 7.3.20 Communication.Shortened Bit Times...... 530 7.4 Test procedures...... 533 7.4.1 Signal shape, timing, delay...... 533 7.4.2 Failure...... 534 7.4.3 Dynamic low battery...... 535 7.4.4 Mode...... 536 7.4.5 Truncation...... 537 8 Appendix...... 538 8.1 FlexRay parameters...... 538 8.2 References to the EPL specification ...... 543 8.3 Index ...... 544
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8.4 List of tables...... 545 8.5 List of figures...... 546 8.6 Footnotes...... 551
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1 Introduction
1.1 Scope This specification describes the conformance test for the electrical physical layer for FlexRay communication systems. It is part of this document to define a test that considers the ISO9646 standard and the FlexRay Communications System Electrical Physical Layer Specification V2.1 Rev B. The purpose of this document is to provide a standardized way to verify whether FlexRay bus driver and active star products are compliant to the FlexRay electrical physical layer specification. The primary motivation is to ensure a level of interoperability of FlexRay bus drivers and active stars from different sources in a system environment. This document shall provide all necessary technical information to ensure that test results will be identical even on different test systems, provided that the particular test suite and the test system are compliant to the content of this document.
1.2 References [01-PL Spec] FlexRay Communications System Electrical Physical Layer Specification V2.1 Rev B, November 2006 [02-BG Spec] FlexRay Communications System Bus Guardian Specification V2.0, 30-June-2004 [03-ISO1] ISO 9646 Part 1, General Concepts [04-ISO2] ISO 9646 Part 2, Abstract Test Suite Specification [05-ISO4] ISO 9646 Part 4, Test Realization [06-DIN1] ISO 7637 (comparable to DIN 40839) [07-EMC Spec] FlexRay Physical Layer EMC Measurment Specification V2.1, December 1005 [08-Prot Spec] FlexRay Communications System Protocol Specification V2.1 Rev A, December 2005 [09-EPLAN] FlexRay Communications System Electrical Physical Layer Application Notes V2.1 Rev B, November 2006 Hint: All footnotes in this document can be found in the appendix in chapter 8.6.
1.3 Terms and definitions See [08-Prot Spec].
Version 2.1 Revision B June 2008 Page 11 of 553 FlexRay Physical Layer Conformance Test Specification Introduction 1.4 Acronyms and abbreviations AS ...... Active Star AS_BGI ...... Active Star – Bus Guardian Interface AS_IVR ...... Active Star – Internal Voltage Regulator AS_VRC...... Active Star – Voltage Regulator Control ASP...... Abstract Service Primitive BD ...... Bus Driver BD_VRC...... Bus Driver – Voltage Regulator Control BD_BGCI ...... Bus Driver – Bus Guardian Control Interface BD_IVR ...... Bus Driver – Internal Voltage Regulator BD_LLA...... Bus Driver – Logic Level Adaptation BG...... Bus Guardian BGE...... Bus Guardian Enable BGT...... Bus Guardian Tick BM...... Bus Minus BP ...... Bus Plus CC...... Communication Controller CE ...... Communication Element CHI...... Controller Host Interface CMC...... Common Mode Choke EN ...... Optional/product specific Mode Control Signals of the Bus Driver DUT...... Device Under Test ECU...... Electronic Control Unit EMC ...... Electromagnetic Compatibility I/R...... Interruption INH1...... Inhibit 1 output signal of the bus driver / active star INTN...... Interrupt Not IUT ...... Implementation Under Test LT...... Lower Tester LWU ...... Local Wake-up
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PCO ...... Point of Control and Observation PDU...... Protocol Data Unit PL...... Physical Layer RWU...... Remote Wake-up RxD ...... Receive data signal from the bus driver RxEN...... Receive data enable Not signal from the bus driver S/C ...... Short circuit SCSN ...... SPI chip select Not input SOVS ...... System Operation Variable Space, see chapter 4 SPI ...... Serial Peripheral Interface STBN...... Standby Not signal SUT...... System under Test SV ...... Supervisor TCP...... Test Coordination Procedure TP...... Test Plane TSS ...... Transmission Start Sequence TxD...... Transmit data signal to the bus driver TxEN ...... Transmit data enable Not signal to the bus driver
UGS ...... Ground Shift Voltage UT ...... Upper Tester
VBAT ...... A supply voltage (Battery)
VCC ...... A supply voltage (+5V)
VECU ...... The supply (battery) voltage of the ECU
VIO ...... Supply voltage for the digital I/O ports WAKE...... Local wake-up input signal of the bus driver WU...... Wake-up
1.5 Notational conventions Notational conventions are listed in [01-PL Spec].
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2 Test Environment
2.1 Test case architecture Each test case is specified with the following parts, that must all described unambiguous: • Test Case Name a name for this test case. • Test Purpose a description of the motivation for this test case. • Configuration the state of the test environment for this test case. • Preamble (setup state) the steps to do before the specified test case could be executed. • Test execution the description of the execution of this test case. • Postamble the steps to do after the specified test case in order to have a defined state. • Pass- / Fail Criteria the criteria to judge the test result. Every test case is independent from the other test cases. Each test case is stressed by some specified stress conditions in order to check the robustness of the IUT. These stress conditions are specified in detail in chapter 3 on page 42 et seqq. The test parameters are FlexRay variables or constants that are defined in [01-PL Spec]. These test parameters are specified in detail in chapter 4 on page 54 et seqq. Every test case starts at the beginning of the preamble and ends after the postamble. There is no delay between the preamble and the test execution and between the test execution and the postamble. The pass/fail criteria is related only on the test execution. Product specific items are not part of this conformance test specification.
2.2 Test method The FlexRay BD has several interfaces, that are supplied by specified power supplies and stimuli and observed by external components (signal measurements). The requirements for those generators and signal measurements are specified in chapter 2.5 on page 34 et seqq. The interfaces of the BD are separated in two parts:
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• Analog interface bus (service provider) and supply pins. • Digital interface the pins for connecting the BD with the FlexRay protocol components. Each test case describes the used pins for supplying, stimulation and observation. The used test method for the FlexRay PL regarding the [03-ISO1] is the local test method, see also Figure 2-1. The local test method contains a lower tester (LT) for the analog interface (bus) and an upper tester (UT) for the digital interface. Both are part of the test system. The coordination of the test cases is done by the test coordination procedure (TCP). The whole test is controlled by the supervisor (SV) that is also part of the test system. The SV controls the UT and LT with the TCP.
Test System PCO Upper Tester ASPs
TCP SV
S Lower Tester PDUs U IUT T PCO ASPs
Service Provider
Figure 2-1: Local Test Method
2.2.1 Upper tester
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The UT has to provide test data, control and observe the IUT at its upper interface. The implementation has to keep in mind the possibility of two different host interfaces of the IUT as specified in [01-PL Spec]. Figure 2-2 shows the mandatory signals of the IUT that the conformance test considers:
Upper Tester Upper Tester TxDTxEN RxD RxEN BGE INH1 ERRNSTBN TxDTxEN RxD RxEN BGE INH1 INTN SPI
IUT (option A) IUT (option B)
Figure 2-2: Upper Tester The tasks of the UT are: • Provide test data streams • Change the mode of the IUT • Observe and acquire the error line • Observe and acquire the received data stream • Provide IUT functions to the supervisor • Provide test system functionality to the IUT
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2.2.2 Lower tester The LT has to provide data and observe the IUT at its lower interface – the supply and bus interface of the IUT. Figure 2-3 shows an overview of this tester.
IUT Supply GND BP BM
Lower Tester
Figure 2-3: Lower Tester The tasks of the LT are: • Generate and control bus failures • Generate ground shift • Control the supply voltages • Provide IUT functions to the supervisor • Provide test system functionality to the IUT 2.2.3 Supervisor The SV has to control and observe the whole test system and communicates with the IUT via the LT and UT. The tasks of the SV are: • Control the LT and UT • Observe and acquire the LT and UT • Control and observe optional measurement devices • Execute and coordinate test procedures • Create the test report 2.3 Test environment The following parameters are constants within the conformance test and used in the standard environment : • Temperature: ambient • Moisture: ambient • Test topology: as described in chapter 2.4 on page 18
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• Termination: as described in the test topology; differences are specified in the used test case • Amount of nodes: as described in the test topology • Amount of Stars: as described in the test topology • Baud rate: 10 Mbit/s (gdBit = 100ns) as part of the harmonized baud rates in the FlexRay consortium • Common mode choke as specified in chapter 2.4.5. 2.4 Test topology The purpose is to test the expected worst case of a possible topology with the maximum number of cascaded active stars, one passive star and one passive bus. It is sufficient to test only with one physical channel, because the behaviour of the physical layer is independent from the number of used channels in a communication network. The used test topology is described in the following sections and shown in Figure 2-4.
Item Description
Ground
Local ground of node 24
Splice for power supply wires 3m
1.5m Bus wire
Bus termination
Cable shield connection
VBat 2m Length of the power supply wire GND 0.5m and
VCC 4m the ground connection GND 0.5m Node 1
11 Active star 2 AS 4 3
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Item Description
PS Passive star
1.5m 0.15m 10m Passive bus with stubs
0 .3 m 0.3m 0.3m 0.3m
Bus splice as part of the passive bus 3
VBAT power supply
VBAT
VCC power supply
VCC
VIO power supply
VIO
Chassis of test system
Table 2-1: Test Topology Description
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1.5m 1.5m 1.5m m .3 0 1
3m 3m 3m
8m 0.3m 4 GND splices 12 Bat V GND 0.5m passivebus 10m
9m 2 0.3m 13 Bat V GND 0.5m spliceNode 24for spliceNode 24for splice Nodefor 24 IO CC BAT V V V 0.15m
3
10m 0.3m 14 Bat GND 0.5m V .5m 1 active staractive 4
2m 6m 1m 3.5m 1 1 3 splice 1 2 Bat Bat AS IO V GND 0.5m V GND 5m 2 4m 4m 2m BAT CC GS 4m V V GND 0.5m V 21 Bat V GND 0.5m andsplice to V see below text 11m channel number cable shield termination CC
m GS 5 .2
0 3m 22 m Bat V .25 GND 0.5m
GND 0.3m 0 splice, to V
Bat PS
m 1 5m 2m length of supplylength of from lines: nodes and star V to to GND splice,to V passive star splice for Nodes, except Node 24
splicefor AS
23 splice AS for Bat GS m V GND 0.5m V
BAT
CC BAT 5
V 2
V V . 0 3m 3m 3m 4m 4m 4m 2m CC BAT BAT 24 Bat CC IO GS V V V V V V GND 0.5m V Battery Battery 1.5m 1.5m 1.5m length of communication lines
Figure 2-4: Conformance Test Topology
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Description of the test topology: • A detailed description of the AS hardware may be given in chapter 2.4.6. • A detailed description of the passive star hardware is given in chapter 2.4.7. • A detailed description of the passive bus hardware is given in chapter 2.4.8. • Nodes without ground shift stress must be connected with their negative terminal to one of the ground splices that are mounted on the stainless steel chassis. • The four ground splices shall be mounted near the nodes and the AS to consider the length of the GND cables of the nodes and the AS. The following nodes are connected to one of the GND splices: GND splice 1: Nodes 11, 12, 13 and 14 GND splice 2: Nodes 21, 22, 23 and 24 GND splice 3: Nodes 1, 2 and the AS GND splice 4: negative terminal of all supplies • Nodes, that are stressed with ground shift, are connected to a switch 1, that guarantees, that these nodes could be connected directly to ground or are stressed by ground shift. This switch shall be controllable by the SV. The attenuation of the used switches shall be as small as possible. • The ground shift terminal of the nodes and the AS are connected to the positive terminal of the ground shift generator. The length of this cable is 1m. • The negative terminal of the ground shift generator is connected to the GND splice of the test system (chassis). The length of this cable is 1m. • All nodes must be connected to the battery splice (+) that is mounted on the chassis.
• The AS must be connected to the V BAT splice (+) for the AS that is mounted on the chassis.
• The AS must be connected to the V CC splice (+) for the AS that is mounted on the chassis.
• Node 24 must be connected to the V BAT splice (+) for the node that is mounted on the chassis.
• Node 24 must be connected to the V CC splice (+) for the node that is mounted on the chassis.
• Node 24 must be connected to the V IO splice (+) for the node that is mounted on the chassis. • The chassis must be a steel plate for the ground connections of the IUTs and the power supply. • The chassis is connected to the negative terminal of the power supply (clamp 31). • The battery splice is connected to the positive terminal of the power supply (clamp 30).
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• The V BAT splice for the nodes is connected to the positive terminal of the nodes V BAT power supply.
• The V BAT splice for the AS is connected to the positive terminal of the AS VBAT power supply.
• The V CC splice for the AS is connected to the positive terminal of the first +5V power supply.
• The V BAT splice for the node 24 is connected to the positive terminal of the VBAT power supply for node 24.
• The V CC splice for the node 24 is connected to the positive terminal of the second +5V power supply.
• The V IO splice for the node 24 is connected to the positive terminal of the VIO power supply. • All communication channels must be terminated regarding the [01-PL Spec]. • The shield of every link must be terminated regarding the [01-PL Spec]. • The bus cables must meet the requirements of the [01-PL Spec]; see also chapter 2.4.9.1 on page 33. All bus cables are shielded. The shield is only connected at the AS (see also chapter 2.4.2). • The supply cables must meet the requirements specified in chapter 2.4.9.2 on page 34. The following topics are part of the implementation of the conformance test, but have to meet the [01-PL Spec]: • the type of mounting of the IUTs on the chassis • the type and manufacturer of the cables • the type and manufacturer of the connectors • the type of the battery splice • the wiring of the IUT 2.4.1 Cable overview of the test topology
No. Type From To Length Termination Remarks [m]
1. Bus wire Node 1 Active star 1 Both ends
2. Ground wire Node 1 GND splice 3 0.5 -
3. Supply wire Node 1 Battery splice 2 -
4. Bus wire Node 2 Active star 3.5 Both ends
5. Ground wire Node 2 GND splice 3 5 -
6. Supply wire Node 2 Battery splice 6 -
7. Bus wire Node 11 Bus splice 1 0.3 No termination Part of the passive bus
8. Ground wire Node 11 GND splice 1 0.5 -
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No. Type From To Length Termination Remarks [m]
9. Supply wire Node 11 Battery splice 6 -
10. Bus wire Node 12 Bus splice 1 0.3 Only at node 12 Part of the passive bus
11. Ground wire Node 12 GND splice 1 0.5 -
12. Supply wire Node 12 Battery splice 8 -
13. Bus wire Node 13 Bus splice 2 0.3 No termination Part of the passive bus
14. Ground wire Node 13 GND splice 1 0.5 -
15. Supply wire Node 13 Battery splice 9 -
16. Bus wire Node 14 Bus splice 3 0.3 No termination Part of the passive bus
17. Ground wire Node 14 GND splice 1 0.5 -
18. Supply wire Node 14 Battery splice 10 -
19. Bus wire Node 21 Passive star 0.25 No termination Connected to the passive star 20. Ground wire Node 21 GND splice 2 0.5 -
21. Supply wire Node 21 Battery splice 4 -
22. Bus wire Node 22 Passive star 0.25 No termination Connected to the passive star 23. Ground wire Node 22 GND splice 2 0.5 -
24. Supply wire Node 22 Battery splice 3 -
25. Bus wire Node 23 Passive star 1 Only at node 23 Connected to the passive star 26. Ground wire Node 23 GND splice 2 0.5 -
27. Supply wire Node 23 Battery splice 5 -
2 28. Ground shift wire VGS supply Node 23 1 - Connected to positive terminal 3 29. Ground shift wire VGS supply GND splice 4 1 - Connected to negative terminal 30. Bus wire Node 24 Passive star 0.25 No termination Connected to the passive star 31. Ground wire Node 24 GND splice 2 0.5 -
32. Supply wire Node 24 Battery splice 4 -
2 33. Ground shift wire VGS supply Node 24 1 - Connected to positive terminal 3 34. Ground shift wire VGS supply GND splice 4 1 - Connected to negative terminal 35. Ground wire Active star GND splice 2 0.5 -
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No. Type From To Length Termination Remarks [m]
36. Supply wire Active star VBAT splice 4 -
37. Supply wire Active star VCC splice 4 -
38. Bus wire Active star Passive star 11 Only at active star
39. Bus Wire Active star Bus splice 3 1.5 Only at active star
2 40. Ground shift wire VGS supply Active star 1 - Connected to positive terminal 2 41. Ground shift wire VGS supply GND splice 4 1 - Connected to negative terminal 42. Bus wire Bus splice 1 Bus splice 2 10 No termination Part of the passive bus
43. Bus wire Bus splice 2 Bus splice 3 0.15 No termination Part of the passive bus
44. Supply wire Battery Battery splice 3 - VBAT supply for nodes
45. Ground wire Battery GND splice 4 1.5 - VBAT supply for nodes
46. Supply wire Battery Battery splice 3 - VBAT supply for AS
47. Ground wire Battery GND splice 4 1.5 - VBAT supply for AS
48. Supply wire VCC Supply VCC splice 3 - VCC supply for AS
49. Ground wire VCC Supply GND splice 4 1.5 - VCC supply for AS
50. Supply wire Battery Battery splice 3 - VBAT supply for node 24
51. Ground wire Battery GND splice 4 1.5 - VBAT supply for node 24
52. Supply wire VCC Supply VCC splice 3 - VCC supply for node 24
53. Ground wire VCC Supply GND splice 4 1.5 - VCC supply for node 24
54. Supply wire VIO Supply VIO splice 3 - VIO supply for node 24
55. Ground wire VIO Supply GND splice 4 1.5 - VIO supply for node 24
56. Ground wire Passive star GND splice 2 0.3 - Ground connection of PS
Table 2-2: Cable Overview of Test Topology
2.4.2 Shield Each communication link must have one cable shield connection. The conformance test uses one active star, that is the central point of shield connection in the topology. Table 2-3 and Figure 2-5 show the specified shield connection with bus cable, connectors, active star and node:
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Name Description Typ Unit
Rs Damping resistance 1000 Ω
Tolerance 1 %
Cs Capacitance 470 nF
Tolerance 10 %
L2, R 2, R 3 and C 1 Components of the passive star, see chapter 2.4.7.
Table 2-3: Shield Connection Components
Node Active Star Passive Star Node
Bus Cable Bus Cable Bus Cable
Cs Cs L2 L2 Rs Rs R2 R2 Cable Shield Cable Shield C1 Cable Shield R3
Figure 2-5: Cable Shield Connection
The cable shield of each branch at the PS is connected via L 2 and R 2 to C 1 and R 3 to the local ground of the PS, see chapter 2.4.7. The shield must be interrupted between the housings of the active star, N23 and N24 due to ground shift condition at those nodes. The shield must not be interrupted between the housings of N1, N2, N11-14, N21 and N22, because those nodes have no ground shift condition.
2.4.3 ESD protection To emulate the load of ESD protection circuits every BD has a specified load at the bus terminals:
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ECU
CBP BP
RT1 FlexRay Bus
BD R1 CDiff
C1 RT2
BM
CBM
Figure 2-6: ESD Load Circuit
Name Description Typ Unit
CBP Capacitance of BP to GND 47 pF
Tolerance; NP0 dielectric 5 %
CBM Capacitance of BM to GND 47 pF
Tolerance; NP0 dielectric 5 %
CDiff ECU’s differential input capacitance 39 pF
Tolerance; NP0 dielectric 5 %
Table 2-4: ESD Load Circuit As described in Figure 2-6 the ESD load circuit is placed on the board between the termination and the bus terminals. If no termination exist the ESD load circuit is placed between the CMC and the bus terminals.
2.4.4 Termination Each terminated node and star as described in the test topology must have the following split termination:
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BP C1 RT1 R1 IUT 3.5m R T2 2 BM
Figure 2-7: Terminated Node
The RDCLoad is specified in [01-PL Spec] in chapter 4.7 on page 24. See also figure 4- 5 in [01-PL Spec].
For the nominal (default) RDCLoad the termination resistor (as specified in figure 4-1
on page 22 and 4-5 on page 24 in [01-PL Spec]) is defined as e.g. R T= R T1 +R T2 .
Values of discrete components:
Name Description Typ Unit
RT1 Resistor of split termination Z 0 Ω 4 2
Tolerance 1 %
RT2 Resistor of split termination Z 0 Ω 4 2
Tolerance 1 %
R1 Resistor 5 Ω
Tolerance 1 %
C1 Ceramic capacitor 4.7 nF
Tolerance 10 %
Table 2-5: Split Termination Components
The value of Z0 depends on the used bus cable. This cable is defined in chapter 2.4.9.1. Some nodes in the test topology have no termination. Figure 2-8 shows the bus connection of an unterminated node.
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BP
IUT 0.2m
BM 14
Figure 2-8: Unterminated Node
2.4.5 Common mode chokes Common mode chokes shall be used within the conformance testing of bus drivers as follows:
ECU
BP
RT1 CMC FlexRay Bus
BD R1
C1 RT2
BM
Figure 2-9: Common Mode Choke Implementation As described in Figure 2-9 the CMC is placed on the board between the IUT and the termination. If no termination exist the CMC is placed between the IUT and the ESD protection circuit. The manufacturer of the CMC is: Epcos The type of the CMC is: B82789C0104N002 (bifilar winding)
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2.4.7 Passive star The passive star shall be implemented as follows:
Bus BP BM Shield Plug 1 L1 BP R1
L1 BM R1
L2 C1 R3 Shield R2
GND Splice Bus Plug n L1 BP R1
L1 BM R1
L2 Shield R2
Figure 2-10: Passive Star Implementation
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Name Description Typ Unit
R1 Series resistance on signal wire 22 Ω
Tolerance 1 %
L1 Series inductance on signal wire 220 nH
Tolerance 10 %
R2 Series resistance on signal wire 100 Ω
Tolerance 1 %
L2 Series inductance on signal wire 220 nH
Tolerance 10 %
R3 Inductance of shield to system ground 1 MΩ
Tolerance 1 %
C1 Capacitance to system ground 100 nF
Tolerance 10 %
Table 2-6: Passive Star Implementation The ground of the passive star is connected to GND splice 2 with a ground wire of 0.1m length.
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2.4.8 Passive bus The passive bus shall be implemented as follows:
Splice BP Cable Cable BM Bus Bus Shield
Zoom Node x
BP
BM
Shield Bus Bus
Node x Node
Figure 2-11: Passive Bus Implementation The plugs shall be realized with 9 pin Sub-D connectors mounted on a small board. The wires between the connectors shall be as short as possible.
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2.4.9 Cables
2.4.9.1 Bus Cables The used bus cables in the conformance test must have a shield and require the following conditions:
Name Description Typ Tolerance Unit
Z0 Differential mode 90 ± 2% Ω impedance @ 10 MHz
Table 2-7: Bus Cable Impedance
Name Description Min Max Unit
T’ 0 Specific line delay 10 ns/m
α5MHz Cable attenuation @ 5 MHz 82 dB/km
lBus Maximum electrical distance 24 m between two nodes 5 or active stars, see also [01-PL Spec]
lStubDistance M,N Distance between two 150 mm network splices
Table 2-8: Bus Cable Characteristics See further recommendations about bus cables in the application notes of [01-PL Spec]. An example for a bus cable is: Cable manufacturer: Gebauer & Griller Cable type: xF8FF_2_B56_FlM02YHBY
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2.4.9.2 Power supply cables The used cables in the conformance test must require the following conditions:
Name Description Min Max Unit
2 ACross section Cross section of GND and 1.5 mm power supply wires
Table 2-9: Supply Cable Characteristics An example for a supply cable is: Supply cable manufacturer: Coroplast Supply cable type: FLRY-A 2.5
2.4.10 Connectors The used connectors in the conformance test must require the following conditions:
Name Description Min Max Unit
RDCContact Contact resistance 50 mΩ (including crimps)
ZConnector Impedance of connector 70 200 Ω
6 lCoupling Length coupling connection 150 mm
dContactInterruption Contact interruption; 100 ns 7 RDCContact > 1 Ω
Table 2-10: Connectors Characteristics See further recommendations about connectors in the application notes of [01-PL Spec]. An example for a connector is: Connector manufacturer: Erni Connector type: Sub-D 9 pin
2.5 Test equipment
2.5.1 General Hint : In every test case the accuracy/resolution of each generator and measurement device must be taken into account.
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Hint : INH1 is floating while the IUT is in sleep mode and at VBAT level while the IUT is not in a sleep mode. A pull down resistor shall be used to force a floating INH1 output to ground. The logical level of the optional signal INH1 must be interpreted as:
• Logical High: uINH1 > uV BAT – 2V while uV BAT > 5.5V
• Logical Low: uINH1 < uV BAT – 2V while uV BAT > 5.5V
2.5.2 Power supply V BAT The power supply must be connected with the negative terminal to the chassis of the test system (that is connected to the ground pin) and with the positive terminal to the
VBAT splice of the communication network. This supply simulates a battery in an automotive environment.
The default voltage of V BAT is the maximal battery operational range defined in the data sheet of the IUT up to +42V. Alternatively, for some test cases, the IUT is powered by a low battery generator as defined in 2.5.6 instead.
Output Description Min Max Unit
VBAT Supply voltage DC +50 V
Ripple (rms) AC 10 mV
Imin 5 A
Precision/Accuracy 1 %
Table 2-11: VBAT Power Supply Characteristics An example for this supply is: Supply manufacturer: Toellner Supply type: 8825-64
Used voltages of V BAT : +14V…+42V, +7.0, +5.5V, VBATUndervoltage .
Hint: All nodes must support to be supplied independently by extra V BAT power supplies.
Hint: Nodes 24 must support to be supplied independently by extra VCC and VIO power supplies.
Hint: The active star must support to be supplied independently by extra V BAT , V CC
and V IO power supplies.
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2.5.3 Power supply V CC The power supply must be connected with the negative terminal to the chassis of the test system (that is connected to the ground pin) and with the positive terminal to the
VCC splice of the communication network. This supply simulates the voltage regulator inside an active star or a node in an automotive environment.
The default voltage of V CC is +5.0V.
Output Description Min Max Unit
VCC Supply voltage DC +5.05 V
Ripple (rms) AC 10 mV
Imin 0.7 A
Precision/Accuracy 1 %
Table 2-12: VCC Power Supply Characteristics An example for this supply is: Supply manufacturer: Toellner Supply type: 8842-32
Hint: The V CC on the nodes shall be generated by local voltage regulators and are not independent from V ECU .
Used voltages of V CC : +5.0 (normal), VCCUndervoltage .
Node 23, Node 24 and the AS must be supplied independently by an extra V CC power supply.
2.5.4 Power supply V IO The power supply must be connected with the negative terminal to the chassis of the test system (that is connected to the ground pin) and with the positive terminal to the
VIO splice of the communication network. This supply simulates the voltage regulator inside a node in an automotive environment.
The default voltage of V IO depends on the I/O voltage of the devices counterpart, i.e. the host.
Output Description Min Max Unit
VIO Supply voltage DC +5.05 V
Ripple (rms) AC 5 mV
Imin 0.7 A
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Output Description Min Max Unit
Precision/Accuracy 1 %
Table 2-13: V IO Power Supply Characteristics An example for this supply is: Supply manufacturer: Toellner Supply type: TOE 8840
Hint: The V IO on the nodes shall be generated by local voltage regulators and are not independent from V ECU .
Standard voltage of V IO : depends on implementation.
Undervoltage of V IO : VIOUndervoltage .
Node 24 must be supplied independently by an extra V IO power supply.
The AS must be supplied independently by an extra VIO power supply. The logical high level of the digital signal is specified in chapter 11 in [01-PL Spec] on page 81.
2.5.5 Ground shift generator This generator is used to simulate ground shift between selected nodes and stars of a communication network. It is connected between the predefined ground pin of the node or star and the chassis of the test system (ground connection of the power supply).
Output Description Min Max Unit
UGS Ground shift voltage DC -5 +5 V
Ripple (rms) AC 10 mV
Imin 0.8 A
Precision/Accuracy 1 %
Table 2-14: Ground Shift Generator Characteristics An example for this supply is: Supply manufacturer: Kepco Supply type: BOP 20-10M
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Output Description Min Max Unit
VECU Low battery voltage DC +14 V
Ripple (rms) AC 5 mV
Imin 5 A
Precision/Accuracy 1 %
Table 2-15: Low Battery Generator Characteristics An example for this supply is: Supply manufacturer: Toellner Supply type: 8842-32
2.5.7 Signal generator The signal generator is connected to TxD, TxEN and BGE 8 of the bus driver and its ground pin. The generator is used to provide various test patterns, that are described in the test cases chapters below.
Output Description Min Max Unit
UTxD Bit time in test pattern 100 400 ns
Voltage level of test pattern for 0 5 V digital input
Imin 10 mA
Precision/Accuracy 1 %
Fall time of signal @ digital input of 3 ns IUT
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Output Description Min Max Unit
Rise time of signal @ digital input 3 ns of IUT
Table 2-16: Signal Generator Characteristics An example for this generator is: Generator manufacturer: Agilent Generator type: 16720A
2.5.8 Analog signal measurement The characteristics of the measurement device are described in this chapter. This may be an oscilloscope or equivalent device.
Input Description Min Max Unit
Ux Voltage level of analog test 0 14 V signals
Cx Input capacitance of probe 10 pF
Rx Input resistance 1 MΩ
Sample Rate 800 MSa/s
Bandwidth 200 MHz
Table 2-17: Analog Measurement Device Characteristics An example for this oscilloscope is: Oscilloscope manufacturer: LeCroy Oscilloscope type: Waverunner 6050
2.5.9 Digital signal measurement The characteristics of the measurement device are described in this chapter. This shall be a logic analyzer or equivalent device.
Input Description Min Max Unit
Ux Voltage level of digital test signals -5 5 V
Bandwidth 2 GHz
Cx Capacitance load 10 pF
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Input Description Min Max Unit
Rx Resistive load 0.1 MΩ
Number of channels 96 -
Timing sample rate 2 ns (full channel mode)
Table 2-18: Digital Measurement Device Characteristics An example for this logic analyzer is: Logic analyzer manufacturer: Agilent Logic analyzer type: 16911A
2.5.10 Data acquisition unit The characteristics of the measurement device are described in this chapter. This shall be a unit for measuring voltages or currents.
Input Description Min Max Unit
Ux Absolut input voltage -5 5 V
Ix Absolut input current -1 1 A
Number of channels 2 -
Timing sample rate 600 S/s (full channel mode)
Precision/Accuracy 1 %
Table 2-19: Data Acquisition Unit An example for this data acquisition unit is: Data acquisition unit manufacturer: Agilent Data acquisition unit type: 34970A
2.5.11 Broadband amplifier The characteristics of this generator are described in this chapter. This device is necessary for dynamic ground shift.
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Output Description Min Max Unit
Ux Absolut output voltage 0 10 V
Frequency range (-3dB) 0 500 kHz
Gain 13 dB
imin 1 A
Precision/Accuracy 0.5 %
Response time 1 µs
Table 2-20: Broadband Amplifier An example for this broadband amplifier is: Broadband amplifier manufacturer: Toellner Broadband amplifier type: 7608
2.5.12 Arbitrary function generator The characteristics of this generator are described in this chapter. This device is necessary for dynamic ground shift.
Output Description Min Max Unit
Ux Voltage level of digital test signals 0 2 V
Frequency range (-3dB) 0 500 kHz
Sample rate 50 MS/s
Precision/Accuracy 2 %
Table 2-21: Arbitrary Function Generator An example for this arbitrary function generator is: Arbitrary function generator manufacturer: Agilent Arbitrary function generator type: 33250A
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3 Stress Conditions
3.1 Ground shift The ground shift is located between the chassis and the predefined ground connection of the used IUTs. Every test case describes the usage of the ground shift and that IUT is/are affected.
Node IUT IUT (not stressed) (Nodes 1-23) (Node 24)
VIO BD VCC BD
VIO VCC VIO VCC VCC VIO internal + - + - + - external
+
UGS
UBAT - UGS
+ -
UBAT
Figure 3-1: Usage of Ground Shift
Signal Description Min Max Unit
UGS Static ground shift voltage -5 V
Table 3-1: Ground Shift
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Location of ground shift in the test topology:
1
Ground Shift Injection 1m
11
PS 11m 2 AS 4 1.5m 0.15m 10m
3 0 0 . . 0 2 m 2 .1 m .2 m m m 0 1 0.2m 0.2m 0.2m 3.5m
24 23 22 21 2 14 13 12 11
Ground Shift Injection
Figure 3-2: Location of Ground Shift
3.2 Low battery voltage inside operational range The test condition in case of a heavily discharged battery inside the operational range (with respect to the supply voltage boundaries specified in [01-PL Spec]) is called low battery voltage inside operational range. The behaviour of the IUT during this stress condition is very important regarding the low operation modes and the wake-up mechanism. Since the kind of diode (Schottky, etc.) inside the ECU varies from application to application VBAT is the stress voltage instead of VECU . The difference between VECU
(supply voltage at the ECU) and VBAT (the voltage at the bus driver pin), is described in Figure 3-3. Requirements: • All nodes including the IUTs and hosts of the topology (in bus driver test cases) / the active star (in active star test cases) shall be supplied by this low battery voltage.
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ECU/Star
V V BAT Diode ECU BD
+ - Battery GND GND
Figure 3-3: Description of VBAT and VECU
Signal Description Min Max Unit
VBATlow Low battery voltage for evaluation +5.5 V
of wake-up detection if V CC is not implemented and non wake-up test cases are applied.
VBATlow Low battery voltage for evaluation +7.0 V
of wake-up detection if V CC is implemented.
Table 3-2: Stress Condition Static Low Battery Voltage inside operational Range
3.3 Undervoltage The behaviour of the IUT during this stress condition is very important regarding the low operation modes and the wake-up mechanism, especially for the recovery functionality of the IUT.
• In case of presence of a V BAT pin of the IUT: V BATUndervoltage = +2.0V.
• In case of presence of a V CC pin of the IUT: V CCUndervoltage = +2.0V.
• In case of presence of a V IO pin of the IUT: V IOUndervoltage = +0.75V.
In case the implemented minimum undervoltage treshold of the IUT for V BAT , V CC of
VIO is higher than specified in [01-PL Spec] then the undervoltage value in the conformance test shall be the specified minimum undervoltage value as given in the data sheet of the IUT.
E.g. for UV_VBAT :
• The undervoltage value of V BAT is specified in [01-PL Spec] as +2.0V.
• The minimum undervoltage threshold of V BAT of the IUT in the data sheet is +4.5V.
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• The undervoltage value for VBAT in the conformance test shall be +4.5V.
E.g. for UV_VCC :
• The undervoltage value of V CC is specified in [01-PL Spec] as +2.0V.
• The minimum undervoltage threshold of V CC of the IUT in the data sheet is +4.0V.
• The undervoltage value for V CC in the conformance test shall be +4.0V.
E.g. for UV_VIO :
• The undervoltage value of V IO is specified in [01-PL Spec] as +0.75V.
• The minimum undervoltage threshold of V IO of the IUT in the data sheet is +2.0V.
• The undervoltage value for V IO in the conformance test shall be +2.0V.
3.4 Dynamic low battery voltage The IUT will also be affected by a test signal 4’ (according to ISO 7637 and DIN 40839). The test signal 4’ emulates a low battery voltage that appears when turning on the starter circuit, so the generator is connected to VECU of the IUT.
Signal Description Value Unit
US Battery voltage difference after t f at the IUT 7.6 V
UA Battery voltage difference after t 7 at the IUT 6.1 V
UB Nominal battery voltage at the IUT 11.6 V tf Fall time of battery voltage 5 ms t6 Time of U S 15 ms t7 Rise time of battery voltage 50 ms t8 Time of U A 10000 ms tr Rise time of battery voltage 100 ms
US/t f1 Fall time of U S for t f1 (simulates a small 7.6/5 V/ms capacitance in an ECU)
US/t f6 Fall time of U S for t f6 (simulates a big 6.1/300 V/ms capacitance in an ECU)
Table 3-3: Stress signal 4’
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VBAT
US/tf1 US/tf6
US UA
UB
tf t6 t7 t8 tr t
Figure 3-4: Stress signal 4’
3.5 Failures This stress parameter shall examine the behaviour of the IUT in case of failures onboard. A faulty link might be a faulty connection between the power lines or the digital signals. Requirements: • Only one link is stressed by one test parameter. • The test nodes are supplied as specified in the test case. • Check the behaviour of the IUT while stressed • Check the recovery of the IUT after removal of stress
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1 1m
11
PS 11m 2 AS 4 1.5m 0.15m 10m
3 0 0 . . 0 2 m 2 .1 m .2 m m m 0 1 0.2m 0.2m 0.2m 3.5m
24 23 22 21 2 14 13 12 11
Onboard Failures
Figure 3-5: Location of the onboard Failures
Overview of all failures:
Abbreviation Condition Description
9 FL1 I/R V BAT Interruption of supply line V BAT of the IUT
FL2 I/R V CC Interruption of supply line V CC of the IUT
FL3 I/R V BAT and V CC Interruption of supply lines V BAT and V CC of the IUT
FL4 S/C TxEN GND Short circuit between TxEN and ground
FL5 I/R TxEN Interruption of TxEN 10
FL6 I/R TxD Interruption of TxD 10
11 FL7 Minimum RDCLoad Minimum allowed bus load (40 Ω) , see [01- PL Spec]. See also Figure 2-7.
11 FL8 Maximum RDCLoad Maximum allowed bus load (55 Ω) , see [01- PL Spec]. See also Figure 2-7.
FL9 I/R STBN Interruption of STBN 10
FL10 I/R BGE Interruption of BGE 10
FL11 S/C BP GND Short circuit between BP and GND
FL12 S/C BM GND Short circuit between BM and GND
FL13 S/C BP +48V Short circuit between BP and +48V 12
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Abbreviation Condition Description
FL14 S/C BM +48V Short circuit between BM and +48V 12
FL15 I/R GND_IUT Loss of GND of the IUT
FL17 I/R V IO Interruption of supply line V IO of the IUT
FL18 I/R EN Interruption of EN 10
FL19 S/C BP -5V Short circuit between BP and -5V
FL20 S/C BM -5V Short circuit between BM and -5V
FL21 S/C BP BM Short circuit between BP and BM
FL22 VBAT =0V Set battery supply to 0V
FL23 VCC =0V Set V CC supply to 0V
FL24 VBAT =0V and Set battery supply to 0V and set V CC supply
VCC =0V to 0V
FL25 I/R BP and I/R BM BD looses connection to channel (BP and BM interrupted)
Table 3-4: Faulty Lines Test Parameter
IUT IUT
VBAT VBAT VCC VCC FL1: VIO FL2: VIO
IUT IUT
VBAT VBAT VCC VCC FL3: VIO FL17: VIO
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IUT IUT
VBAT=0V VBAT VCC VCC=0V FL22: VIO FL23: VIO
IUT
VBAT=0V VCC=0V FL24: VIO
Figure 3-6: Failure/Loss of Supplies
TxD TxD TxD TxEN TxEN TxEN IUT BGE IUT BGE IUT BGE STBN STBN STBN EN EN EN FL5: FL6:
FL4: GND
TxD TxD TxEN TxD IUT BGE TxEN TxEN STBN IUT BGE IUT BGE EN STBN STBN FL10: EN EN FL9: FL18:
Figure 3-7: Failures of digital Signals TxEN, TxD, BGE, STBN and EN
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BP BP IUT IUT
BM BM
GND GND +48V +48V FL11: -5V FL12: -5V
BP BP IUT IUT
BM BM
GND GND +48V +48V FL13: -5V FL14: -5V
BP BP IUT IUT
BM BM
GND GND +48V +48V FL19: -5V FL20: -5V
BP BP IUT IUT
BM BM
FL21: FL25:
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Figure 3-8: Failures of Bus Wires BP and BM
IUT
FL15: GND
Figure 3-9: Failures of GND Wire
1 1m
11
PS 11m 2 AS 4 1.5m 0.15m 10m
3 0 0 . . 0 2 m 2 .1 m .2 m m m 0 1 0.2m 0.2m 0.2m 3.5m
24 23 22 21 2 14 13 12 11
Faulty Termination
Figure 3-10: Location of Termination Changes inside a Node
3.6 Babbling idiot The AS must recognize a babbling idiot at a branch in order to prevent the communication of the other nodes from a faulty node. This is also described in [01- PL Spec]. Requirements: • The test signal supplies the TxD pin of the babbling idiot(s). • The TxEN is active while sending data (the IUTs are enabled to transmit data from their CCs/hosts). • An optionally BGE signal is also active (the IUTs are enabled to transmit data from their CCs/hosts). • Optionally mode control signals shall be set to normal mode of the IUTs.
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The test signal is specified in chapter 6.1.3.1.
3.7 Dynamic ground shift The IUT shall also be affected by a dynamic ground shift. The connection and usage are described in chapter 3.1.
4 Bits = 400ns 6V
3 Bits = 300ns UGS 2V 0V
10 Bits = 1 µs 25µs 1ms
Figure 3-11: Dynamic Ground Shift Curve - Input Due to internal filters and the speed of a broad band amplifier the output ( uGS_dyn ) may look like the yellow curve in the following figure (the input signal is drawn in voilet):
Figure 3-12: Dynamic Ground Shift Curve - possible Output
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3.9 ESD This conformance test specification does not support EMC stress conditions. This is part of [07-EMC Spec].
3.10 Temperature tests This conformance test specification does not support temperature tests as a stress condition. This is part of the semiconductor manufacturer and included in the data sheet of the corresponding physical layer device.
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4 Parameter List The parameter list is organized by a tree and structured by the system operation variable space (SOVS). The SOVS approach is a specific method to derive test cases by combining basic system “variables” with each other. The system operation conditions are given from experience from existing communication systems. In order to have an easier way of reproducibility the test parameters are grouped into the following variables:
Static Test Cases
Communication
Mode
Power Supply
Environment
Dynamic Low Battery Voltage
Ground Shift
Failure
Functional Class
Figure 4-1: Overview of the SOVS Parameters
All combinations of these variables represent all theoretical possible test cases. This would result in a huge number of test cases. But the number of combinations can be reduced dramatically by defining variables as “constant” (e.g. environment) or by selecting just a few representative (i.e. concerted) values for each variable. So the relevant test cases are selected in the test case chapters beginning from page 68.
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Static Test Cases
Figure 4-2: SOVS Static Tests
4.2 Communication This vector contains the test parameters that affect the data communication of the test system in normal operational mode. This item is divided in some more sub items:
Communication Delay
Signal Shape
Threshold
Timing Masks
Truncation Shortened Bit Times
Figure 4-3: SOVS Communication with Sub Items
4.2.1 Delay The sub item delay contains all relevant tests with the focus on delay in the data communication. This item is divided in some more sub items:
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Figure 4-4: SOVS Delay with FlexRay Parameters
4.2.2 Signal shape The sub item signal shape contains all relevant tests with the focus on the signal form. This item is divided in some more sub items:
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Figure 4-5: SOVS Signal Shape with FlexRay Parameters
4.2.3 Threshold Threshold test cases are static test cases and specified in the chapters 5.2, 6.2 and 7.2.
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Threshold uV DIG-OUT-HIGH
uV DIG-OUT-LOW
uV DIG-IN-HIGH
uV DIG-IN-LOW
uBus ActiveHigh
uBus ActiveLow
uData_0
uData_1
uData
Figure 4-6: SOVS Threshold with FlexRay Parameters
4.2.4 Timing The sub item timing contains all relevant tests with the focus on the timing of the transmitted signal. This item is divided in some more sub items:
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Figure 4-7: SOVS Timing with FlexRay Parameters
4.2.4.1 Masks This vector tests the asymmetric delay in the network.
Masks
Figure 4-8: SOVS Masks
4.2.5 Truncation The sub item truncation contains all relevant tests with the focus on the star truncation. This item is divided in some more sub items:
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Truncation dStarTruncation
dTruncation M,N
Figure 4-9: SOVS Truncation with FlexRay Parameters
4.3 Mode This vector contains the test parameters that contain the mode transitions and especially the low operation modes of the physical layer in node and active star application.
Version 2.1 Revision B June 2008 Page 60 of 553 FlexRay Physical Layer Conformance Test Specification Parameter List Idle Active FailSilent GoToSleep GoToSleep_Fail Branch Normal Normal Low Low Power Low Power ReceiveOnly Bus Bus Driver Active Star Mode
Figure 4-10: SOVS Mode with Sub Items
Version 2.1 Revision B June 2008 Page 61 of 553 FlexRay Physical Layer Conformance Test Specification Parameter List 4.3.1 Active star This sub vector contains all relevant test parameters regarding the bus driver equipped in an active star. It is divided in several sub items:
4.3.1.1 Branch Tests regarding the behaviour of branches.
Branch Active
Idle dBranchFailSilentIdle
FailSilent dBranchActive
Figure 4-11: SOVS Branch with Sub Items
4.3.1.2 Low power Tests regarding the low operation mode.
Low Power dStarWakeUpReaction
dStarGoToSleep
Figure 4-12: SOVS Low Power with Sub Items
4.3.1.3 Normal Tests regarding the normal mode and its behaviour.
Normal GoToSleep
GoToSleep_Fail
Figure 4-13: SOVS Normal with Sub Items
4.3.2 Bus driver This sub vector contains all relevant test parameters regarding the bus driver equipped in a node. It is also divided in three sub items:
4.3.2.1 Low power Tests regarding the low operation mode and its behaviour.
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Low Power uBias – Low Power
Wake-up dWakePulse
dWU 0Detect
dWU IdleDetect
dWU Timeout
Figure 4-14: SOVS Normal with Sub Items
4.3.2.2 Normal Tests regarding the normal mode and its behaviour.
Normal uBias – BD_Normal
Figure 4-15: SOVS Normal with Sub Item
4.3.2.3 ReceiveOnly Tests regarding the operation mode BD_ReceiveOnly and its behaviour.
ReceiveOnly
Figure 4-16: SOVS ReceiveOnly
4.4 Power supply This vector stresses the physical layer at its given pins, e.g. undervoltage. This SOVS parameter has three more sub items.
Power Supply Undervoltage V BAT
Undervoltage V CC
Undervoltage V IO
Figure 4-17: SOVS Power Supply
Version 2.1 Revision B June 2008 Page 63 of 553 FlexRay Physical Layer Conformance Test Specification Parameter List 4.5 Environment The environment of the IUT is tested by this vector. This SOVS parameter does not have sub items.
Environment
Figure 4-18: SOVS Environment
4.6 Dynamic low battery voltage This vector emulates the start of an engine with a dynamic low battery voltage. The supply voltage is specified in chapter 3.4. This SOVS parameter does not have sub items.
Dynamic Low Battery Voltage
Figure 4-19: SOVS Dynamic Low Battery Voltage
4.7 Ground shift This vector stresses the physical layer with a specified ground shift as described in chapter 3.1 on page 42. The ground shift generator requirements are described in chapter 2.5.5 on page 37.
Ground Shift Dynamic Ground Shift
Figure 4-20: SOVS Ground Shift
4.8 Failure This vector stresses the physical layer with predefined failures of the links, power supplies and termination. The failures are described in chapter 3.5 on page 46.
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Failure Babbling Idiot
Loss Power VBAT
TxD VCC
TxEN VIO
GND IUT
EN
STBN
BGE
Short Circuit BM
BP
TxEN
Termination Minimum R DCLoad
Maximum R DCLoad
Nominal R DCLoad
Figure 4-21: SOVS Failure with Sub Items
4.8.1 Babbling idiot This vector contains the test parameter regarding the detection and signaling of a babbling idiot. This vector does not have any sub items.
Babbling Idiot
Figure 4-22: SOVS Babbling Idiot
4.8.2 Loss This vector describes the possible loss of supply lines and digital signals at the bus driver.
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Loss Power VBAT
TxD VCC
TxEN VIO
GND IUT
EN
STBN
BGE
Figure 4-23: SOVS Loss with several Sub Items
4.8.3 Short circuit This vector describes the possibility of short circuit of digital signals and the bus wires and the behaviour of the bus driver.
Short Circuit BM iBM GNDShortMax
iBM BATShortMax
iBM -5VShortMax
BP iBP GNDShortMax
iBP BATShortMax
iBP -5VShortMax TxEN
Figure 4-24: SOVS Short Circuit with Sub Items
4.8.4 Termination This vector contains test parameters regarding different termination values.
Termination Minimum R DCLoad
Maximum R DCLoad
Nominal R DCLoad
Figure 4-25: SOVS Termination
Version 2.1 Revision B June 2008 Page 66 of 553 FlexRay Physical Layer Conformance Test Specification Parameter List 4.9 Functional class Some functions of the IUT are grouped in Functional Classes that must be test by this vector.
Functional Class BD voltage regulator control
Bus Driver – Bus Guardian control interface
Bus Driver internal voltage regulator
Bus Driver logic level adaption
Active Star – Bus Guardian interface
Active Star – Communication controller interface
Active Star – Voltage Regulator Control
Active Star – Internal Voltage Regulator
Figure 4-26: SOVS Functional Class
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5 Test Cases for Bus Drivers
5.1 Configuration
5.1.1 Topology As specified in chapter 2.4. All IUTs are the same type and manufacturer.
5.1.2 Test planes
5.1.2.1 Analog signals The test planes at the FlexRay node for analog signals (FlexRay bus) are the same as specified in [01-PL Spec].
TP1 TP2 TP3 TP4
Transmitting Receiving Node Node
BP BD Network BD
BM
Figure 5-1: Test Planes @ the Nodes (analog Signals)
TP Name Signals Description
TP1 uBP /uBM Bus signals of the transmitter as close as possible to the chip
TP2 uBP /uBM Bus signals of the transmitter at the connector near to the network
TP3 uBP /uBM Bus signals of the receiver at the connector near to the network
TP4 uBP /uBM Bus signals of the receiver as close as possible to the chip
Table 5-1: Test Planes @ the Nodes (analog Signals)
Version 2.1 Revision B June 2008 Page 68 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers 5.1.2.2 Digital signals The test planes at the FlexRay node for digital signals (observed by the logic analyzer) are specified as:
TxEN TxD RxEN RxD BGE EN STBN IUT SCSN ERRN INTN WAKE INH1
Figure 5-2: Test Planes @ the Nodes (digital Signals)
TP Name Signals Basis Description
TP_Nx_TxEN TxEN VIO /V CC Transmit Data Enable Not input signal of the IUT
TP_Nx_TxD TxD VIO /V CC Transmit Data input signal of the IUT
TP_Nx_RxD RxD VIO /V CC Receive Data output signal of the IUT
TP_Nx_ERRN ERRN VIO /V CC Error Not output signal of the IUT (only if host interface A is implemented)
TP_Nx_STBN STBN VIO /V CC Standby Not input signal of the IUT (only if host interface A is implemented)
TP_Nx_INTN INTN VIO /V CC Interrupt Not output signal of the IUT (only if host interface B is implemented)
TP_Nx_SCSN SCSN VIO /V CC The SCSN input signal of the SPI interface of the IUT (only if host interface B is implemented)
TP_Nx_EN EN VIO /V CC Mode control input signal of the IUT (only if Functional Class "BD voltage regulator control" is implemented)
TP_Nx_WAKE WAKE VBAT Local wake-up input signal input of the IUT (only if Functional Class "BD voltage regulator control" is implemented)
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TP Name Signals Basis Description
TP_Nx_INH1 INH1 VBAT INH1 output signal of the IUT (only if Functional Class "BD voltage regulator control" is implemented)
TP_Nx_BGE BGE VIO /V CC BG Enable input signal (only if Functional Class "Bus Driver - Bus Guardian control interface" is implemented)
TP_Nx_RxEN RxEN VIO /V CC Receive Data Enable Not output signal of the IUT (only if Functional Class "Bus Driver - Bus Guardian control interface" is implemented)
Table 5-2: Test Planes @ the Nodes (digital Signals)
5.1.2.3 Naming convention The test planes used in this specification are divided in three parts for digital signals and two parts for analog signals. The naming convention is defined as: • TPy_Nx for analog signals y describes the location of the test plane x represents the number of the node, see topology in chapter 2.4 • TP_Nx_YYY for digital signals x represents the number of the node, see topology in chapter 2.4 YYY stands for the digital signal • The analog test planes of the FlexRay bus are differential signals: uBus = uBP - uBM . • The digital test planes of the digital signals are single ended signals: uRxD, uTxD and uTxEN . Example 1: TP_N1_RxD represents the test plane for the single ended signal RxD at node 1. Example 2: TP4_N23 represents the test plane for the differential analog bus signal of the receiver at node 23.
5.1.2.4 Test planes for the oscilloscope The oscilloscope observes the following test planes: • TP_N23_RxD • TP_N23_TxEN • TP_N23_TxD
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• TP1_N23 (if the node is a transmitter) • TP4_N23 (if the node is a receiver) • TP4_N2 • TP4_N12 • TP_N12_RxD • TP_N24_TxD • TP_N24_TxEN • TP_N24_RxD • TP_N24_BP • TP_N24_BM • Eye_TPAS4_B3 • TP_N23_UGS (dynamic ground shift voltage)
1 UGS GND Node23 1m
Test Planes for Oscilloscope 11 PS 11m 2 AS 4 1.5m 0.15m 10m
3 BP/BM 0 0 . . 0 2 m 2 .1 m .2 m m m 0 1 0.2m 0.2m 0.2m 3.5m
24 23 22 21 2 14 13 12 11
BP/BM BP/BM BP/BM BP/BM RxD TxD, TxEN (& RxD)
Figure 5-3: Test Planes for the Oscilloscope
5.1.2.5 Test planes for the logic analyzer The logic analyzer observes the following test planes: • TP_Nx 13 _RxD • TP_Nx_RxEN • TP_Nx_TxD • TP_Nx_TxEN • TP_Nx_STBN • TP_Nx_ERRN • TP_Nx_INH1 • TP_Nx_WAKE • TP_Nx_BGE • TP_Nx_EN
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• TP_Nx_INTN • TP_Nx_SCSN
5.1.2.6 Test planes for the pattern generator The pattern generator stimulates the following test planes: • TP_Nx 14 _TxD • TP_Nx_TxEN • TP_Nx_BGE • TP_N24_WAKE 5.1.2.7 Test planes for current measurement A shunt shall be implemented in order to measure the current of the bus wires:
14 • TP_Nx _R iBP
• TP_Nx_R iBM 5.1.3 Test Patterns
5.1.3.1 Wake-up The wake-up signal is specified in [08-Prot Spec] and shown in the following figure:
gdWakeupSymbolTxLow gdWakeupSymbolTxIdle High TxD Low
High TxEN Low
Figure 5-4: Wake-up Symbol for the Test Pattern The length of gdWakeupSymbolTxLow and gdWakeupSymbolTxIdle shall be independent of the bus speed. The wake-up pattern shall be repeated pWakeupPattern times. Length of gdWakeupSymbolTxLow : 6 µs Length of gdWakeupSymbolTxIdle : 18 µs Number of repetitions ( pWakeupPattern ): 2
5.1.3.2 TSS The TSS symbol is specified in [08-Prot Spec] and shown in the following figure:
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Figure 5-5: Test Pattern for the TSS Symbol The length of gdTSSTransmitter (1100ns) depends on the bus speed (see [08-Prot Spec]) and is specified in chapter 8.1. The pattern of gdTSSTransmitter is sent in each test case once.
5.1.3.3 Data signal 50/50 This test signal has a duty cycle of 50% (including the BSS):
gdBit 0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-6: Test Pattern for Data Signal 50/50
5.1.3.4 Data signal 10/90 This test signal has a duty cycle of 10/90, that means that 1 bit has high and 9 bit have low level (including the BSS):
gdBit 0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-7: Test Pattern for Data Signal 10/90
5.1.3.5 Data signal 90/10 This test signal has a duty cycle of 90/10, that means that 9 bit have high and 1 bit has low level (including the BSS):
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gdBit 0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-8: Test Pattern for Data Signal 90/10
5.1.3.6 Data signal 10Bit Low The IUT shall signal Data_0 on the bus with this test signal.
gdBit 0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-9: Test Pattern 10Bit Low
5.1.3.7 Data signal 10Bit High This test signal is necessary to verify the BD_Standby state of the IUT. TxD shall stay in logical HIGH state to be prepared for a possible additional feature called “Wake on TxD”.
gdBit 0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-10: Test Pattern 10Bit High
5.1.3.8 Data signal SymbolTxLow_Idle This test signal shall be used to switch between Low and Idle.
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gdSymbolTxLow gdSymbolTxIdle High TxD Low
High TxEN Low
Figure 5-11: Test Pattern SymbolTxLow_Idle Length of the gdSymbolTxLow : 6µs Length of the gdSymbolTxIdle : 6µs
5.1.3.9 Current measurement This test pattern shall be used to measure the current flowing from the BD into the bus wires.
Data_0 Idle Data_1 Idle gdSymbolTxLow gdSymbolTxIdle gdSymbolTxHigh gdSymbolTxIdle High TxD Low
High TxEN Low 1500µs 1500µs 1500µs 1500µs
Figure 5-12: Test Pattern for Current Measurement of Bus Wires
5.1.3.10 Non wake-up short idle phase This test pattern shall be used to check the robustness of the IUT not to wake-up in case of a non suitable wake-up pattern due to a shorter idle phase.
Idle 6µs Data_0 0.9µs Idle 6µs Data_0 Idle High TxD Low
High TxEN Low
Figure 5-13: Test Pattern for non suitable Wake-up short idle Phase
5.1.3.11 Non wake-up short low phase This test pattern shall be used to check the robustness of the IUT not to wake-up in case of a non suitable wake-up pattern due to a shorter low phase.
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Idle 6µs Data_0 6µs Idle 0.9µs Data_0 Idle High TxD Low
High TxEN Low
Figure 5-14: Test Pattern for non suitable Wake-up short low Phase
5.1.3.12 Non wake-up prolonged pattern This test pattern shall be used to check the robustness of the IUT not to wake-up in case of a non suitable wake-up pattern due to a prolonged pattern.
Idle 6µs Data_0 140µs Idle 6µs Data_0 Idle High TxD Low
High TxEN Low
Figure 5-15: Test Pattern for non suitable Wake-up prolonged Pattern
5.1.4 Observation windows
5.1.4.1 Parameters dBDTx10 , dBDTx01 , dBDRx10 and dBDRx01
TSS gdWakeupSymbolTxLow gdWakeupSymbolTxIdle gdWakeupSymbolTxLow gdWakeupSymbolTxIdle 60gdBit 180gdBit 60gdBit 180gdBit 11gdBit High TxD Low
TxEN High Low High RxD Low
42.6µs 10Bit HIGH and 10Bit LOW Pattern, 20gdBit Trigger Event Zoom
Zoom
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 High TxD Low
High TxEN Low
High RxD Low
Observation Window
Figure 5-16: Observation Point for the Analysis of the Timing Characteristics Trigger event: first positive edge of TxD or RxD signal (inside WUP).
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Trigger level: 70% of VIO (if implemented, otherwise VCC) level. Start acquisition point: 42.6µs after the trigger event. Observation Window : 2.0µs The [01-PL Spec] shows the measurement descriptions of the parameters [dBDRx10 , dBDRx01 ] in figure 8-6 and of the parameters [ dBDTx10 , dBDTx01 ] in figure 8-8.
5.1.4.2 Verification of bus in idle state The bus is verified to be in idle or idle_LP state at TP1/4 of node 23. Trigger event: first negative edge of external trigger signal. Start acquisition point: 0µs after the trigger event. Observation Window : 5.0µs
The absolute differential voltage |uBus | must not exceed 30mV ( uBDTx idle ).
5.1.4.3 Shortened bits with low state
TSS 3x 10Bit High 2x 10Bit High 11gdBit 30gdBit 20gdBit High TxD Low Zoom High TxEN Low
90/10 Pattern 10gdBit
Zoom – Observation Window
0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-17: Observation Point for the shortened Bits with Low State Trigger event: negative edge of external trigger, trigger level 2.5V. Start acquisition point: 2.95µs after the trigger event. Observation Window : 1µs
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TSS 3x 10Bit Low 2x 10Bit Low 11gdBit 30gdBit 20gdBit High TxD Low Zoom High TxEN Low
10/90 Pattern 10gdBit Zoom – Observation Window
0 1 2 3 4 5 6 7 8 9 High TxD Low
High TxEN Low
Figure 5-18: Observation Point for the shortened Bits with High State Trigger event: negative edge of external trigger, trigger level 2.5V. Start acquisition point: 2.87µs after the trigger event. Observation Window : 1µs
5.1.4.5 Dynamic ground shift
Wake-Up TSS Pattern 11gdBit 1x 50/50 pattern 9x 50/50 pattern
TxD
TxEN
4 Bits = 400ns 6V
3 Bits = 300ns 2V 0V UGS 10 Bits = 1 µs 25µs 1ms
Observation Window 15µs
Figure 5-19: Observation Point for Dynamic Ground Shift Trigger event: first falling edge of TxD (within the first wake-up low phase), trigger level +2.0V. Start acquisition point: 47µs after the trigger event. Observation Window : 15µs
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TSS 11gdBit 10x 50/50 Pattern High TxD Low
High TxEN Low
High uBus Low Observation Window 15µs
Figure 5-20: Observation Window for Eye Diagram Trigger event: negative edge of external trigger. Start acquisition point: immediately. Observation Window : 9.5µs (500ns space to frame end)
5.1.5 Operation modes of the bus driver The IUT has the following operation modes: • BD_Normal : receive/transmit possible. • BD_Standby : receive/transmit NOT possible. • BD_Sleep : optional: receive/transmit NOT possible. • BD_ReceiveOnly : optional: receive possible, transmit NOT possible.
The IUT reaches the operation modes by: Operation mode Hard Wired Signals SPI BD_Normal STBN = High Product specific. Part EN (optional 15 ) = High of the implementation. BD_Standby STBN = Low Product specific. Part EN (optional 15 ) = Low of the implementation. BD_Sleep 14 STBN = Low Product specific. Part EN (optional 15 ) = pull-up of the implementation.
to V IO /V CC
BD_ReceiveOnly 14 STBN = High Product specific. Part EN (optional 15 ) = Low of the implementation.
Table 5-3: Operation modes of the Bus Driver
5.1.6 Power supplies The used power supplies:
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• In case of a VBAT pin the V BAT supply is connected to the IUT with different voltages. VBAT = VBATUndervoltage , +5.5V, +7.0V, default.
• In case of a V CC pin the V CC supply is connected to the IUT with different voltages. VCC = VCCUndervoltage , +5.0V. All other supplies are optional and part of the implementation.
5.1.7 Stress • The ground shift is located as shown in Figure 3-2. • The low battery is a global stress parameter and affects all nodes of the topology. Note that the active star is not stressed at all in bus driver test cases! The AS is always supplied with all implemented supply voltages and not stressed by low battery or ground shift.
5.1.8 Failures The failures are located as shown in Figure 3-5.
5.1.9 Optional features The following features are optional as specified in [01-PL Spec] and shall be tested in the test cases if available in the IUT: • BD mode BD_Sleep • BD mode BD_ReceiveOnly • Signal BGE • Signal INH1 • Signal RxEN • Signal WAKE • Signal EN
• Power supply input VIO
• Power supply input VCC
• Power supply input VBAT 5.1.9.1 Functional class “Bus Driver Voltage Regulator Control” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: • BD mode BD_Sleep • Signal INH1 • Signal WAKE • Signal EN
• Power supply input VBAT
Version 2.1 Revision B June 2008 Page 80 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers 5.1.9.2 Functional class “Bus Driver – Bus Guardian Control Interface” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: • Signal BGE • Signal RxEN 5.1.9.3 Functional class “Bus Driver Internal Voltage Regulator”
• This Functional Class comprises the implementation of a “V BAT ” power supply input and requires that the BD is fully operational without a V CC supply. 5.1.9.4 Functional class “Bus Driver Logic Level Adaptation”
• This Functional Class comprises the implementation of a “V IO ” power supply input and requires that the thresholds of all digital inputs can be controlled by this voltage as well as all digital outputs are related to this voltage level. 5.1.10 Definition of communication and control
5.1.10.1 Communication Matrix A (round robin test): In some test cases it is necessary that every node within the specified topology is the transmitter. That means that the test case starts with node 1 as transmitter and the other nodes transmit one after another (all other nodes are receivers). This matrix is used for observation of digital signals.
Message from Node x
Transmitters 1 2 11 12 13 14 21 22 23 24
t
Receivers all *) all *) all *) all *) all *) all *) all *) all *) all *) all *) t *) except the transmitting node
Figure 5-21: Communication Matrix A Pause between the messages 17 : 20µs.
Node 11 as transmitter: In some test instances node 11 is the transmitter and node 12 that is observed by the oscilloscope is the receiver.
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Message from Node
Transmitter 11
t
Receiver 12
t
Figure 5-22: Communication with Node 11 as Transmitter (Time Diagram)
1
T 11 ra n s PS 2 AS 4 mi tt e 3 r
24 23 22 21 2 14 13 12 11
Point of Observation
Figure 5-23: Communication with Node 11 as Transmitter (Topology)
Node 12 as transmitter: In some test instances node 12 is the transmitter and node 23 that is observed by the oscilloscope is the receiver.
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Message from Node
Transmitter 12
t
Receiver 23
t
Figure 5-24: Communication with Node 12 as Transmitter (Time Diagram)
1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Point of Observation Transmitter
Figure 5-25: Communication with Node 12 as Transmitter (Topology)
Node 1 as transmitter: In some test instances node 1 is the transmitter and node 2 that is observed by the oscilloscope is the receiver.
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Message from Node
Transmitter 1
t
Receiver 2
t
Figure 5-26: Communication with Node 1 as Transmitter (Time Diagram)
Transmitter 1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Point of Observation
Figure 5-27: Communication with Node 1 as Transmitter (Topology)
Node 23 as transmitter: In this communication node 23 is the transmitter and observed by the oscilloscope.
Message from Node
Transmitter 23
t
Figure 5-28: Communication with Node 23 as Transmitter (Time Diagram)
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1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter Point of Observation
Figure 5-29: Communication with Node 23 as Transmitter (Topology)
Node 24 as transmitter: In this communication node 24 is the transmitter and node 23 is observed by the oscilloscope.
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Message from Node
Transmitter 24
t
Receiver 23
t
Figure 5-30: Communication with Node 24 as Transmitter (Time Diagram)
1
11
PS 2 AS 4 3
24 23 22 21 2 14 13 12 11
Transmitter Point of Observation
Figure 5-31: Communication with Node 24 as Transmitter (Topology)
Node 24 and 23 as transmitter: In this communication node 24 and 23 are the transmitters with scope observation of the bus at node 23 and logic analyzer observation of both nodes.
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Message from Node
Transmitter 23 24
t
Receiver 24 23
t
Figure 5-32: Communication with Node 24 as observed Transmitter (Time Diagram)
1
11
PS 2 AS 4 3
24 23 22 21 2 14 13 12 11
Transmitter Point of Observation
Figure 5-33: Communication with Node 24 as observed Transmitter (Topology)
Node 24 and 1 as transmitter: In this communication node 24 and node 1 are the transmitters and all IUTs are observed by the logic analyzer.
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Message from Nodes
Transmitters 24 1
t
Figure 5-34: Communication with Node 24 and 1 as Transmitter (Time Diagram)
Transmitter 1
Point of Observation 11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Figure 5-35: Communication with Node 24 and 1 as Transmitter (Topology)
5.1.10.2 Control Host command: Wait 1000µs after a host command to the IUT before performing the next step in the test execution. In that case the IUT is able to switch from one mode to the other. The commanded nodes and the observed nodes are specified in the test cases.
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1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Host Command to the Nodes 1, 2, 11-14 and 21-24
Figure 5-36: Host Command to IUTs
5.1.11 Standard preamble 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD shall be in logical HIGH (idle) state. 6. In case of a BGE signal this signal shall be in logical HIGH state. 7. In case of a VIO signal this voltage shall be supplied by the voltage used in the implementation of the conformance test. 8. In case of a WAKE pin this signal shall be in logical HIGH state. 9. Stimulate all IUTs via host interface to enter BD_Normal . 10. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
5.1.12 Standby preamble 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration.
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2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD shall be in logical HIGH (idle) state. 6. In case of a BGE signal this signal shall be in logical HIGH state. 7. In case of a VIO signal this voltage shall be supplied by the voltage used in the implementation of the conformance test. 8. In case of a WAKE pin this signal shall be in logical HIGH state. 9. Stimulate all IUTs via host interface to enter BD_Standby . 10. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
5.1.13 Sleep preamble The sleep preamble will only be used if the IUT has the Functional Class “BD voltage regulator control” ( BD_Sleep mode) implemented. The hosts of all nodes except node 24 will be switched off. The needed host command will be product specific. 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD shall be in logical HIGH (idle) state. 6. In case of a BGE signal this signal shall be in logical HIGH state. 7. In case of a VIO signal this voltage shall be supplied by the voltage used in the implementation of the conformance test. 8. In case of a WAKE pin this signal shall be in logical HIGH state. 9. Stimulate all IUTs via host interface to enter BD_Sleep . 10. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
Version 2.1 Revision B June 2008 Page 90 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers 5.1.14 ReceiveOnly preamble The ReceiveOnly preamble will only be used if the IUT has the BD_ReceiveOnly mode implemented. The needed host command will be product specific. 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD shall be in logical HIGH (idle) state. 6. In case of a BGE signal this signal shall be in logical HIGH state. 7. In case of a VIO signal this voltage shall be supplied by the voltage used in the implementation of the conformance test. 8. In case of a WAKE pin this signal shall be in logical HIGH state. 9. Stimulate all IUTs via host interface to enter BD_ReceiveOnly . 10. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
5.1.15 Standard postamble 1. Set ground shift to 0V. 2. Set to faultless configuration (reset failures). 3. Switch off power supplies.
5.1.16 Receiver masks The path asymmetry is a very important parameter for the decoding of FlexRay signals. Each component in the physical layer may cause asymmetries, transmitters, active stars, receivers, but also passive network segments as passive busses or stars, connectors, ESD protection, etc. As a consequence, is is not enough to just sum up the allowed asymmetries for transmitters, receivers and active stars. These parameters are verified seperately. The complete physical layer including the whole signal path may cause a path asymmetry as defined in chapter 12 in [01-PL Spec]. For a sequence of 10 bits logical LOW the allowed path asymmetry is:
Signal path asymmetry including jitter: ±25 ns
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Hint: The accuracy/resolution of the logic analyzer as described in chapter 2.5.9 must be taken into account. The sequence of 10 bit logical LOW must be enclosed by logical HIGH sequences, i.e. the bus shall change from Data_1 to 10 bit times Data_0 and back to Data_1 . The asymmetric channel delays are independent from the propagation delay.
5.1.17 Services In this section, all required services are specified on measurement device or generator. Each device (oscilloscope, logic analyzer, pattern generator, power supply, etc.) requires own, dedicated services.
5.1.17.1 Oscilloscope services The oscilloscope requires services to configure the scope, to start acquisition and to obtain specific parameters from the acquired data. The oscilloscope observes bus and logic signals and is part of the upper tester as well as the lower tester. Scope
IConfiguration
Configure
Acquisition
Channel
TriggerConfig
IAcquireBusData
Initiate
GetWaveform
Figure 5-37: Oscilloscope Services
5.1.17.1.1 Services of the IConfiguration interface • Configure scope with standard configuration properties: Acquisition related properties like type and sample rate, channel specific properties like probe attenuation, input impedance, maximal input frequency and coupling as well as trigger specific properties like trigger edge and coupling: Configure(ConfigurationSet)
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• Configure scopes acquisition behaviour: Acquisition(MimimalNumberOfPoints, StartOffset, AcquisitionLength) • Configure scopes channels: Channel(Channel, Range, Offset, ProbeAttenuation, Bandwidthlimit) • Configure scopes trigger event: TriggerConfig(Source, Level, Slope)
5.1.17.1.2 Services of the IAcquisition interface • Put scope from idle into ready state. Scope will wait for trigger event immediately after this command. Acquisition is enabled for selected channels: Initiate(ChannelList) • To store acquired data of selected channels into storage structure for obtaining parameter: GetWaveform(ChannelList)
5.1.17.2 Pattern penerator services The pattern generator requires services to get configured and to prepare and upload defined pattern sequences to the pattern generator. PatternGenerator
IPatternGenerator
CreateComposedPatternMatrix
CreateComposedPattern
CreateComposedParticularPattern
UnsetBGE
CreateLocalWakeUp
CreateExternTrigger
ShiftAllPatterns
Figure 5-38: Pattern Generator Services
5.1.17.2.1 Services of the IPatternGenerator interface • To create a sequence of test patterns that shall be sent by a pre-defined matrix of transmitters. This method is very similar to CreateComposedPattern() but allows to use pre-defined sequences of
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transmitters (communication matrices) instead of stating each single transmitter: CreateComposedPatternMatrix(BitDuration, Matrix, WakeUpNodes, WakeUpPattern, WakeUpQuantity, Patterns, IdleTime, RepeatPatternSequence, WaitForTrigger) • Create a composed pattern sequence with specific communication matrix, patterns, selectable wake-up nodes, etc.: CreateComposedPattern (gBitDuration, Nodes, WakeUpNodes, WakeUpPattern, WakeUpQuantity, Patterns, IdleTime, RepeatPatternSequence, WaitForTrigger ) • To create test patterns that make use of pre-defined particular test patterns. CreateComposedParticularPattern(BitDuration, WakeUpNodes, WakeUpPattern, WakeUpQuantity, SpecialPatterns, RepeatPatternSequence, WaitForTrigger) • Set BGE input of specific nodes to logical LOW state for a defined period. If this method is unused, all BGE inputs have to be set to logical HIGH. If Offset is set to zero, the selected BGE signals are logical LOW immediately after starting the test execution: UnsetBGE(StateDuration, SelectedNodes, Offset) • To create a local wake-up pulse at the WAKE input of the IUT, if this input is implemented. The pulse width and direction (positive or negative) can be selected. CreateLocalWakeUp(WakeUpType, Offset, Pulsewidth) • To create a specific trigger event for devices that are triggered by the pattern generator, e.g. the oscilloscope or the data acquisition unit. CreateExternTrigger(Externtrigger, EdgeDirection, Offset) • To all signals between the bit being at offset = 0 (that one which is the first bit in time after the rising edge of TRIGGER_1, i.e. at the begin of the programmed pattern) and the bit which is the first bit in time which belongs to the composed pattern sequence: ShiftAllPatterns(BitsToShift)
5.1.17.3 Logic analyzer services The logic analyzer requires a service to get configured. LogicAnalyzer
ILogicAnalyzer
Configure
Figure 5-39: Logic Analyzer Services
5.1.17.3.1 Services of the ILogicAnalyzer interface
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• Configure the logic analyzer to acquire selected signals with given sample rate, thresholds of the data PODs and acquisition depth: Configure(SignalsToCapture, SampleRate, ThresholdSettings, MinAcquisitionDepth, TriggerSignal, TriggerDelay)
5.1.17.4 Logic analysis system services The logic analyzer requires a service to execute a test. LogicAnalysisSystem
ILogicAnalysisSystem
PrepareLogicTest
RunLogicTest
ExecuteLogicTest
FinishLogicTest
Figure 5-40: Logic Analysis System Services
5.1.17.4.1 Services of the ILogicAnalysisSystem interface • Execute a test case. Preconditions to execute a logic test case are ILogicAnalyzer.Configure, IPatternGenerator.Configure, IPatternGenerator.CreateComposedPattern or IPatterGenerator.CreateParticularPattern and optionally IPatternGenerator.UnsetBGE: ExecuteLogicTest() • To prepare a test case. Preconditions are the same as in ExecuteLogicTest. PrepareLogicTest() • To Start a logic test. Precondition: PrepareLogicTest. RunLogicTest() • To Finish a logic Test. Precondition: RunLogicTest. FinishLogicTest()
5.1.17.5 Power supply services Power supplies are required for providing the battery voltage, Vcc, Vio and Ground Shift to the standard net. Additionally, the power supply for emulating the battery must be able to simulate a battery voltage breakdown which is commonly caused by the starter circuit.
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PowerSupply
IBatterySupplyConfig
Output
DynamicLowBat
EnableOutputs
IDCPowerSupplyConfig
Output
EnableOutputs
Figure 5-41: Power Supply Services
5.1.17.5.1 Services of the IBatterySupplyConfig interface • Set output voltage and current limitation of battery power supply: Output(Voltage, CurrentLimit) • Configure emulation of battery voltage breakdown by battery power supply. The pulse shape and the pulse offset from a following trigger event have to be selected. The power supply will set up the voltage of the first pulse shape point on its outputs when enabled. The pulse start requires a trigger (software/hardware). A pulse may be repeated: DynamicLowBat(Pulseform, PulseOffset, Repetitions) • Enable or disable power supply output: EnableOutputs(Enabled)
5.1.17.5.2 Services of the IDCPowerSupplyConfig interface • Set output voltage and current limitation of DC power supply. Multi-channel power supplies are supported: Output(Channel, Voltage, CurrentLimit) • Enable or disable power supply output: EnableOutputs(Enabled)
5.1.17.6 Network services Multiple switching and control services are required for setting up power supply connections, short circuits, interruptions and to set and get the bus driver states or cause local wake-up events.
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NetServices
ISwitch
SetShortCircuitBusWire
SetShortCircuitOnBoard
SetGroundShift
SetInterruptionBusWire
SetInterruptionOnBoard
SetTermination
SetSupplyConfig
SetVRType
ResetNet
IControl
SetOperatingMode
SendLocalWakeup
GetIUTStatus
SetHostParameter
Figure 5-42: Network Services
5.1.17.6.1 Services of the ISwitch interface • To set up or reset a short circuit of bus wire lines (BM, BP) with each other or one of both bus wire lines with V BAT , V CC or GND: SetShortCircuitBusWire(Line1, Line2, Enable) • To set up or reset a short circuit of digital input lines (TxEN or TxD with GND, BGE with V IO or V CC ) of the IUT within selected nodes: SetShortCircuitOnBoard(SelectedNodes, Line1, Line2, Enable) • To set up or reset a ground shift in selected nodes. A selected node is always shifted by +5V: SetGroundShift(SelectedNodes, Enable)
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• To set up or reset an interruption of bus lines (BP, BM) of selected nodes: SetInterruptionBusWire(SelectedNodes, Lines, Enable) • To set up or reset an interruption of digital inputs or supply lines (TxD, TxEN, STBN, BGE, WAKE, V BAT , V CC , V IO or GND) of the IUT within selected nodes: SetInterruptionOnBoard(SelectedNodes, Lines, Enable) • To set up a selected termination in selected nodes: SetTermination(SelectedNodes, TerminationType, Enable) • To set up a specific power supply configuration of selected nodes: SetSupplyConfig(SelectedNodes, SuppliesConfiguration) • To select switching voltage regulators (default) or linear voltage regulators for VCC and VIO, depending on the requirements of the specific test case: SetVRType(SelectedNodes, RegulatorConfig) • To reset all failures (short circuits, interruptions) and abnormal conditions (ground shift, specific power supply) in all nodes: ResetNet()
5.1.17.6.2 Services of the IControl interface • To set up a specific operating mode in selected nodes: SetOperatingMode(SelectedNodes, OperationalMode) • To cause a local wake-up event in selected nodes: SendLocalWakeup(SelectedNodes, WakeupEvent) • To acquire the status of the IUT of selected nodes: GetIUTStatus(SelectedNodes) • To set specific parameters of the host processor to control the nodes hardware configuration, i.e. to enable/disable level shifters, for example: SetHostParameter(SelectedNodes, HostParameter, State)
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5.2 Static test cases The motivation of static test cases is to check the availability and the boundaries in the data sheet of the IUT (topology independent). Every parameter must be part of the data sheet and fulfill the specified boundaries. If at least one parameter does not pass this test, the result of the whole conformance test is failed.
Index Parameter SOVS Brace Description Min Max Unit
1. dRxAsym Communication. Receiver delay 5 ns Delay mismatch
2. dBDRx10 Communication. Receiver delay, 100 ns Delay negative edge
3. dBDRx01 Communication. Receiver delay, 100 ns Delay positive edge
4. dBDRxai Communication. Idle reaction time 50 400 ns Timing
5. dBDRxia Communication. Activity reaction time 100 450 ns Timing
6. dTxAsym Communication. Transmitter delay 4 ns Delay mismatch
7. dBDTx10 Communication. Transmitter delay, 100 ns Delay negative edge
8. dBDTx01 Communication. Transmitter delay, 100 ns Delay positive edge
9. dBDTxai Communication. Propagation delay 100 ns Timing active idle
10. dBDTxia Communication. Propagation delay 100 ns Timing idle active
11. dBusTxai Communication. Transition time 30 ns Signal Shape active idle
12. dBusTxia Communication. Transition time 30 ns Signal Shape idle active
18 13. dBusTx01 Communication. Rise time differential 3.75 18.75 ns Signal Shape voltage (20% 80%)
18 14. dBusTx10 Communication. Fall time differential 3.75 18.75 ns Signal Shape voltage (80% 20%)
19 15. uBDTx active Communication. Absolute differential 600 2000 mV Signal Shape voltage while sending
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Index Parameter SOVS Brace Description Min Max Unit
19 16. uBDTx idle Communication. Absolute differential 0 30 mV Signal Shape voltage while Idle
21 21 17. uV DIG-OUT-HIGH Communication. Output voltage on a 0.8xuV DIG 1.0xuVDIG - Threshold digital ouput, when in logical high state 20
21 18. uV DIG-OUT-LOW Communication. Output voltage on a 0.2xuV DIG - Threshold digital ouput, when in logical low state 20
21 19. uV DIG-IN-HIGH Communication. Threshold for 0.7xuV DIG - Threshold detecting a digital input as on logical high
21 20. uV DIG-IN-LOW Communication. Threshold for 0.3xuV DIG - Threshold detecting a digital input as on logical low
21. uBus ActiveHigh Communication. Upper receiver 150 425 mV Threshold threshold for detecting activity
22. uBus ActiveLow Communication. Lower receiver -425 -150 mV Threshold threshold for detecting activity
23. uData0 Communication. Receiver threshold for -30022 -15022 mV Threshold detecting Data_0
24. uData1 Communication. Receiver threshold for 150 22 300 22 mV Threshold detecting Data_1
25. ∆uData Communication. Mismatch of receiver 1022 % Threshold thresholds
26. dActivity Communication. Allowed time for 100 300 ns Detection Timing receiver to detect bus activity
27. dIdleDetection Communication. Allowed time for 50 250 ns Timing receiver to detect bus Idle
28. RCM1 , RCM2 Environment Common mode input 10 40 kΩ resistance
29. uCM Environment. Common mode -10 +15 V Ground Shift voltage range
30. SPI interface 23 Environment Characteristics of the 0.01 1 MBit/s optional SPI bus driver to host interface
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Index Parameter SOVS Brace Description Min Max Unit
31. iBM GNDShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted to GND
32. iBP GNDShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted to GND
33. iBP BAT48ShortMax Failure. Maximum output 120 mA Short circuit.BP current when shorted
to V BAT =48V
34. iBM BAT48ShortMax Failure. Maximum output 120 mA Short circuit.BM current when shorted
to V BAT =48V
35. iBMBAT27ShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted
to V BAT =+27V
36. iBPBAT27ShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted
to V BAT =+27V
37. uBias – Mode. Voltage @ BP & BM 1800 3200 mV BD_Normal 24 Bus Driver. during bus state Idle Normal
38. uBias – Mode. Voltage @ BP & BM -200 +200 mV Low Power 24 Bus Driver. during bus state Low Power Idle_LP
39. dWakePulse Mode. Duration of a valid 1 500 µs Filter Bus Driver. wake pulse @ local Low Power. WAKE pin Wake-up
40. dWU 0Detect Mode. Time for detection of 1 4 µs Bus Driver. a Data_0 phase in Low Power. WU pattern Wake-up
41. dWU IdleDetect Mode. Time for detection of 1 4 µs Bus Driver. a Idle phase in WU Low Power. pattern Wake-up
42. dWU Timeout Mode. Acceptance timeout 48 140 µs Bus Driver. for WU pattern Low Power. recognition Wake-up
43. VBAT for Power Supply Battery voltage 7 V WU detector required for wake-up detector operation
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Index Parameter SOVS Brace Description Min Max Unit
44. uUV BAT Power Supply Transition to low 2 5.5 V power when VBAT voltage falls below product specific threshold
45. uUV CC Power Supply Transition to low 2 Product V power when VCC specific voltage falls below product specific threshold
46. dUV CC Power Supply Reaction time for 1000 ms VCC undervoltage detection
47. iBP Leak Mode. Leakage current 25 µA Bus Driver. when all supplies are
Off.iBP Leak switched off
48. iBM Leak Mode. Leakage current 25 µA Bus Driver. when all supplies are
Off.iBM Leak switched off
49. Functional Functional Class Checks the complete - - Class implementation of all ”BD voltage specified options regulator control” 50. Functional Functional Class Checks the complete - - Class implementation of all ”Bus Driver – specified options Bus Guardian control interface” 51. Functional Functional Class Checks the complete - - Class implementation of all ”Bus Driver specified options internal voltage regulator” 52. Functional Functional Class Checks the complete - - Class implementation of all ”Bus Driver specified options logic level adaptation” 53. T Environment Ambient temperature -40 +125 °C
54. dBDTxDM Communication. Transmitter on/off 50 ns Delay delay mismatch |dBDTxia -dBDTxai |
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Index Parameter SOVS Brace Description Min Max Unit
55. iBM-5VShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted
to V BAT =-5V
56. iBP-5VShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted
to V BAT =-5V
57. dRxSlope Communication. Fall and rise time 5 ns Timing 20%-80%, 15pF load
58. iBMBP ShortMax Failure. Maximum output 100 mA Short current when BM circuit.BMBP shorted BP
59. iBPBM ShortMax Failure. Maximum output 100 mA Short current when BP circuit.BPBM shorted BM
60. iBMBAT60ShortMax Failure. Maximum output 150 mA Short circuit.BP current when shorted
to V BAT =+60V
61. iBPBAT60ShortMax Failure. Maximum output 150 mA Short circuit.BM current when shorted
to V BAT =+60V
62. dUV VBAT Power Supply Reaction time for 1000 ms VBAT undervoltage detection
63. uUV IO Power Supply Transition to low 0.75 Product V power when VIO specific voltage falls below product specific threshold
64. dUV IO Power Supply Reaction time for VIO 1000 ms undervoltage detection
Table 5-4: Static Test Cases
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5.3 Test Cases
5.3.1 Communication.Delay. dBDTx01
5.3.1.1 to 5.3.1.6: Transmitter delay dBDTx01
5.3.1.1.1 Test Purpose This test checks the transmitter delay dBDTx01 from low to high according to figure 8-8 in [01-PL Spec] while no stress condition is present.
5.3.1.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.1.1.3 Preamble (setup state) • Standard preamble.
5.3.1.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TP1_N23 of node 23 according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_N23_INH1 of node 23. • Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
5.3.1.1.5 Postamble • Standard postamble.
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5.3.1.1.6 Pass- / Fail Criteria Pass criteria: • dBDTx01 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
5.3.1.1.7 Test Instances Instance 5.3.1.1 5.3.1.2 5.3.1.3 5.3.1.4 5.3.1.5 5.3.1.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition BD_VRC
impl.
Configuration Power Supply VBAT =
5.5V
Ground Shift -5.0V @ -5.0V @
N23 N24
Failure FL7 @ FL8 @
N23 N23
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.2 Communication.Delay. dBDTx10
5.3.2.1 to 5.3.2.6: Transmitter delay dBDTx10
5.3.2.1.1 Test Purpose This test checks the transmitter delay dBDTx10 from high to low according to figure 8-8 in [01-PL Spec] while no stress condition is present.
5.3.2.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.2.1.3 Preamble (setup state) • Standard preamble.
5.3.2.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TP1_N23 of node 23 according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_N23_INH1 of node 23. • Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
5.3.2.1.5 Postamble • Standard postamble.
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5.3.2.1.6 Pass- / Fail Criteria Pass criteria: • dBDTx10 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
5.3.2.1.7 Test Instances Instance 5.3.2.1 5.3.2.2 5.3.2.3 5.3.2.4 5.3.2.5 5.3.2.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition BD_VRC
impl.
Configuration Power Supply VBAT =
5.5V
Ground Shift -5.0V @ -5.0V @
N23 N24
Failure FL7 FL8
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.3 Communication.Delay. dTxAsym
5.3.3.1 to 5.3.3.6: Transmitter asymmetry dTxAsym
5.3.3.1.1 Test Purpose This test case calculates the asymmetric transmitter delay that is measured by the parameters dBDTx01 (chapter 5.3.1.1) and dBDTx10 (chapter 5.3.2.1) according to figure 8-8 in [01-PL Spec] while no stress condition is present. All acquired asymmetric transmitter delays for positive and negative edges are used to calculate the resulting asymmetry in pairs according to the applied test condition.
5.3.3.1.2 Configuration • No configuration needed.
5.3.3.1.3 Preamble (setup state) • No preamble necessary.
5.3.3.1.4 Test execution • Calculation of | dBDTx10 -dBDTx01 | as measured in the test cases in chapters 5.3.1and 5.3.2.
5.3.3.1.5 Postamble • No postamble necessary.
5.3.3.1.6 Pass- / Fail Criteria Pass criteria: • |dBDTx10 -dBDTx01 | ≤ 4ns.
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5.3.3.1.7 Test Instances Instance 5.3.3.1 5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Test dBDTx01 dBDTx01 dBDTx01 dBDTx01 dBDTx01 dBDTx01 Description (chapter (chapter (chapter (chapter (chapter (chapter 5.3.1.2) 5.3.1.3) 5.3.1.1) 5.3.1.4) 5.3.1.5) 5.3.1.6) and and and and and and dBDTx10 dBDTx10 dBDTx10 dBDTx10 dBDTx10 dBDTx10 (chapter (chapter (chapter (chapter (chapter (chapter 5.3.2.2) 5.3.2.3) 5.3.2.1) 5.3.2.4) 5.3.2.5) 5.3.2.6) while while while no while low while while ground ground stress battery minimal maximal shift at the shift at the condition voltage is bus load is bus load is transmitter receiver is is present present present present is present present
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.4 Communication.Delay. dBDRx01
5.3.4.1 to 5.3.4.6: Receiver delay dBDRx01
5.3.4.1.1 Test Purpose This test checks the receiver delay dBDRx01 from low to high according to figure 8-6 in [01-PL Spec] while no stress condition is present.
5.3.4.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 12 as transmitter.
5.3.4.1.3 Preamble (setup state) • Standard preamble.
5.3.4.1.4 Test execution • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_N23_INH1 of node 23. • In case node 12 is the transmitter, stimulate IUT of node 12 at TP_N12_TxD and TP_N12_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern. In case node 24 is the transmitter, stimulate the same pattern sequence at TP_N24_TxD and TP_N24_TxEN
5.3.4.1.5 Postamble • Standard postamble.
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5.3.4.1.6 Pass- / Fail Criteria Pass criteria: • dBDRx01 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
5.3.4.1.7 Test Instances Instance 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.4.6
Purpose Stress ground ground shift @ low min. bus max. bus none shift @ transmitter battery load load receiver
Precondition BD_VRC
impl.
Configuration Power Supply VBAT =
5.5V
Ground Shift -5.0V @ -5.0V @ N24 N23
Failure FL7 FL8
Preamble
Test Execution N24 as
transmitter
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.5 Communication.Delay. dBDRx10
5.3.5.1 to 5.3.5.6: Receiver delay dBDRx10
5.3.5.1.1 Test Purpose This test checks the receiver delay dBDRx10 from low to high according to figure 8-6 in [01-PL Spec] while no stress condition is present.
5.3.5.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 12 as transmitter.
5.3.5.1.3 Preamble (setup state) • Standard preamble.
5.3.5.1.4 Test execution • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_N23_INH1 of node 23. • In case node 12 is the transmitter, stimulate IUT of node 12 at TP_N12_TxD and TP_N12_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern. In case node 24 is the transmitter, stimulate the same pattern sequence at TP_N24_TxD and TP_N24_TxEN
5.3.5.1.5 Postamble • Standard postamble.
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5.3.5.1.6 Pass- / Fail Criteria Pass criteria: • dBDRx10 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
5.3.5.1.7 Test Instances Instance 5.3.5.1 5.3.5.2 5.3.5.3 5.3.5.4 5.3.5.5 5.3.5.6
Purpose Stress ground ground shift @ low min. bus max. bus none shift @ transmitter battery load load receiver
Precondition BD_VRC
impl.
Configuration Power VBAT =
Supply 5.5V
Ground Shift -5.0V @ -5.0V @ N24 N23
Failure FL7 FL8
Preamble
Test Execution N24 as
transmitter
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.6 Communication.Delay. dRxAsym
5.3.6.1 to 5.3.6.6: Receiver asymmetry dRxAsym
5.3.6.1.1 Test Purpose This test case calculates the asymmetric receiver delay that is measured by the parameters dBDRx01 (chapter 5.3.4.1) and dBDRx10 (chapter 5.3.5.1) according to figure 8-6 in [01-PL Spec] while no stress condition is present. All acquired asymmetric receiver delays for positive and negative edges are used to calculate the resulting asymmetry in pairs according to the applied test condition.
5.3.6.1.2 Configuration • No configuration needed.
5.3.6.1.3 Preamble (setup state) • No preamble necessary.
5.3.6.1.4 Test execution • Calculation of | dBDRx10 -dBDRx01 | as measured in the test cases in chapters 5.3.4 and 5.3.5.
5.3.6.1.5 Postamble • No postamble necessary.
5.3.6.1.6 Pass- / Fail Criteria Pass criteria: • |dBDRx10 -dBDRx01 | ≤ 5ns.
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5.3.6.1.7 Test Instances Instance 5.3.6.1 5.3.6.2 5.3.6.3 5.3.6.4 5.3.6.5 5.3.6.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Test dBDRx01 dBDRx01 dBDRx01 dBDRx01 dBDRx01 dBDRx01 Description (chapter (chapter (chapter (chapter (chapter (chapter 5.3.4.2) 5.3.4.3) 5.3.4.1) 5.3.4.4) 5.3.4.5) 5.3.4.6) and and and and and and dBDRx10 dBDRx10 dBDRx10 dBDRx10 dBDRx10 dBDRx10 (chapter (chapter (chapter (chapter (chapter (chapter 5.3.5.2) 5.3.5.3) 5.3.5.1) 5.3.5.4) 5.3.5.5) 5.3.5.6) while while while no while low while while ground ground stress battery minimal maximal shift at the shift at the condition voltage is bus load is bus load is transmitter receiver is is present present present present is present present
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7 Mode.Bus Driver.Low Power.Standby
5.3.7.1 to 5.3.7.3: Operation mode change from BD_Normal to BD_Standby due to host command
5.3.7.1.1 Test Purpose This test checks the ability of the IUT to change from BD_Normal mode to BD_Standby due to host command according to figure 8-2, transition number 10 in [01-PL Spec] while no stress condition is present.
5.3.7.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.1.3 Preamble (setup state) • Standard preamble.
5.3.7.1.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • Stimulate IUT in node 24 via host interface to enter BD_Standby . • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.1.5 Postamble • Standard postamble.
5.3.7.1.6 Pass- / Fail Criteria Pass criteria: • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of TxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ). • uRxD of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • in case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution.
5.3.7.1.7 Test Instances Instance 5.3.7.1 5.3.7.2 5.3.7.3
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.4 to 5.3.7.6: Operation mode change from BD_Sleep to BD_Standby due to remote wake-up
5.3.7.4.1 Test Purpose This test checks the ability of the IUT to change from BD_Sleep mode to BD_Standby due to a remote wake-up according to section 8.11 on page 60 in [01- PL Spec] and figure 8-2, transition 1 in [01-PL Spec] on page 39 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case is skipped in case the remote wake-up is not implemented.
5.3.7.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 as transmitter.
5.3.7.4.3 Preamble (setup state) • Sleep preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.7.4.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 24. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 24. • Observe and acquire the error signal of the host interface ( TP_Nx_ERRN or TP_Nx_INTN ) of all nodes. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes except node 24.
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• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern.
5.3.7.4.5 Postamble • Standard postamble.
5.3.7.4.6 Pass- / Fail Criteria Pass criteria: • uINH1 of all observed nodes shall be in logical LOW state (Sleep ) before the transmission start of the wake-up pattern, i.e. the first falling edge of uTxD or uTxEN of node 24. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep ), i.e. the IUTs are in BD_Standby mode. • uRxD of all observed nodes shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 24. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uRxD of all observed nodes shall be in logical LOW state. • In case of an available RxEN signal uRxEN all observed nodes shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 24. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uRxEN of all observed nodes shall be in logical LOW state. • The error signal shall be LOW at the host interface of all observed nodes except node 24 after the wake-up event is detected. • The error signal shall be HIGH at the host interface of node 24 while the test execution.
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5.3.7.4.7 Test Instances Instance 5.3.7.4 5.3.7.5 5.3.7.6
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.7 to 5.3.7.9: Operation mode change from BD_Sleep to BD_Standby due to local wake-up (negative pulse)
5.3.7.7.1 Test Purpose This test checks the ability of the IUT to change from BD_Sleep mode to BD_Standby due to a local wake-up (LWU) event according to section 8.10 in [01-PL Spec] on page 60 and figure 8-2, transition 1 in [01-PL Spec] on page 39 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case is skipped in case the local wake-up is not implemented.
5.3.7.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V • Failure: none. • Communication: none.
5.3.7.7.3 Preamble (setup state) • Sleep preamble.
5.3.7.7.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
5.3.7.7.5 Postamble • Standard postamble.
5.3.7.7.6 Pass- / Fail Criteria Pass criteria: • uINH1 shall be in logical LOW state (Sleep ) while the IUT of node 24 is in BD_Sleep mode, before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state (BD_Standby : Not_Sleep ). • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • The error signal shall be LOW at the host interface of node 24 after the wake-up event is detected. Test Instances Instance 5.3.7.7 5.3.7.8 5.3.7.9
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.10 to 5.3.7.12: Operation mode change from BD_Sleep to BD_Standby due to local wake-up (positive pulse)
5.3.7.10.1 Test Purpose This test checks the ability of the IUT to change from BD_Sleep mode to BD_Standby due to a local wake-up (LWU) event according to section 8.10 in [01-PL Spec] on page 60 and figure 8-2, transition 1 in [01-PL Spec] on page 39 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or an optional positive pulse by a local wake-up is not provided by the IUT. This test case is skipped in case the local wake-up is not implemented.
5.3.7.10.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V • Failure: none. • Communication: none.
5.3.7.10.3 Preamble (setup state) • Sleep preamble. Hint: set uWAKE to logical LOW before the IUT is set to BD_Sleep .
5.3.7.10.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24.
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• Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
5.3.7.10.5 Postamble • Standard postamble.
5.3.7.10.6 Pass- / Fail Criteria Pass criteria: • uINH1 shall be in logical LOW state (Sleep ) while the IUT of node 24 is in BD_Sleep mode, before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state (BD_Standby : Not_Sleep ). • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • The error signal shall be LOW at the host interface of node 24 after the wake-up event is detected.
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5.3.7.10.7 Test Instances Instance 5.3.7.10 5.3.7.11 5.3.7.12
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.13 to 5.3.7.15: Operation mode change from BD_ReceiveOnly to BD_Standby due to host command
5.3.7.13.1 Test Purpose This test checks the ability of the IUT to change from BD_ReceiveOnly mode to BD_Standby due to host command according to figure 8-2, transition number 5 in [01-PL Spec] while no other stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.7.13.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 as transmitter.
5.3.7.13.3 Preamble (setup state) • ReceiveOnly preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.7.13.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes except node 24. • Stimulate IUTs of all nodes except node 24 via host interface to enter BD_Standby .
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• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.7.13.5 Postamble • Standard postamble.
5.3.7.13.6 Pass- / Fail Criteria Pass criteria: Hint: All observed nodes must not receive the transmission of node 24, but they should detect the transmitted wake-up pattern and bus activity as remote wake-up event. Thus, uRxD and uRxEN should change from logical HIGH state to logical LOW state during test execution. • uRxD of all observed nodes shall not contain more than one falling edge (remote wake-up detection), i.e. the observed nodes shall not receive the patterns applied to uTxD and uTxEN of node 24. • in case of an available INH1 signal uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of all observed nodes shall not contain more than one falling edge (remote wake-up detection).
5.3.7.13.7 Test Instances Instance 5.3.7.13 5.3.7.14 5.3.7.15
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.16 to 5.3.7.18: Operation mode change from BD_Standby to BD_Standby due to remote wake-up
5.3.7.16.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_Standby due to a remote wake-up according to section 8.11 and figure 8-2, transition 2 in [01-PL Spec] on page 60 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case is skipped in case the remote wake-up is not implemented.
5.3.7.16.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 as transmitter.
5.3.7.16.3 Preamble (setup state) • Standby preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.7.16.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 24. • Observe and acquire the error signal of the host interface ( TP_Nx_ERRN or TP_Nx_INTN ) of all nodes. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes except node 24. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern.
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5.3.7.16.5 Postamble • Standard postamble.
5.3.7.16.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 24. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uRxD of all observed nodes shall be in logical LOW state. • The error signal shall be LOW at the host interface of all observed nodes except node 24 after the wake-up event is detected. • The error signal shall be HIGH at the host interface of node 24 while the test execution. • INH1 signal uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN all observed nodes shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 24. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uRxEN of all observed nodes shall be in logical LOW state.
5.3.7.16.7 Test Instances Instance 5.3.7.16 5.3.7.17 5.3.7.18
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.19 to 5.3.7.21: Operation mode change from BD_Standby to BD_Standby due to local wake-up (negative pulse)
5.3.7.19.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_Standby due to a local wake-up event according to section 8.10 and figure 8-2, transition 2 in [01-PL Spec] on page 60 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case is skipped in case the local wake-up is not implemented.
5.3.7.19.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: none.
5.3.7.19.3 Preamble (setup state) • Standby preamble.
5.3.7.19.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
5.3.7.19.5 Postamble • Standard postamble.
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5.3.7.19.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • The error signal shall be LOW at the host interface of node 24 after the wake-up event is detected.In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state.
5.3.7.19.7 Test Instances Instance 5.3.7.19 5.3.7.20 5.3.7.21
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Gground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.22 to 5.3.7.24: Operation mode change from BD_Standby to BD_Standby due to local wake-up (positive pulse)
5.3.7.22.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_Standby due to a local wake-up event according to section 8.10 and figure 8-2, transition 2 in [01-PL Spec] on page 60 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or an optional positive pulse by a local wake-up is not provided by the IUT. This test case is skipped in case the local wake-up is not implemented.
5.3.7.22.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: none.
5.3.7.22.3 Preamble (setup state) • Standby preamble. Hint: set uWAKE to logical LOW before the IUT is set to BD_Standby .
5.3.7.22.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
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5.3.7.22.5 Postamble • Standard postamble.
5.3.7.22.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • The error signal shall be LOW at the host interface of node 24 after the wake-up event is detected.In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state.
5.3.7.22.7 Test Instances Instance 5.3.7.22 5.3.7.23 5.3.7.24
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.25 to 5.3.7.27: Insufficient local wake-up
5.3.7.25.1 Test Purpose This test checks the ability of the IUT to reject spikes on the WAKE pin and to stay in BD_Standby mode if the wake-pulse width is insufficient according to section 8.10 in [01-PL Spec] on page 60 while no other stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case is skipped in case the local wake-up is not implemented.
5.3.7.25.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: none.
5.3.7.25.3 Preamble (setup state) • Standby preamble.
5.3.7.25.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 1µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
5.3.7.25.5 Postamble • Standard postamble.
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5.3.7.25.6 Pass- / Fail Criteria Hint: due to dStarWakeUpReaction the observed signals shall be observed and aquired at least for 100ms. Pass criteria: • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • uRxD of node 24 shall be in logical HIGH state during test execution. • The error signal shall be HIGH at the host interface of node 24 after the wake-up event is sent.In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
5.3.7.25.7 Test Instances Instance 5.3.7.25 5.3.7.26 5.3.7.27
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.28 to 5.3.7.30: Operation mode change from BD_Normal to
BD_Standby due to undervoltage of VCC
5.3.7.28.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Normal mode to BD_Standby in case of an undervoltage on V CC according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-PL
Spec] on page 39 while VBAT is implemented and no other stress condition is present.
In case of a missing V BAT supply input, see test case 5.3.14.1 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.7.28.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.28.3 Preamble (setup state) • Standard preamble.
5.3.7.28.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V CC power supply of IUT in node 24 to VCCUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.28.5 Postamble • Standard postamble.
5.3.7.28.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.7.28.7 Test Instances Instance 5.3.7.28 5.3.7.29 5.3.7.30
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.31 to 5.3.7.32: Operation mode change from BD_Normal to
BD_Standby due to undervoltage of VIO
5.3.7.31.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Normal mode to BD_Standby in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is implemented, see test case 5.3.9.8 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented or the Functional class “Bus Driver Logic Level Adaptation” is not implemented.
5.3.7.31.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.31.3 Preamble (setup state) • Standard preamble.
5.3.7.31.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Set external V IO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.31.5 Postamble • Standard postamble.
5.3.7.31.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.7.31.7 Test Instances Instance 5.3.7.31 5.3.7.32
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.33 to 5.3.7.35: Operation mode change from BD_ReceiveOnly to
BD_Standby due to undervoltage of VCC
5.3.7.33.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_ReceiveOnly mode to BD_Standby in case of an undervoltage on V CC according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-
PL Spec] on page 39 while VBAT is implemented and no other stress condition is present.
In case of a missing V BAT supply input, see test case 5.3.14.3 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the BD_ReceiveOnly mode is not implemented or the Functional class
“Bus Driver Internal Voltage Regulator” is implemented and a V CC supply input is not available.
5.3.7.33.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.33.3 Preamble (setup state) • ReceiveOnly preamble. • Stimulate IUT in node 23 via host interface to enter BD_Normal .
5.3.7.33.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V CC power supply of IUT in node 24 to VCCUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.33.5 Postamble • Standard postamble.
5.3.7.33.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.7.33.7 Test Instances Instance 5.3.7.33 5.3.7.34 5.3.7.35
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.36 to 5.3.7.37: Operation mode change from BD_ReceiveOnly to
BD_Standby due to undervoltage of VIO
5.3.7.36.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_ReceiveOnly mode to BD_Standby in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01- PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is implemented, see test case 5.3.9.11 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented or if the Functional class “Bus Driver Logic Level Adaptation” or the BD_ReceiveOnly mode is not implemented.
5.3.7.36.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.36.3 Preamble (setup state) • ReceiveOnly preamble. • Stimulate IUT in node 23 via host interface to enter BD_Normal .
5.3.7.36.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Set external VIO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.36.5 Postamble • Standard postamble.
5.3.7.36.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.7.36.7 Test Instances Instance 5.3.7.36 5.3.7.37
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.38 to 5.3.7.40: Operation mode change from BD_Standby to
BD_Standby due to undervoltage of VCC
5.3.7.38.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Standby mode to BD_Standby in case of an undervoltage on V CC according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 2 in [01-PL
Spec] on page 39 while VBAT is implemented and no other stress condition is present.
In case of a missing V BAT supply input, see test case 5.3.14.2 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.7.38.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.38.3 Preamble (setup state) • Standby preamble. • Stimulate IUT in node 23 via host interface to enter BD_Normal .
5.3.7.38.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V CC power supply of IUT in node 24 to VCCUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.38.5 Postamble • Standard postamble.
5.3.7.38.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • No error shall be signaled via the host interface of node 24, because in a low operation mode no undervoltage detection is required. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.7.38.7 Test Instances Instance 5.3.7.38 5.3.7.39 5.3.7.40
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.41 to 5.3.7.42: Operation mode change from BD_Standby to
BD_Standby due to undervoltage of VIO
5.3.7.41.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Standby mode to BD_Standby in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 2 in [01-PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is implemented, see test case 5.3.9.19 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented or if the Functional class “Bus Driver Logic Level Adaptation” is not implemented.
5.3.7.41.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.41.3 Preamble (setup state) • Standby preamble. • Stimulate IUT in node 23 via host interface to enter BD_Normal .
5.3.7.41.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Set external V IO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.41.5 Postamble • Standard postamble.
5.3.7.41.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • An error shall be signaled via the host interface of node 24. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.7.41.7 Test Instances Instance 5.3.7.41 5.3.7.42
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.43 to 5.3.7.45: IUT enter BD_Standby (power on event)
5.3.7.43.1 Test Purpose This test checks the behaviour and the ability of the IUT to enter BD_Standby in case of a power on event according to section 8.3.1.1 in [01-PL Spec] while no stress condition is present.
5.3.7.43.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 and 23 as transmitter.
5.3.7.43.3 Preamble (setup state) • Standard preamble. • Disable outputs of external power supplies of IUT in node 24. • If host interface option A is implemented: o Switch STBN signal of node 24 and all available mode control signals (EN) to unconnected. This is to make the IUTs state independent from a host command. • If host interface option B is implemented: o Do not send any host command to the IUT during test execution.
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5.3.7.43.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Enable power supplies of IUT in node 24. • After the maximal wake-up detection time of 100ms, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until end of scope observation window, i.e. 5.0µs. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by two 50/50 patterns.
5.3.7.43.5 Postamble • Standard postamble.
5.3.7.43.6 Pass- / Fail Criteria Pass criteria: Hint: Power on wake-up detection timeout measurement requires a trigger event when voltages at the IUTs supply inputs have raised to sufficient values. Adaptation of thresholds for digital signals may be required. • After the maximal wake-up detection time of 100ms, the error signal of node 24 shall be in logical HIGH state. Subsequently, no wake-up indication shall be signaled via the host interface of node 24. • uRxD of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution, i.e. bus activity must not be detected as wake-up event. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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• In case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state after the maximal wake-up detection time of 100ms.
5.3.7.43.7 Test Instances Instance 5.3.7.43 5.3.7.44 5.3.7.45
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply External V BAT @ n24 = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.46 to 5.3.7.48: IUT remain in BD_Standby (RWU violation)
5.3.7.46.1 Test Purpose This test checks the ability of the IUT to ignore non suitable remote wake-up (RWU) patterns with shorted idle phase and to remain in BD_Standby mode according to section 8.11 in [01-PL Spec] on page 60 while no stress condition is present. This test case is skipped in case the remote wake-up is not implemented.
5.3.7.46.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V IO is implemented:
o VIO power supply of all nodes: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: Node 23 as transmitter.
5.3.7.46.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby .
5.3.7.46.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one non wake-up short idle phase pattern as specified in chapter 5.1.3.10.
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5.3.7.46.5 Postamble • Standard postamble.
5.3.7.46.6 Pass- / Fail Criteria Pass criteria: Hint: the observation shall be at least 100ms, because the IUT may wake-up within this time. • In case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution, i.e. node 24 shall remain in BD_Standby . • uRxD of node 24 shall be in logical HIGH state during test execution. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution. • The error signal shall be HIGH at the host interface of node 24 after the wake-up event is sent.Test Instances Instance 5.3.7.46 5.3.7.47 5.3.7.48
Purpose Purpose IUT shall ignore non IUT shall ignore non IUT shall ignore non suitable remote wake- suitable remote wake- suitable prolonged up patterns with up patterns with remote wake-up shorted idle phase shorted low phase patterns
Stress
Precondition
Configuration Power Supply
Ground Shift
Failure
Preamble
Test Execution Stimulate IUT in n23 at Stimulate IUT in n23 at TP_N23_TxD and TP_N23_TxD and TP_N23_TxEN by one TP_N23_TxEN by one non wake-up short low non wake-up phase pattern as prolonged pattern as specified in chapter specified in chapter 5.1.3.11 5.1.3.12
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.49 to 5.3.7.51: RWU detection while undervoltage conditions
5.3.7.49.1 Test Purpose
This test checks the ability of the IUT to detect a remote wake-up (RWU) when V CC and V IO are concurrently in undervoltage conditions according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2, transition 1 in [01-PL Spec] on page 39. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not
implemented or the V CC supply input is not available. This test case is skipped in case the remote wake-up is not implemented.
5.3.7.49.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V.
• Failure: V CC and V IO in undervoltage condition. • Communication: node 23 as transmitter.
5.3.7.49.3 Preamble (setup state) • Sleep preamble. • Stimulate IUT in node 23 via host interface to enter BD_Normal .
• Switch V CC and V IO of node 24 to external power supplies and set uV CC =VCCUndervoltage and uV IO =VIOUndervoltage .
5.3.7.49.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 23. • Observe and acquire the error signal of the host interface ( TP_Nx_ERRN or TP_Nx_INTN ) of all nodes. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern.
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5.3.7.49.5 Postamble • Standard postamble.
5.3.7.49.6 Pass- / Fail Criteria Pass criteria: • uINH1 of all observed nodes shall be in logical LOW state (Sleep ) before the transmission start of the wake-up pattern, i.e. the first falling edge of uTxD or uTxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uINH1 of all observed nodes shall be in logical HIGH state (Not_Sleep ), i.e. the IUTs are in BD_Standby mode. • No error shall be signaled via the host interface of node 23. • An error shall be signaled via the host interface of node 24 after under- voltage is detected.The error signal shall be LOW at the host interface of all nodes except nodes 23 and 24 after the wake-up is detected.
5.3.7.49.7 Test Instances Instance 5.3.7.49 5.3.7.50 5.3.7.51
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply External V BAT @ all
nodes = +7.0V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.52 to 5.3.7.54: LWU detection (negative pulse) while undervoltage conditions
5.3.7.52.1 Test Purpose This test checks the ability of the IUT to detect a negative local wake-up (LWU) pulse when V CC and V IO concurrently in undervoltage conditions according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2, transition 1 in [01-PL Spec] on page 39. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not implemented or the V CC supply input is not available. This test case is skipped in case the local wake-up is not implemented.
5.3.7.52.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V.
• Failure: V CC and V IO in undervoltage condition. • Communication: none.
5.3.7.52.3 Preamble (setup state) • Sleep preamble.
• Switch V CC and V IO of node 24 to external power supplies and set uV CC =VCCUndervoltage and uV IO =VIOUndervoltage .
5.3.7.52.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
5.3.7.52.5 Postamble • Standard postamble.
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5.3.7.52.6 Pass- / Fail Criteria Pass criteria: • uINH1 shall be in logical LOW state (Sleep ) while the IUT of node 24 is in BD_Sleep mode, before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state (BD_Standby : Not_Sleep ). • The error signal shall be LOW at the host interface of node 24 after undervoltage is detected. Test Instances Instance 5.3.7.52 5.3.7.53 5.3.7.54
Purpose Stress Ground Shift low battery
Precondition BD_VRC implemented
Configuration Power Supply External V BAT @ all
nodes = +7.0V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.7.55 to 5.3.7.57: LWU detection (positive pulse) while undervoltage conditions
5.3.7.55.1 Test Purpose This test checks the ability of the IUT to detect a positive local wake-up (LWU) pulse when V CC and V IO concurrently in undervoltage conditions according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2, transition 1 in [01-PL Spec] on page 39. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not implemented or the Functional class “Bus Driver Logic Level Adaptation” is implemented and the V CC supply input is not available. This test case is skipped in case a positive local wake-up pulse is not implemented.
5.3.7.55.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V.
• Failure: V CC and V IO in undervoltage condition. • Communication: none.
5.3.7.55.3 Preamble (setup state) • Sleep preamble.
• Switch V CC and V IO of node 24 to external power supplies and set uV CC =VCCUndervoltage and uV IO =VIOUndervoltage . Hint: set uWAKE to logical LOW before the IUT is set to BD_Sleep .
5.3.7.55.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
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5.3.7.55.5 Postamble • Standard postamble.
5.3.7.55.6 Pass- / Fail Criteria Pass criteria: • uINH1 shall be in logical LOW state (Sleep ) while the IUT of node 24 is in BD_Sleep mode, before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state (BD_Standby : Not_Sleep ). • The error signal shall be LOW at the host interface of node 24 after undervoltage is detected. Test Instances Instance 5.3.7.55 5.3.7.56 5.3.7.57
Purpose Stress Ground Shift low battery
Precondition BD_VRC implemented
Configuration Power Supply External V BAT @ all
nodes = +7.0V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.8 Mode.Bus Driver.Normal
5.3.8.1 to 5.3.8.3: Operation mode change from BD_Standby to BD_Normal due to host command
5.3.8.1.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_Normal due to host command according to figure 8-2, transition number 11 in [01-PL Spec] while no stress condition is present.
5.3.8.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.8.1.3 Preamble (setup state) • Standby preamble.
5.3.8.1.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes. • Stimulate IUTs in all nodes via host interface to enter BD_Normal .
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• Stimulate IUT in the first transmitting node according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.8.1.5 Postamble • Standard postamble.
5.3.8.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes shall contain all 50/50 patterns transmitted at uTxD and uTxEN of all nodes except the patterns transmitted by the specific node itself, i.e. all transmitted data shall be received by all receiving nodes (loopback functionality not mandatory). • in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH state ( Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of all nodes shall be in logical HIGH state before the first node according to the sequence described on matrix A is stimulated (falling edge of uTxD and uTxEN ) and shall be in logical LOW state while uRxD of the corresponding node signals the received patterns.
5.3.8.1.7 Test Instances Instance 5.3.8.1 5.3.8.2 5.3.8.3
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.8.4 to 5.3.8.6: Operation mode change from BD_Sleep to BD_Normal due to host command
5.3.8.4.1 Test Purpose This test checks the ability of the IUT to change from BD_Sleep mode to BD_Normal due to host command according to figure 8-2, transition number 8 in [01-PL Spec] while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.8.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 and node 1 as transmitter.
5.3.8.4.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep .
5.3.8.4.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uSTBN or uSCSN at TP_N24_STBN or TP_N24_SCSN of node 24.
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• Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT in node 24 via host interface to enter BD_Normal . • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.8.4.5 Postamble • Standard postamble.
5.3.8.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before this node is stimulated to transmit, i.e. until the first falling edge of uTxD and uTxEN of node 24. • uRxD of all nodes shall contain all 50/50 patterns transmitted at uTxD and uTxEN of node 24 and node 1 except the patterns transmitted by the specific node itself, i.e. all transmitted data shall be received by all receiving nodes (loopback functionality not mandatory). • in BD_Normal state, uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ). • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before this node is stimulated to transmit, i.e. until the first falling edge of uTxD and uTxEN of node 24. Then, uRxEN of node 24 shall be in logical LOW state while uRxD of node 24 signals the received patterns.
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5.3.8.4.7 Test Instances Instance 5.3.8.4 5.3.8.5 5.3.8.6
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.8.7 to 5.3.8.9: Operation mode change from BD_ReceiveOnly to BD_Normal due to host command
5.3.8.7.1 Test Purpose This test checks the ability of the IUT to change from BD_ReceiveOnly mode to BD_Normal due to host command according to figure 8-2, transition number 6 in [01- PL Spec] while no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.8.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.8.7.3 Preamble (setup state) • ReceiveOnly preamble.
5.3.8.7.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes. • Stimulate IUTs in all nodes via host interface to enter BD_Normal .
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• Stimulate IUT in the first transmitting node according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate IUTs in transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.8.7.5 Postamble • Standard postamble.
5.3.8.7.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes shall contain all 50/50 patterns transmitted at uTxD and uTxEN of all nodes except the patterns transmitted by the specific node itself, i.e. all transmitted data shall be received by all receiving nodes (loopback functionality not mandatory). • in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of all nodes shall be in logical HIGH state before the first node according to the sequence described on matrix A is stimulated (falling edge of uTxD and uTxEN ) and shall be in logical LOW state while uRxD of the corresponding node signals the received patterns.
5.3.8.7.7 Test Instances Instance 5.3.8.7 5.3.8.8 5.3.8.9
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9 Mode.Bus Driver.Low Power.Sleep
5.3.9.1 to 5.3.9.3: Operation mode change from BD_Normal to BD_Sleep due to host command
5.3.9.1.1 Test Purpose This test checks the ability of the IUT to change from BD_Normal mode to BD_Sleep due to host command according to figure 8-2, transition number 9 in [01-PL Spec] while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.9.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.9.1.3 Preamble (setup state) • Standard preamble.
5.3.9.1.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uSTBN or uSCSN at TP_Nx_STBN or TP_Nx_SCSN of all nodes. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Stimulate IUTs in all nodes via host interface to enter BD_Sleep .
5.3.9.1.5 Postamble • Standard postamble.
5.3.9.1.6 Pass- / Fail Criteria Pass criteria: • uINH1 of all nodes shall be in logical HIGH state ( Not_Sleep ) gefore this node is stimulated via host interface (falling edge at uSTBN or at uSCSN ) to enter BD_Sleep mode. After stimulation, uINH1 shall be in logical LOW state (Sleep ). • uRxD of node 24 shall be in logical HIGH state during test execution. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
5.3.9.1.7 Test Instances Instance 5.3.9.1 5.3.9.2 5.3.9.3
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.4 to 5.3.9.5: Operation mode change from BD_Normal to
BD_Sleep due to undervoltage of VBAT
5.3.9.4.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Normal mode to BD_Sleep in case of an undervoltage on V BAT according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-PL
Spec] on page 39 while VCC is implemented and no other stress condition is present.
In case of a missing V CC supply input, see test case 5.3.13.1 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.9.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT and V CC supplies:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.4.3 Preamble (setup state) • Standard preamble.
5.3.9.4.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.4.5 Postamble • Standard postamble.
5.3.9.4.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution. • uINH1 of node 24 shall be in logical LOW state (Sleep ) not later than 1000ms after undervoltage is present. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ). • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.9.4.7 Test Instances Instance 5.3.9.4 5.3.9.5
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.6 to 5.3.9.7: Operation mode change from BD_ReceiveOnly to
BD_Sleep due to undervoltage of VBAT
5.3.9.6.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_ReceiveOnly mode to BD_Sleep in case of an undervoltage on V BAT according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-
PL Spec] on page 39 while VCC is implemented and no other stress condition is present.
In case of a missing V CC supply input, see test case 5.3.13.3 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the BD_ReceiveOnly mode is not implemented or the Functional class
“Bus Driver Internal Voltage Regulator” is implemented and a V CC supply input is not available.
5.3.9.6.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT and V CC supplies:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.6.3 Preamble (setup state) • ReceiveOnly preamble.
5.3.9.6.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24.
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• Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.6.5 Postamble • Standard postamble.
5.3.9.6.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution. • uINH1 of node 24 shall be in logical LOW state ( Sleep ) not later than 1000ms after undervoltage is present. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ). • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.9.6.7 Test Instances Instance 5.3.9.6 5.3.9.7
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.8 to 5.3.9.10: Operation mode change from BD_Normal to
BD_Sleep due to undervoltage of VIO
5.3.9.8.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Normal mode to BD_Sleep in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is not implemented, see test case 5.3.7.31 (the IUT shall then change to BD_Standby ) and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not implemented.
5.3.9.8.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External VCC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.8.3 Preamble (setup state) • Standard preamble.
5.3.9.8.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24 • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
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• Set external V IO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.8.5 Postamble • Standard postamble.
5.3.9.8.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • uINH1 of node 24 shall be in logical LOW state (Sleep ) not later than 1000ms after undervoltage is present. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.9.8.7 Test Instances Instance 5.3.9.8 5.3.9.9 5.3.9.10
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24 -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.11 to 5.3.9.13: Operation mode change from BD_ReceiveOnly to
BD_Sleep due to undervoltage of V IO
5.3.9.11.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_ReceiveOnly mode to BD_Sleep in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 3 in [01-PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is not implemented, see test case 5.3.7.36 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” or the BD_ReceiveOnly mode is not implemented.
5.3.9.11.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.11.3 Preamble (setup state) • ReceiveOnly preamble.
5.3.9.11.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
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• Set external V IO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.11.5 Postamble • Standard postamble.
5.3.9.11.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • uINH1 of node 24 shall be in logical LOW state ( Sleep ) not later than 1000ms after undervoltage is present. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.9.11.7 Test Instances Instance 5.3.9.11 5.3.9.12 5.3.9.13
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.14 to 5.3.9.16: Operation mode change from BD_Standby to BD_Sleep due to host command
5.3.9.14.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_Sleep due to host command according to figure 8-2, transition number 12 in [01- PL Spec] while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.9.14.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.9.14.3 Preamble (setup state) • Standby preamble.
5.3.9.14.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uSTBN or uSCSN at TP_Nx_STBN or TP_Nx_SCSN of all nodes. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUTs in all nodes via host interface to enter BD_Sleep .
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5.3.9.14.5 Postamble • Standard postamble.
5.3.9.14.6 Pass- / Fail Criteria Pass criteria: • uINH1 of all nodes shall be in logical HIGH state (Not_Sleep ) before this node is stimulated via host interface (falling edge at uSTBN or at uSCSN ) to enter BD_Sleep mode. After stimulation, uINH1 shall change to logical LOW state (Sleep ). • uRxD of node 24 shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
5.3.9.14.7 Test Instances Instance 5.3.9.14 5.3.9.15 5.3.9.16
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.17 to 5.3.9.18: Operation mode change from BD_Standby to
BD_Sleep due to undervoltage of V BAT
5.3.9.17.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Standby mode to BD_Sleep in case of an undervoltage on V BAT according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 12 in [01-
PL Spec] on page 39 while VCC is implemented and no other stress condition is present.
In case of a missing V CC supply input, see test case 5.3.13.2 and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.9.17.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT and V CC supplies:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.17.3 Preamble (setup state) • Standby preamble.
5.3.9.17.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uRxD at TP_N24_RxD of node 24.
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• Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.17.5 Postamble • Standard postamble.
5.3.9.17.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of node 24 shall be in logical HIGH state during test execution. • uINH1 of node 24 shall be in logical LOW state ( Sleep ) not later than 1000ms after undervoltage is present. • No error shall be signaled via the host interface of node 24, because the IUT is in a low operation mode. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ). • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.9.17.7 Test Instances Instance 5.3.9.17 5.3.9.18
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.19 to 5.3.9.21: Operation mode change from BD_Standby to
BD_Sleep due to undervoltage of VIO
5.3.9.19.1 Test Purpose This test checks the fail silent behaviour and the ability of the IUT to change from
BD_Standby mode to BD_Sleep in case of an undervoltage on V IO according to section 8.7 in [01-PL Spec] on page 46 and figure 8-2, transition number 12 in [01- PL Spec] on page 39 while no other stress condition is present. If the BD_Sleep mode is not implemented, see test case 5.3.7.41 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not implemented.
5.3.9.19.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.19.3 Preamble (setup state) • Standby preamble.
5.3.9.19.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
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• Set external V IO power supply of IUT in node 24 to VIOUndervoltage . • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window.
5.3.9.19.5 Postamble • Standard postamble.
5.3.9.19.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . Adaptation of thresholds for digital signals may be required. • uINH1 of node 24 shall be in logical LOW state ( Sleep ) not later than 1000ms after undervoltage is present. • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is present. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
5.3.9.19.7 Test Instances Instance 5.3.9.19 5.3.9.20 5.3.9.21
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.22 to 5.3.9.24: Insufficient wake-up pulse
5.3.9.22.1 Test Purpose This test checks the ability of the IUT to reject spikes on the WAKE pin and to stay in BD_Sleep mode if the wake-pulse width is insufficient according to section 8.10 in [01-PL Spec] on page 60 while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.9.22.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.9.22.3 Preamble (setup state) • Sleep preamble.
5.3.9.22.4 Test execution • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 1µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec].
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5.3.9.22.5 Postamble • Standard postamble.
5.3.9.22.6 Pass- / Fail Criteria Hint: due to the possibility to wake-up the duration of the observation shall be at least 500µs. Pass criteria: • uINH1 shall be in logical LOW state (Sleep ) during test execution. • uRxD of node 24 shall be in logical HIGH state during test execution. • no error shall be signaled via the host interface of node 24, i.e. no wake-up was detected. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
5.3.9.22.7 Test Instances Instance 5.3.9.22 5.3.9.23 5.3.9.24
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.25 to 5.3.9.27: IUT remain in BD_Sleep (RWU violation)
5.3.9.25.1 Test Purpose This test checks the ability of the IUT to ignore non suitable remote wake-up patterns with shortend idle phase and to remain in BD_Sleep mode according to section 8.11 in [01-PL Spec] on page 60 while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.9.25.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes except node 24: +5.0V.
o External VCC power supply of node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• In case that V IO is implemented:
o VIO power supply of all nodes except node 24: depends on implementation.
o External VIO power supply of node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: Node 23 as transmitter.
5.3.9.25.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep .
5.3.9.25.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one non wake-up short idle phase pattern as specified in chapter 5.1.3.10.
5.3.9.25.5 Postamble • Standard postamble.
5.3.9.25.6 Pass- / Fail Criteria Pass criteria: Hint: the observation shall be at least 100ms, because the IUT may wake-up within this time. • uINH1 of node 24 shall be in logical LOW state (Sleep ) during test execution, i.e. node 24 shall remain in BD_Sleep . • uRxD of node 24 shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution. • no error shall be signaled via the host interface of node 24, i.e. no wake-up was detected.
5.3.9.25.7 Test Instances Instance 5.3.9.25 5.3.9.26 5.3.9.27
Purpose Purpose IUT shall ignore non IUT shall ignore non IUT shall ignore non suitable remote wake- suitable remote wake- suitable prolonged up patterns with up patterns with remote wake-up shortend idle phase shortend low phase patterns
Stress
Precondition
Configuration Power Supply
Ground Shift
Failure
Preamble
Test Execution Stimulate IUT in n23 at Stimulate IUT in n 23 TP_N23_TxD and at TP_N23_TxD and TP_N23_TxEN by one TP_N23_TxEN by one non wake-up short low non wake-up phase pattern as prolonged pattern as specified in chapter specified in chapter 5.1.3.11 5.1.3.12
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.28 to 5.3.9.30: Operation mode change from BD_Normal to
BD_Standby to BD_Sleep due to undervoltage of VCC & V IO
5.3.9.28.1 Test Purpose This test checks the ability of the IUT to change from BD_Normal to BD_Standby
and then to BD_Sleep mode while first V CC is in undervoltage condition and then V IO is in undervoltage condition according to section 8.3 in [01-PL Spec] on page 39 while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator
Control” or the “Bus Driver Logic Level Adaptation” or the V CC supply input is not implemented.
5.3.9.28.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External VCC power supply of node 24: +5.0V.
• VIO power supply of all nodes: depends on implementation.
• External VIO power supply of node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.9.28.3 Preamble (setup state) • Standard preamble.
5.3.9.28.4 Test execution • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uBus at TP4_N23 of node 23. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Set external V CC power supply of the IUT in node 24 to VCCUndervoltage . • Wait 1000ms.
• Set external V IO power supply of the IUT in node 24 to VIOUndervoltage . • Wait 1000ms. • After the detection of the undervoltage condition by the IUT, i.e. after the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit Low pattern followed by
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one 10Bit High pattern followed by one 10Bit Low pattern. Repeat this sequence. • Trigger the scope to start observation one second after the undervoltage in VCC . • Wait until the end of the scope observation window.
5.3.9.28.5 Postamble • Standard postamble.
5.3.9.28.6 Pass- / Fail Criteria Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . Adaptation of thresholds for digital signals may be required. Pass criteria: • uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) before detecting the V IO undervoltage, i.e. node 24 shall change from BD_Normal to BD_Standby . After detecting the V IO undervoltage uINH1 of node 24 shall be in logical LOW state (Sleep ) until the end of the test execution, i.e. node 24 shall enter in BD_Sleep . • An error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage in V CC is present. The error signal shall remain in logical LOW until the end of the test execution. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning one second after undervoltage in V CC . The absolute bus voltage shall not exceed 30mV ( uBDTxidle ).
5.3.9.28.7 Test Instances Instance 5.3.9.28 5.3.9.29 5.3.9.30
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.9.31 to 5.3.9.33: IUT remain in BD_Sleep while EN is high
5.3.9.31.1 Test Purpose This test checks the ability of the IUT to remain BD_Sleep mode while EN is set to high by the host according to section 8.6 in [01-PL Spec] on page 43 while no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the EN signal input is not implemented.
5.3.9.31.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External VCC power supply of node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• In case that V IO is implemented:
o VIO power supply of all nodes: depends on implementation.
o External VIO power supply of node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.9.31.3 Preamble (setup state) • Sleep preamble.
5.3.9.31.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uSTBN or uSCSN at TP_Nx_STBN or TP_Nx_SCSN of all nodes. • Observe and acquire uEN at TP_Nx_EN of all nodes. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate the host interface of node 24 to switch the IUT to BD_Standby , i.e. the STBN and EN signals of node 24 shall be both LOW. • Wait 100ms.
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5.3.9.31.5 Postamble • Standard postamble.
5.3.9.31.6 Pass- / Fail Criteria Pass criteria: • uINH1 of all nodes shall be in logical LOW state ( Sleep ) during the whole test execution, i.e. the IUT shall not leave the BD_Sleep mode. • uRxD of node 24 shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
5.3.9.31.7 Test Instances Instance 5.3.9.31 5.3.9.32 5.3.9.33
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10 Mode.Bus Driver.ReceiveOnly
5.3.10.1 to 5.3.10.3: Operation mode change from BD_Normal to BD_ReceiveOnly due to host command
5.3.10.1.1 Test Purpose This test checks the ability of the IUT to change from BD_Normal mode to BD_ReceiveOnly due to host command according to figure 8-2, transition number 7 in [01-PL Spec] while no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.10.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.10.1.3 Preamble (setup state) • Standard preamble.
5.3.10.1.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes.
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• Stimulate IUTs in all nodes except node 24 via host interface to enter BD_ReceiveOnly . The IUT in node 24 remains in BD_Normal . • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.10.1.5 Postamble • Standard postamble.
5.3.10.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall not contain any 50/50 pattern transmitted at uTxD and uTxEN of all other nodes, i.e. the IUTs in all nodes except node 24 shall not transmit any data while in BD_ReceiveOnly mode. • uRxD of all nodes except node 24 shall contain the 50/50 pattern transmitted at uTxD and uTxEN of node 24, i.e. the IUTs in all nodes except node 24 shall receive data while in BD_ReceiveOnly mode. • in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH state ( Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of all nodes shall be in logical HIGH state before the IUT in node 24 is stimulated to transmit (falling edge of uTxD and uTxEN of node 24) and shall be in logical LOW state while the signal uRxD of the corresponding node signals the received pattern.
5.3.10.1.7 Test Instances Instance 5.3.10.1 5.3.10.2 5.3.10.3
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.4 to 5.3.10.6: Operation mode change from BD_Standby to BD_ReceiveOnly due to host command
5.3.10.4.1 Test Purpose This test checks the ability of the IUT to change from BD_Standby mode to BD_ReceiveOnly due to host command according to figure 8-2, transition number 4 in [01-PL Spec] while no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.10.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.10.4.3 Preamble (setup state) • Standby preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.10.4.4 Test execution Hint: the observation shall start 1000µs after the host command is applied. • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire the error signal of the host interface ( TP_Nx_ERRN or TP_Nx_INTN ) of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • In case of an available RxEN signal observe and acquire uRxEN at TP_Nx_RxEN of all nodes.
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• Stimulate IUTs in all nodes except node 24 via host interface to enter BD_ReceiveOnly . The IUT in node 24 remains in BD_Normal . • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.10.4.5 Postamble • Standard postamble.
5.3.10.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall not contain any 50/50 pattern transmitted at uTxD and uTxEN of all other nodes, i.e. the IUTs in all nodes except node 24 shall not transmit any data while in BD_ReceiveOnly mode. • uRxD of all nodes except node 24 shall contain the 50/50 pattern transmitted at uTxD and uTxEN of node 24, i.e. the IUTs in all nodes except node 24 shall receive data while in BD_ReceiveOnly mode. • in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH state ( Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of all nodes shall be in logical HIGH state before the IUT in node 24 is stimulated to transmit (falling edge of uTxD and uTxEN of node 24) and shall be in logical LOW state while the signal uRxD of the corresponding node signals the received pattern. • no error shall be signaled via the host interfaces of all nodes.
5.3.10.4.7 Test Instances Instance 5.3.10.4 5.3.10.5 5.3.10.6
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.7 to 5.3.10.9: Wake-up source indication (RWU, initial operation mode is BD_Sleep )
5.3.10.7.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a remote wake-up (RWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the EN signal at the hard-wired host interface is not implemented. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.10.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.10.7.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.7.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.7.5 Postamble • Standard postamble.
5.3.10.7.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • In case of an available RxEN signal uRxEN of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ), i.e. the IUT is in BD_Standby mode. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical LOW state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.7.7 Test Instances Instance 5.3.10.7 5.3.10.8 5.3.10.9
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 202 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.10 to 5.3.10.12: Wake-up source indication (LWU, negative pulse, initial operation mode is BD_Sleep )
5.3.10.10.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (negative pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.10.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.10.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.10.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.10.5 Postamble • Standard postamble.
5.3.10.10.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) while the IUT of node 24 is in BD_Sleep mode before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ). • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.10.7 Test Instances Instance 5.3.10.10 5.3.10.11 5.3.10.12
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 205 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.13 to 5.3.10.15: Wake-up source indication (LWU, positive pulse, initial operation mode is BD_Sleep )
5.3.10.13.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (positive pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the local wake-up (positive pulse) is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.13.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.13.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.13.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.13.5 Postamble • Standard postamble.
5.3.10.13.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) while the IUT of node 24 is in BD_Sleep mode before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ). • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.13.7 Test Instances Instance 5.3.10.13 5.3.10.14 5.3.10.15
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 208 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.16 to 5.3.10.18: Wake-up source indication (RWU, initial operation mode is BD_Standby )
5.3.10.16.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a remote wake-up (RWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.16.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.10.16.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.16.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.16.5 Postamble • Standard postamble.
5.3.10.16.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical LOW state between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • In case of an available RxEN signal uRxEN of node 24 shall be in logical LOW state between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during the test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical LOW state 1ms after entering the BD_ReceiveOnly mode.
5.3.10.16.7 Test Instances Instance 5.3.10.16 5.3.10.17 5.3.10.18
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 210 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers 5.3.10.19 to 5.3.10.21: Wake-up source indication (LWU, negative pulse, initial operation mode is BD_Standby )
5.3.10.19.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (negative pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.19.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.19.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.19.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.19.5 Postamble • Standard postamble.
5.3.10.19.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during the test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.19.7 Test Instances Instance 5.3.10.19 5.3.10.20 5.3.10.21
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 213 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.22 to 5.3.10.24: Wake-up source indication (LWU, positive pulse, initial operation mode is BD_Standby )
5.3.10.22.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (positive pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and no stress condition is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the local wake-up (positive pulse) is not implemented.
5.3.10.22.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.22.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.22.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.22.5 Postamble • Standard postamble.
5.3.10.22.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during the test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.22.7 Test Instances Instance 5.3.10.22 5.3.10.23 5.3.10.24
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 216 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.25 to 5.3.10.27: Wake-up source indication (LWU, negative pulse, initial operation mode is BD_Standby , active failure)
5.3.10.25.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (negative pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 while an active failure in BD_ReceiveOnly mode is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.25.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.25.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.25.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal . • Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL4. • Wait 15000µs.
5.3.10.25.5 Postamble • Standard postamble.
5.3.10.25.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • uINH1 shall be in logical LOW state (Sleep) while the IUT of node 24 is in BD_Sleep mode before the falling edge of uWAKE. After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ). • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.25.7 Test Instances Instance 5.3.10.25 5.3.10.26 5.3.10.27
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 219 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.28 to 5.3.10.30: Wake-up source indication (LWU, positive pulse, initial operation mode is BD_Sleep , active failure)
5.3.10.28.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (positive pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 while an active failure in BD_ReceiveOnly mode is present. This test case is skipped if the BD_ReceiveOnly mode is not implemented or the EN signal at the host interface is not implemented or the local wake-up (positive pulse) is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.10.28.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.28.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.28.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24.
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• Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal . • Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL4. • Wait 15000µs.
5.3.10.28.5 Postamble • Standard postamble.
5.3.10.28.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • uINH1 shall be in logical LOW state (Sleep) while the IUT of node 24 is in BD_Sleep mode before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ). • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.28.7 Test Instances Instance 5.3.10.28 5.3.10.29 5.3.10.30
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.31 to 5.3.10.33: No wake-up source indication after passing BD_Normal (RWU, initial operation mode is BD_Standby )
5.3.10.31.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a remote wake-up (RWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the remote wake-up or the BD_ReceiveOnly mode is not implemented.
5.3.10.31.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.10.31.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.31.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.31.5 Postamble • Standard postamble.
5.3.10.31.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • In case of an available RxEN signal uRxEN of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.31.7 Test Instances Instance 5.3.10.31 5.3.10.32 5.3.10.33
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.34 to 5.3.10.36: No wake-up source indication after passing BD_Normal (LWU, negative pulse, initial operation mode is BD_Standby )
5.3.10.34.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (negative pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the local wake- up or the BD_ReceiveOnly mode is not implemented.
5.3.10.34.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.34.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.34.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.34.5 Postamble • Standard postamble.
5.3.10.34.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.34.7 Test Instances Instance 5.3.10.34 5.3.10.35 5.3.10.36
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 228 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.37 to 5.3.10.39: No wake-up source indication after passing BD_Normal (LWU, positive pulse, initial operation mode is BD_Standby )
5.3.10.37.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (positive pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the local wake- up or the BD_ReceiveOnly mode is not implemented.
5.3.10.37.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.37.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.37.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.37.5 Postamble • Standard postamble.
5.3.10.37.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.37.7 Test Instances Instance 5.3.10.37 5.3.10.38 5.3.10.39
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.40 to 5.3.10.42: No wake-up source indication after passing BD_Normal (RWU, initial operation mode is BD_Sleep )
5.3.10.40.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a remote wake-up (RWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the remote wake-up or the BD_ReceiveOnly mode is not implemented.
5.3.10.40.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
5.3.10.40.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.40.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT of node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.40.5 Postamble • Standard postamble.
5.3.10.40.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • In case of an available RxEN signal uRxEN of node 24 shall be in logical LOW between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ), i.e. the IUT is in BD_Standby mode. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the transmission start of the wake-up pattern, i.e. the first falling edge of TxD or TxEN of node 23. After the wake-up event is detected (between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.40.7 Test Instances Instance 5.3.10.40 5.3.10.41 5.3.10.42
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 234 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.43 to 5.3.10.45: No wake-up source indication after passing BD_Normal (LWU, negative pulse, initial operation mode is BD_Sleep )
5.3.10.43.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the local wake- up or the BD_ReceiveOnly mode is not implemented.
5.3.10.43.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.43.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.43.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.43.5 Postamble • Standard postamble.
5.3.10.43.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) while the IUT of node 24 is in BD_Sleep mode before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ). • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.43.7 Test Instances Instance 5.3.10.43 5.3.10.44 5.3.10.45
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
Version 2.1 Revision B June 2008 Page 237 of 553 FlexRay Physical Layer Conformance Test Specification Test Cases for Bus Drivers
5.3.10.46 to 5.3.10.48: No wake-up source indication after passing BD_Normal (LWU, positive pulse, initial operation mode is BD_Sleep )
5.3.10.46.1 Test Purpose This test checks the ability of the IUT not to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 and entering BD_Normal mode while no stress condition is present. This test case is skipped if the Functional Class "Bus Driver Voltage Regulator Control" or the EN signal at the host interface is not implemented or the local wake- up or the BD_ReceiveOnly mode is not implemented.
5.3.10.46.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.46.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Sleep . The IUTs of all other nodes remain in BD_Normal .
5.3.10.46.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ Normal . • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal .
5.3.10.46.5 Postamble • Standard postamble.
5.3.10.46.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical LOW state ( Sleep ) while the IUT of node 24 is in BD_Sleep mode before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uINH1 shall be in logical HIGH state ( Not_Sleep ) • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_Normal mode.
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5.3.10.46.7 Test Instances Instance 5.3.10.46 5.3.10.47 5.3.10.48
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.49 to 5.3.10.51: Wake-up source indication with active failure (LWU, negative pulse, initial operation mode is BD_Standby )
5.3.10.49.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up (LWU) event (negative pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 while an active failure in BD_ReceiveOnly mode is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or EN signal at the hard-wired host interface is not implemented or the BD_ReceiveOnly mode is not implemented.
5.3.10.49.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.49.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.49.4 Test execution • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical LOW to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal . • Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL4. • Wait 15000µs.
5.3.10.49.5 Postamble • Standard postamble.
5.3.10.49.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during the test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the falling edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.49.7 Test Instances Instance 5.3.10.49 5.3.10.50 5.3.10.51
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.10.52 to 5.3.10.55: Wake-up source indication with active failure (LWU, positive pulse, initial operation mode is BD_Standby )
5.3.10.52.1 Test Purpose This test checks the ability of the IUT to signal the wake-up source while the IUT is in BD_ReceiveOnly mode after a local wake-up event (positive pulse) according to section 8.11 on page 60 in [01-PL Spec] and figure 8-2 while an active failure in BD_ReceiveOnly mode is present. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or EN signal at the hard-wired host interface is not implemented or the BD_ReceiveOnly mode is not implemented or the local wake-up (positive pulse) is not implemented.
5.3.10.52.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: none.
5.3.10.52.3 Preamble (setup state) • Standard preamble. • Stimulate IUT in node 24 via host interface to enter BD_Standby . The IUTs of all other nodes remain in BD_Normal .
5.3.10.52.4 Test execution • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uSTBN at TP_N24_STBN of node 24. • Observe and acquire uEN at TP_N24_EN of node 24. • Observe and acquire uWAKE at TP_N24_WAKE of node 24. • Observe and acquire the error signal of the host interface (TP_N24_ERRN ) of node 24.
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• Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Apply a wake-up pulse of 500µs logical HIGH to the IUT in node 24 at TP_N24_WAKE according to dWakePulseFilter in [01-PL Spec]. • Wait 100ms. • Stimulate IUT in node 24 via host interface to enter BD_ReceiveOnly . The IUTs of all other nodes remain in BD_Normal . • Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL4. • Wait 15000µs.
5.3.10.52.5 Postamble • Standard postamble.
5.3.10.52.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxD of node 24 shall be in logical LOW state. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the rising edge of uWAKE. After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), uRxEN of node 24 shall be in logical LOW state. • INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during the test execution. • The ERRN signal uERRN of node 24 shall be in logical HIGH state before the rising edge of uWAKE . After the wake-up event is detected (between 1µs after the beginning of the local wake-up event and 500µs after the beginning of the local wake-up event), ERRN of node 24 shall be in logical LOW state. ERRN shall be in logical HIGH state 1ms after entering the BD_ReceiveOnly mode.
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5.3.10.52.7 Test Instances Instance 5.3.10.52 5.3.10.53 5.3.10.54
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.11 Failure.Loss
5.3.11.1 Failure: STBN unconnected
5.3.11.1.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected STBN signal according to table 8-28 in [01-PL Spec]. This test case is skipped if the STBN signal (host interface option A) is not implemented. This test case considers only the BD_Normal mode.
5.3.11.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: STBN unconnected. • Communication: node 24 and 1 as transmitter.
5.3.11.1.3 Preamble (setup state) • Standard preamble. • Switch STBN signal of node 24 to unconnected according to Figure 3-5 and Table 3-4, failure FL9 and all available mode control signals (EN) to logical LOW state.
5.3.11.1.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes.
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• Observe and acquire the error signal of the host interface (TP_N24_ERRN or TP_N24_INTN) of node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by two wake-up patterns. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by two wake-up patterns.
5.3.11.1.5 Postamble • Standard postamble.
5.3.11.1.6 Pass- / Fail Criteria Hint: due to dWakeUpReaction the observed signals shall be observed and aquired at least for 100ms. Pass criteria: • uRxD of all nodes shall be in logical HIGH state while the IUT in node 24 is stimulated to transmit (while uTxEN of node 24 is in logical LOW), i.e. the IUT in node 24 shall not transmit any pattern in BD_Standby mode. • uRxD of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxD of node 24 shall be in logical LOW state. • in case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxEN of node 24 shall be in logical LOW state. • The error signal at the host interface of node 24 shall be in logical HIGH state before the first falling edge of uTxD and uTxEN of node 1. After the wake-up event is detected, the error signal shall be in logical LOW state.
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5.3.11.2 Failure: EN unconnected
5.3.11.2.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected EN signal according to table 8-28 in [01-PL Spec]. This test case is skipped if the host interface option A is not implemented or the Functional class “Bus Driver Voltage Regulator Control” is not implemented. This test case considers only the BD_Normal mode.
5.3.11.2.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: EN unconnected. • Communication: node 24 and 1 as transmitter.
5.3.11.2.3 Preamble (setup state) • Standard preamble. • Switch EN signal of node 24 to unconnected according to Figure 3-5 and Table 3-4, failure FL18 and all other available mode control signals (EN) and STBN to logical LOW state.
5.3.11.2.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire the error signal of the host interface (TP_N24_ERRN or TP_N24_INTN) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by two wake-up patterns. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by two wake-up patterns.
5.3.11.2.5 Postamble • Standard postamble.
5.3.11.2.6 Pass- / Fail Criteria Hint: due to dWakeUpReaction the observed signals shall be observed and aquired at least for 100ms. Pass criteria: • uRxD of all nodes shall be in logical HIGH state while the IUT in node 24 is stimulated to transmit (while uTxEN of node 24 is in logical LOW), i.e. the IUT in node 24 shall not transmit any pattern in BD_Standby mode. • uRxD of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxD of node 24 shall be in logical LOW state. • uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. After the wake-up event is detected, uRxEN of node 24 shall be in logical LOW state. • The error signal at the host interface of node 24 shall be in logical HIGH state before the first falling edge of uTxD and uTxEN of node 1. After the wake-up event is detected, the error signal shall be in logical LOW state.
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5.3.11.3 Failure: TxEN unconnected
5.3.11.3.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected TxEN signal according to table 8-28 and table 8-27 in [01-PL Spec]. This test case considers only the BD_Normal mode.
5.3.11.3.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: TxEN unconnected. • Communication: node 24 and 1 as transmitter.
5.3.11.3.3 Preamble (setup state) • Standard preamble. • Switch TxEN signal of node 24 to unconnected according to Figure 3-5 and Table 3-4, failure FL5.
5.3.11.3.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
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• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.11.3.5 Postamble • Standard postamble.
5.3.11.3.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes shall be in logical HIGH state while the IUT in node 24 is stimulated to transmit, i.e. the IUT in node 24 shall be fail silent while TxEN is unconnected. • uRxD of node 24 shall contain the 50/50 pattern transmitted by node 1. • in case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. Then, uRxEN of node 24 shall be in logical LOW state while uRxD of node 24 signals the received patterns.
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5.3.11.4 Failure: TxD unconnected
5.3.11.4.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected TxD signal according to table 8-28 and table 8-27 in [01-PL Spec]. This test case considers only the BD_Normal mode.
5.3.11.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: TxD unconnected. • Communication: node 24 and 1 as transmitter.
5.3.11.4.3 Preamble (setup state) • Standard preamble. • Switch TxD signal of node 24 to unconnected according to Figure 3-5 and Table 3-4, failure FL6.
5.3.11.4.4 Test execution • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24.
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• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.11.4.5 Postamble • Standard postamble.
5.3.11.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes except node 24 shall contain a logical LOW state sequence of at least 11 bit times after the IUT in node 24 starts TSS pattern transmission (corresponding falling edge of uTxEN of node 24), i.e. the IUT in node 24 reads TxD as logical LOW state while TxD is unconnected. • uRxD of node 24 shall contain the 50/50 pattern transmitted by node 1. • in case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • in case of an available RxEN signal uRxEN of node 24 shall be in logical LOW state while uRxD of node 24 signals the received patterns. • no error shall be signaled via the host interface of node 24.
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5.3.11.5 Failure: BGE unconnected
5.3.11.5.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected BGE signal according to table 8-28 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver – Bus Guardian Control Interface” is not implemented. This test case considers only the BD_Normal mode.
5.3.11.5.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: BGE unconnected. • Communication: node 24 and 1 as transmitter.
5.3.11.5.3 Preamble (setup state) • Standard preamble. • Switch BGE signal of node 24 to unconnected according to Figure 3-5 and Table 3-4, failure FL10.
5.3.11.5.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxEN at TP_N24_RxEN of node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24.
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• Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
5.3.11.5.5 Postamble • Standard postamble.
5.3.11.5.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes shall be in logical HIGH state while the IUT in node 24 is stimulated to transmit, i.e. the IUT in node 24 shall be fail silent while BGE is unconnected. • uRxD of node 24 shall contain the 50/50 pattern transmitted by node 1. • uRxEN of node 24 shall be in logical HIGH state before the first falling edge of uTxD or uTxEN of node 1. Then, uRxEN of node 24 shall be in logical LOW state while uRxD of node 24 signals the received patterns. • in case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution.
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5.3.11.6 Failure: VBAT interrupted, V CC implemented
5.3.11.6.1 Test Purpose
This test checks the behaviour of the IUT in case of an interruption of V BAT according to table 8-10 and table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.6.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V.
• Failure: V BAT interrupted. • Communication: none.
5.3.11.6.3 Preamble (setup state) • Standard preamble.
• Interrupt supply wire V BAT of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL1.
5.3.11.6.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.6.5 Postamble • Standard postamble.
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5.3.11.6.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state during test execution. • uINH1 of node 24 shall be in logical LOW state (Sleep ) during test execution. • an error shall be signaled via the host interface of node 24. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.11.7 Failure: VBAT interrupted, V CC not implemented
5.3.11.7.1 Test Purpose
This test checks the behaviour of the IUT in case of an interruption of V BAT according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Internal Voltage Regulator” is not implemented and a V CC supply input is although available.
5.3.11.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation. • Ground shift: 0V.
• Failure: V BAT interrupted. • Communication: none.
5.3.11.7.3 Preamble (setup state) • Standard preamble.
• Interrupt supply wire V BAT of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL1.
5.3.11.7.4 Test execution • Observe and acquire the error signal of the host interface (TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.7.5 Postamble • Standard postamble.
5.3.11.7.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical LOW state during test execution. • an error shall be signaled via the host interface of node 24.
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5.3.11.8 Failure: VCC interrupted, V BAT implemented
5.3.11.8.1 Test Purpose
This test checks the behaviour of the IUT in case of an interruption of V CC according to table 8-10 and table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.8.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V CC interrupted. • Communication: none.
5.3.11.8.3 Preamble (setup state) • Standard preamble.
• Interrupt supply wire V CC of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL2.
5.3.11.8.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.8.5 Postamble • Standard postamble.
5.3.11.8.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state during test execution.
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• uINH1 of node 24 shall be in logical HIGH state (Not_Sleep ) during test execution. • an error shall be signaled via the host interface of node 24. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.11.9 Failure: VCC interrupted, V BAT not implemented
5.3.11.9.1 Test Purpose
This test checks the behaviour of the IUT in case of an interruption of V CC according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented.
5.3.11.9.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V CC interrupted. • Communication: none.
5.3.11.9.3 Preamble (setup state) • Standard preamble.
• Interrupt supply wire V CC of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL2.
5.3.11.9.4 Test execution • Observe and acquire the error signal of the host interface (TP_N24_ERRN or TP_N24_INTN ) of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.9.5 Postamble • Standard postamble.
5.3.11.9.6 Pass- / Fail Criteria Pass criteria: • An error shall be signaled via the host interface of node 24, i.e. ERRN or INTN shall go to LOW latest 1000ms after VCC undervoltage has been detected by the IUT.
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5.3.11.10 Failure: VBAT and V CC interrupted
5.3.11.10.1 Test Purpose
This test checks the behaviour of the IUT in case of an interruption of V BAT and VCC supply input according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.10.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V BAT and V CC interrupted. • Communication: none.
5.3.11.10.3 Preamble (setup state) • Standard preamble.
• Interrupt supply wires V BAT and V CC of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL3.
5.3.11.10.4 Test execution • Observe and acquire the error signal of the host interface (TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.10.5 Postamble • Standard postamble.
5.3.11.10.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical LOW state during test execution. • an error shall be signaled via the host interface of node 24.
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5.3.11.11 Failure: GND unconnected
5.3.11.11.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected GND connection of the IUT according to table 8-27 in [01-PL Spec].
5.3.11.11.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: GND of IUT unconnected. • Communication: node 23 as transmitter.
5.3.11.11.3 Preamble (setup state) • Standard preamble. • Switch GND connection of IUT in node 23 to unconnected according to Figure 3-9 and Table 3-4, failure FL15.
5.3.11.11.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uBus at TP1_N23 of node 23 according to the observation window described in chapter 5.1.4.2. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern. Hint: The observation window for the scope shall be 5µs. The trigger of the oscilloscope shall be 52µs after the first falling edge of N23_TxEN .
5.3.11.11.5 Postamble • Standard postamble.
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5.3.11.11.6 Pass- / Fail Criteria Pass criteria: • the differential bus voltage at TP1_N23 of node 23 shall be | uBus |≤30mV during the observation window in the test execution.
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5.3.11.12 Failure: V BAT =0V, V CC implemented
5.3.11.12.1 Test Purpose
This test checks the behaviour of the IUT in case of V BAT =0V according to table 8-10 and table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available
5.3.11.12.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V.
• Failure: V BAT =0V according to Figure 3-5 and Table 3-4, failure FL22. • Communication: none.
5.3.11.12.3 Preamble (setup state) • Standard preamble.
• Set supply V BAT of the IUT in node 24 to 0V.
5.3.11.12.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.12.5 Postamble • Standard postamble.
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5.3.11.12.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state during test execution. • uINH1 of node 24 shall be in logical LOW state ( Sleep ) during test execution. • an error shall be signaled via the host interface of node 24. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.11.13 Failure: V BAT =0V, V CC not implemented
5.3.11.13.1 Test Purpose
This test checks the behaviour of the IUT in case of V BAT =0V according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Internal Voltage Regulator” is not implemented and a V CC supply input is although available.
5.3.11.13.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation. • Ground shift: 0V.
• Failure: V BAT =0V according to Figure 3-5 and Table 3-4, failure FL22. • Communication: none.
5.3.11.13.3 Preamble (setup state) • Standard preamble.
• Set supply V BAT of the IUT in node 24 to 0V.
5.3.11.13.4 Test execution • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.13.5 Postamble • Standard postamble.
5.3.11.13.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical LOW state during test execution. • an error shall be signaled via the host interface of node 24.
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5.3.11.14 Failure: V CC =0V, V BAT implemented
5.3.11.14.1 Test Purpose
This test checks the behaviour of the IUT in case of V CC =0V according to table 8-10 and table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.14.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V CC =0V according to Figure 3-5 and Table 3-4, failure FL23. • Communication: none.
5.3.11.14.3 Preamble (setup state) • Standard preamble.
• Set supply V CC of the IUT in node 24 to 0V.
5.3.11.14.4 Test execution • Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.14.5 Postamble • Standard postamble.
5.3.11.14.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 24 shall be in logical HIGH state during test execution.
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• uINH1 of node 24 shall be in logical HIGH state ( Not_Sleep ) during test execution. • an error shall be signaled via the host interface of node 24. • in case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.11.15 Failure: V CC =0V, V BAT not implemented
5.3.11.15.1 Test Purpose
This test checks the behaviour of the IUT in case of V CC =0V according to table 8-27 in [01-PL Spec]. This test case must be skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.15.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V CC =0V according to Figure 3-5 and Table 3-4, failure FL23. • Communication: none.
5.3.11.15.3 Preamble (setup state) • Standard preamble.
• Set supply V CC of the IUT in node 24 to 0V.
5.3.11.15.4 Test execution • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.15.5 Postamble • Standard postamble.
5.3.11.15.6 Pass- / Fail Criteria Pass criteria: • An error shall be signaled via the host interface of node 24, i.e. ERRN or INTN shall go to LOW latest 1000ms after VCC undervoltage has been detected by the IUT.
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5.3.11.16 Failure: V BAT =0V and V CC =0V
5.3.11.16.1 Test Purpose
This test checks the behaviour of the IUT in case of V BAT =0V and VCC =0V supply input according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.11.16.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V.
• Failure: V BAT =0V and V CC =0V according to Figure 3-5 and Table 3-4, failure FL24 . • Communication: none.
5.3.11.16.3 Preamble (setup state) • Standard preamble.
• Set supplies V BAT =0V and V CC =0V of the IUT in node 24.
5.3.11.16.4 Test execution • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uINH1 at TP_N24_INH1 of node 24. Hint: The duration of the observation and aquisition shall be at least 100 samples for each signal.
5.3.11.16.5 Postamble • Standard postamble.
5.3.11.16.6 Pass- / Fail Criteria Pass criteria: • uINH1 of node 24 shall be in logical LOW state during test execution. • an error shall be signaled via the host interface of node 24.
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5.3.12 Failure.Short Circuits
5.3.12.1 TxEN shorted to GND
5.3.12.1.1 Test Purpose This test checks the behaviour of the IUT when TxEN is shorted to GND according to table 8-27 in [01-PL Spec].
5.3.12.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: short circuit of TxEN and GND. • Communication: node 24 as transmitter.
5.3.12.1.3 Preamble (setup state) • Standard preamble.
5.3.12.1.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_N23_RxD of node 23. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • In case of an available INH1 signal observe and acquire uINH1 at TP_N24_INH1 of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Short-circuit TxEN and GND of the IUT in node 24 according to Figure 3-5 and Table 3-4, failure FL4. • Beginning with the falling edge of uTxEN of node 24, stimulate IUT in node 24 at TP_N24_TxD by a logical LOW state sequence of at least 15000µs.
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5.3.12.1.5 Postamble • Standard postamble.
5.3.12.1.6 Pass- / Fail Criteria Pass criteria: Hint: For BranchActive timeout measurement, a trigger event on the falling edge of uTxEN is required. • uRxD of node 23 shall be in logical HIGH state before the falling edge of uTxD of node 24. After the falling edge of uTxEN of node 24, uRxD of node 23 shall receive the logical LOW sequence applied to TxD of node 24 until the IUT of node 24 enters Fail Silent mode after at least 1500µs and not more than 15000µs of transmission. Thus, uRxD of node 23 shall return to logical HIGH state not later than 15000µs after the falling edge of uTxEN of node 24 • An error shall be signaled via the host interface of node 24 not earlier than 1500µs and not later than 15000µs after the falling edge of uTxEN of node 24. • In case of an available INH1 signal uINH1 of node 24 shall be in logical HIGH state during the test execution. • In case of an available RxEN signal uRxEN of node 24 shall be in logical HIGH state during test execution.
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5.3.13 Power Supply.Undervoltage V BAT
5.3.13.1 Undervoltage of V BAT , VCC = not implemented, occuring in BD_Normal mode
5.3.13.1.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V BAT occurring in BD_Normal mode if V CC is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V CC supply input, see test case 5.3.9.4 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is not implemented and if a V CC supply input is although available.
5.3.13.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• External V BAT power supply of IUT in node 24: default
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.13.1.3 Preamble (setup state) • Standard preamble.
5.3.13.1.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
5.3.13.1.5 Postamble • Standard postamble.
5.3.13.1.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . • An error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is applied. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.13.2 Undervoltage of V BAT , VCC = not implemented, occuring in BD_Standby mode
5.3.13.2.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V BAT occurring in BD_Standby mode if V CC is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V CC supply input, see test case 5.3.9.17 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is not implemented and if a V CC supply input is although available.
5.3.13.2.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• External V BAT power supply of IUT in node 24: default.
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.13.2.3 Preamble (setup state) • Standby preamble.
5.3.13.2.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the undervoltage reaction time, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24.
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• Wait until the end of the scope observation window, i.e. 5µs.
5.3.13.2.5 Postamble • Standard postamble.
5.3.13.2.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . • No error shall be signaled via the host interface of node 24 during the test execution signaling that no wake-up was received according tables 8-8 and 8-9 in [01-PL Spec]. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.13.3 Undervoltage of V BAT, VCC = not implemented, occuring in BD_ReceiveOnly mode
5.3.13.3.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V BAT occurring in BD_ReceiveOnly mode if V CC is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V CC supply input, see test case 5.3.9.6 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is not implemented and if a V CC supply input is although available, or the BD_ReceiveOnly mode is not implemented.
5.3.13.3.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• External V BAT power supply of IUT in node 24: default.
• VIO power supply:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.13.3.3 Preamble (setup state) • ReceiveOnly preamble.
5.3.13.3.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage . • After the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
5.3.13.3.5 Postamble • Standard postamble.
5.3.13.3.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage . • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is applied. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.13.4 Undervoltage of V BAT , occuring in BD_Sleep mode
5.3.13.4.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V BAT occurring in BD_Sleep mode if no other stress condition is present according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.13.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 24: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.13.4.3 Preamble (setup state) • Sleep preamble.
5.3.13.4.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V BAT power supply of the IUT in node 24 to VBATUndervoltage .
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• After the undervoltage event, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
5.3.13.4.5 Postamble • Standard postamble.
5.3.13.4.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs supply input has dropped to VBATUndervoltage. • No error shall be signaled via the host interface of node 24 during the test execution, i.e. no wake-up was received. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.14 Power Supply.Undervoltage V CC
5.3.14.1 Undervoltage of VCC , V BAT not implemented, occuring in BD_Normal mode
5.3.14.1.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V CC occurring in BD_Normal mode if V BAT is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V BAT supply input, see test case 5.3.7.28 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented.
5.3.14.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.14.1.3 Preamble (setup state) • Standard preamble.
5.3.14.1.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V CC power supply of the IUT in node 24 to VBATUndervoltage . • After the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
5.3.14.1.5 Postamble • Standard postamble.
5.3.14.1.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VBATUndervoltage . • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is applied. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.14.2 Undervoltage of V CC , V BAT = not implemented, occuring in BD_Standby mode
5.3.14.2.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V CC occurring in BD_Standby mode if V BAT is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V BAT supply input, see test case 5.3.7.38 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented.
5.3.14.2.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.14.2.3 Preamble (setup state) • Standby preamble.
5.3.14.2.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V CC power supply of the IUT in node 24 to VCCUndervoltage . • After the undervoltage reaction time, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
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5.3.14.2.5 Postamble • Standard postamble.
5.3.14.2.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . • No error shall be signaled via the host interface of node 24 during the test execution signaling that no wake-up was received according tables 8-8 and 8-9 in [01-PL Spec]. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.14.3 Undervoltage of V CC , V BAT = not implemented, occuring in BD_ReceiveOnly mode
5.3.14.3.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V CC occurring in BD_ReceiveOnly mode if V BAT is not implemented and no other stress condition is present according to table 8-27 in [01-PL Spec].
In case of an available V BAT supply input, see test case 5.3.7.33 and following and skip this test case. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is implemented, or the BD_ReceiveOnly mode is not implemented.
5.3.14.3.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.14.3.3 Preamble (setup state) • ReceiveOnly preamble.
5.3.14.3.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V CC power supply of the IUT in node 24 to VCCUndervoltage . • After the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
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5.3.14.3.5 Postamble • Standard postamble.
5.3.14.3.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is applied. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.14.4 Undervoltage of V CC , occuring in BD_Sleep mode
5.3.14.4.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V CC occurring in BD_Sleep mode if no other stress condition is present according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented or the Functional class “Bus Driver Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
5.3.14.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.14.4.3 Preamble (setup state) • Sleep preamble.
5.3.14.4.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V CC power supply of the IUT in node 24 to VCCUndervoltage . • After the undervoltage reaction time, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24. • Wait until the end of the scope observation window, i.e. 5µs.
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5.3.14.4.5 Postamble • Standard postamble.
5.3.14.4.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs supply input has dropped to VCCUndervoltage . • No error shall be signaled via the host interface of node 24 during the test execution, i.e. no wake-up was received. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.15 Power Supply.Undervoltage V IO
5.3.15.1 Undervoltage of V IO in BD_Sleep mode
5.3.15.1.1 Test Purpose This test checks the behaviour of the IUT under the fault condition of an undervoltage of V IO occurring in BD_Sleep mode if no other stress condition is present according to table 8-27 in [01-PL Spec]. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” or the Functional class “Bus Driver Logic Level Adaptation” is not implemented.
5.3.15.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes: depends on implementation.
• External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: node 24 as transmitter.
5.3.15.1.3 Preamble (setup state) • Sleep preamble.
5.3.15.1.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Observe and acquire uBus at TP4_N23 of node 23 according to the observation window described in chapter 5.1.4.2.
• Set external V IO power supply of the IUT in node 24 to VIOUndervoltage . • After the falling edge of the error signal of node 24, stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one 10Bit High pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N24_TxEN of node 24.
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5.3.15.1.5 Postamble • Standard postamble.
5.3.15.1.6 Pass- / Fail Criteria Pass criteria:
Hint: Undervoltage detection timeout measurement requires a trigger event when V IO voltage at the IUTs supply input has dropped to VIOUndervoltage . • an error shall be signaled via the host interface of node 24 not later than 1000ms after undervoltage is applied. • uBus at TP4_N23 of node 23 shall stay within idle range during the observation window, beginning with the falling edge of uTxEN of node 24. The absolute bus voltage shall not exceed 30mV ( uBDTx idle ).
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5.3.16 Dynamic Low Battery Voltage
5.3.16.1 to 5.3.16.2: Dynamic low battery occuring in BD_Normal mode
5.3.16.1.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in BD_Normal mode. Hint: This test case intends to test the capability of the bus driver to return to the operating state that was active before the dynamic low battery pulse. This test case
is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC (and if implemented V IO ) voltage regulator (the battery voltage of the ECU) is stressed by the dynamic low battery voltage pulse.
5.3.16.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: 11.6V.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: 11.6V.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
• Test signal: U S/t f1 as specified in chapter 3.4.
5.3.16.1.3 Preamble (setup state) • Standard preamble.
5.3.16.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern,
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followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
5.3.16.1.5 Postamble • Standard postamble.
5.3.16.1.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC and V IO voltage regulator is present: o uRxD of all nodes except the corresponding transmitting node shall contain all 50/50 patterns transmitted by all nodes (according to uTxD and uTxEN of all nodes), i.e. all data shall be transmitted and received by the IUTs in all nodes. o in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH.
5.3.16.1.7 Test Instances Instance 5.3.16.1 5.3.16.2
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.16.3 to 5.3.16.4: Dynamic low battery occuring in BD_Standby mode
5.3.16.3.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in BD_Standby mode. Hint: This test case intends to test the capability of the bus driver to return to the operating state that was active before the dynamic low battery pulse. This test case
is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC (and if implemented V IO ) voltage regulator (the battery voltage of the ECU) is stressed by the dynamic low battery voltage pulse.
5.3.16.3.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A.
• Test signal: U S/t f1 as specified in chapter 3.4.
5.3.16.3.3 Preamble (setup state) • Standby preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
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5.3.16.3.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
5.3.16.3.5 Postamble • Standard postamble.
5.3.16.3.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC and V IO voltage regulator is present: o uRxD of node 24 shall not contain any pattern of any other node, i.e. nothing is transmitted by the IUTs of all nodes except node 24. o uRxD of all nodes except node 24 shall not contain any pattern of node 24, i.e. the IUTs in all nodes except node 24 shall not receive any data. o in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH.
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5.3.16.3.7 Test Instances Instance 5.3.16.3 5.3.16.4
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.16.5 to 5.3.16.6: Dynamic low battery occuring in BD_Sleep mode
5.3.16.5.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in BD_Sleep mode. Hint: This test case intends to test the capability of the bus driver to return to the operating state that was active before the dynamic low battery pulse. The input voltage of the optional VCC or V IO voltage regulator (the battery voltage of the ECU) is stressed by the dynamic low battery voltage pulse, when implemented. This test case is skipped if the Functional class “Bus Driver Voltage Regulator Control” is not implemented.
5.3.16.5.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A.
• Test signal: U S/t f1 as specified in chapter 3.4.
5.3.16.5.3 Preamble (setup state) • Sleep preamble. • Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.16.5.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes.
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• Observe and acquire uRxD at TP_N24_RxD of node 24. • Observe and acquire uINH1 at TP_Nx_INH1 of all nodes except node 24. • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
5.3.16.5.5 Postamble • Standard postamble.
5.3.16.5.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC and V IO voltage regulator is present: o uRxD of node 24 shall contain no pattern of any other node, i.e. nothing shall be transmitted by any IUT of all nodes except node 24. o uINH1 of all nodes except node 24 shall be in logical LOW.
5.3.16.5.7 Test Instances Instance 5.3.16.5 5.3.16.6
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.16.7 to 5.3.16.8: Dynamic low battery occuring in BD_ReceiveOnly mode
5.3.16.7.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in BD_ReceiveOnly mode. Hint: This test case intends to test the capability of the bus driver to return to the operating state that was active before the dynamic low battery pulse. This test case is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC (and if implemented V IO ) voltage regulator (the battery voltage of the ECU) is stressed by the dynamic low battery voltage pulse. This test case is skipped if the BD_ReceiveOnly mode is not implemented.
5.3.16.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of node 24: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes except node 24: 11.6V.
o External V BAT power supply of node 24: default.
• VIO power supply (in case of an available V IO supply input):
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 24: depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A.
• Test signal: U S/t f1 as specified in chapter 3.4.
5.3.16.7.3 Preamble (setup state) • ReceiveOnly preamble.
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• Stimulate IUT in node 24 via host interface to enter BD_Normal .
5.3.16.7.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_Nx_INH1 of all nodes. • Stimulate IUTs of transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
5.3.16.7.5 Postamble • Standard postamble.
5.3.16.7.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC and V IO voltage regulator is present: o uRxD of all nodes except node 24 shall contain the 50/50 patterns transmitted by node 24 (according to uTxD and uTxEN of node 24), i.e. all data transmitted shall be received by the IUTs in BD_ReceiveOnly mode. o uRxD of node 24 shall contain no pattern of any other node, i.e. nothing shall be retransmitted by any IUT in BD_ReceiveOnly mode. o in case of an available INH1 signal uINH1 of all nodes shall be in logical HIGH.
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5.3.16.7.7 Test Instances Instance 5.3.16.7 5.3.16.8
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.17 Communication.Timing.Masks
5.3.17.1 to 5.3.17.3: Path asymmetry dPathAsym
5.3.17.1.1 Test Purpose This test checks the network parameter dPathAsym of the overall physical layer if no stress condition is present according to the timing constraints chapter 12 in [01-PL Spec]. This test shall verify, that a protocol controller would decode the information transmitted properly.
5.3.17.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.17.1.3 Preamble (setup state) • Standard preamble.
5.3.17.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Stimulate IUT in the first transmitting node according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate IUTs in transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern, followed by one 10Bit High pattern.
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5.3.17.1.5 Postamble • Standard postamble.
5.3.17.1.6 Pass- / Fail Criteria Pass criteria: • the length of all received 10Bit Low patterns in uRxD of all nodes shall be equal to the length of the 10Bit Low pattern in uTxD of the corresponding transmitting node -30.75ns/+43.23ns, i.e. the signal path asymmetry shall be within the allowed range, according to chapter 5.1.16.
5.3.17.1.7 Test Instances Instance 5.3.17.1 5.3.17.2 5.3.17.3
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.18 Communication.Truncation
5.3.18.1 to 5.3.18.3: Path truncation
5.3.18.1.1 Test Purpose This test checks the overall channel truncation if no stress condition is present according to the sum of all allowed truncation effects specified in [01-PL Spec]. This test shall verify, that only the transmission start sequence is affected by truncation effects and that a protocol controller would decode the following data properly.
5.3.18.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
5.3.18.1.3 Preamble (setup state) • Standard preamble.
5.3.18.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Stimulate IUT in the first transmitting node according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate IUTs in transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 10/90 pattern.
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5.3.18.1.5 Postamble • Standard postamble.
5.3.18.1.6 Pass- / Fail Criteria Pass criteria: • the width of all received TSS patterns (logical LOW phase from the falling edge of the received TSS pattern to the rising edge of the first bit of the following 10/90 pattern) in uRxD of all nodes except the corresponding transmitting node shall be at least 100ns, i.e. the channel truncation shall be within the allowed range.
5.3.18.1.7 Test Instances Instance 5.3.18.1 5.3.18.2 5.3.18.3
Purpose Stress none ground shift low battery
Precondition BD_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ N24
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.19 Failure.Short Circuit Bus Wires
5.3.19.1 to 5.3.19.2: Short circuit bus wires to GND
5.3.19.1.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to GND. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
5.3.19.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to GND. • Communication: Node 24 and 23 as transmitter.
5.3.19.1.3 Preamble (setup state) • Standard preamble. • Short circuit BP (failure FL11) of node 24 to GND at TP2_N24 .
5.3.19.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23.
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• Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire uRxD at TP_N23_RxD of node 23. • In case of an available RxEN signal observe and acquire uRxEN at TP_N23_RxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Observe and acquire iBP GNDShortMax at TP_N24_RiBP of node 24 (shall be at TP1_N24 ). • Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by a short circuit current measurement pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples where taken by the data acquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 24. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL11) of node 24. Wait at least 12 seconds. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.19.1.5 Postamble • Standard postamble.
5.3.19.1.6 Pass- / Fail Criteria Pass criteria:
• |iBP GNDShortMax | ≤ 100mA. • The IUT of node 24 shall signal an error to the host after detecting the failure. • After switching off the failure: o uRxD of the IUT in node 24 must receive the patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23 and signal them at TP_N24_RxD accordingly. o uRxD of the IUT in node 23 must receive the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 23 and signal them at TP_N23_RxD accordingly.
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o In case of an available RxEN signal uRxEN at TP_N24_RxEN of the IUT in node 24 must be in logical LOW state while receiving the patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23 o In case of an available RxEN signal uRxEN at TP_N23_RxEN of the IUT in node 23 must be in logical LOW state while receiving the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 24
5.3.19.1.7 Test Instances Instance 5.3.19.1 5.3.19.2
Purpose Stress S/C BP to GND at node 24 S/C BM to GND at node 24
Precondition
Configuration Power Supply
Ground Shift
Failure S/C BP to GND S/C BM to GND
Preamble Standard Standard Short circuit BP (failure FL11) of Short circuit BM (failure FL12) of node 24 to GND at TP2_N24 . node 24 to GND at TP2_N24
Test Execution … …
Observe and acquire iBP GNDShortMax Observe and acquire iBMGNDShortMax
at TP_N24_R iBP of node 24 (shall at TP_N24_R iBM of node 24 (shall be at TP1_N24 ). be at TP1_N24 ).
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL11) of node 24. Wait at least 12 FL12) of node 24. Wait at least 12 seconds. seconds
… …
Pass/Fail Criteria |iBP GNDShortMax | ≤ 100mA. |iBM GNDShortMax | ≤ 100mA. … … █ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.19.3 to 5.3.19.4: Short circuit bus wires to V BAT
5.3.19.3.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to +48V 25 . Additionally it is checked that the IUT is not permanently damaged by the short circuit.
5.3.19.3.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only VCC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to +48V 25 . • Communication: Node 24 and 23 as transmitter.
5.3.19.3.3 Preamble (setup state) • Standard preamble. • Short circuit BP (failure FL13) of node 24 to +48V25 at TP2_N24 .
5.3.19.3.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24.
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• Observe and acquire uRxD at TP_N23_RxD of node 23. • In case of an available RxEN signal observe and acquire uRxEN at TP_N23_RxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. 26 27 • Observe and acquire iBP BAT48ShortMax or iBP BAT27ShortMax at TP_N24_RiBP of node 24 (shall be at TP1_N24 ). • Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by a short circuit current measurement pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples where taken by the data acquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 24. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL13) of node 24. Wait at least 12 seconds. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.19.3.5 Postamble • Standard postamble.
5.3.19.3.6 Pass- / Fail Criteria Pass criteria:
• In case the IUT does not support 42V systems: |iBP BAT27ShortMax | ≤ 100mA.
• In case the IUT does support 42V systems: |iBP BAT48ShortMax | ≤ 120mA. • The IUT of node 24 shall signal an error to the host after detecting the failure. • After switching off the failure: o uRxD of the IUT in node 24 must receive the patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23 and signal them at TP_N24_RxD accordingly. o uRxD of the IUT in node 23 must receive the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 23 and signal them at TP_N23_RxD accordingly. o In case of an available RxEN signal uRxEN at TP_N24_RxEN of the IUT in node 24 must be in logical LOW state while receiving the
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patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23. o In case of an available RxEN signal uRxEN at TP_N23_RxEN of the IUT in node 23 must be in logical LOW state while receiving the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 24.
5.3.19.3.7 Test Instances Instance 5.3.19.3 5.3.19.4
Purpose Stress S/C BP to V BAT at node 24 S/C BM to V BAT at node 24
Precondition
Configuration Power Supply
Ground Shift
Failure S/C BP to +48V 25 S/C BM to +48V 25
Preamble Standard. Standard. Short circuit BP (failure FL13) of node Short circuit BM (failure FL14) of 24 to +48V 25 at TP2_N24 . node 24 to +48V 25 at TP2_N24
Test Execution … … Observe and acquire Observe and acquire 26 27 26 27 iBP BAT48ShortMax or iBP BAT27ShortMax iBM BAT48ShortMax or iBM BAT27ShortMax
at TP_N24_R iBP of node 24 (shall be at TP_N24_R iBM of node 24 (shall be
at TP1_N24 ). at TP1_N24 ).
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL13) of node 24. Wait at least 12 FL14) of node 24. Wait at least 12 seconds. seconds
… …
Pass/Fail Criteria In case the IUT does not support 42V In case the IUT does not support 42V
systems: |iBP BAT27ShortMax | ≤ 100mA. systems: |iBM BAT27ShortMax | ≤ 100mA.
In case the IUT does support 42V In case the IUT does support 42V
systems: |iBP BAT48ShortMax | ≤ 120mA. systems: |iBM BAT48ShortMax | ≤ 120mA.
… …
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.19.5 to 5.3.19.6: Short circuit bus wires to -5V
5.3.19.5.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to -5V. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
5.3.19.5.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to -5V. • Communication: Node 24 and 23 as transmitter.
5.3.19.5.3 Preamble (setup state) • Standard preamble. • Short circuit BP (failure FL19) of node 24 to -5V at TP2_N24.
5.3.19.5.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24.
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• Observe and acquire uRxD at TP_N23_RxD of node 23. • In case of an available RxEN signal observe and acquire uRxEN at TP_N23_RxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Observe and acquire iBP -5VShortMax at TP_N24_RiBP of node 24 (shall be at TP1_N24 ). • Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by a short circuit current measurement pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples where taken by the data acquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 24. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL19) of node 24. Wait at least 12 seconds. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.19.5.5 Postamble • Standard postamble.
5.3.19.5.6 Pass- / Fail Criteria Pass criteria:
• |iBP -5VShortMax | ≤ 100mA. • The IUT of node 24 shall signal an error to the host after detecting the failure. • After switching off the failure: o uRxD of the IUT in node 24 must receive the patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23 and signal them at TP_N24_RxD accordingly. o uRxD of the IUT in node 23 must receive the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 23 and signal them at TP_N23_RxD accordingly. o In case of an available RxEN signal uRxEN at TP_N24_RxEN of the IUT in node 24 must be in logical LOW state while receiving the
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patterns that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23 o In case of an available RxEN signal uRxEN at TP_N23_RxEN of the IUT in node 23 must be in logical LOW state while receiving the patterns that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 24
5.3.19.5.7 Test Instances Instance 5.3.19.5 5.3.19.6
Purpose Stress S/C BP to -5V at node 24 S/C BM to -5V at node 24
Test description
Precondition
Configuration Power Supply
Ground Shift
Failure S/C BP to -5V S/C BM to -5V
Preamble Standard. Standard. Short circuit BP (failure FL19) of Short circuit BM (failure FL20) of node 24 to -5V at TP2_N24 . node 24 to -5V at TP2_N24
Test Execution … …
Observe and acquire iBP -5VShortMax Observe and acquire iBM -5VShortMax
at TP_N24_R iBP of node 24 (shall at TP_N24_R iBM of node 24 (shall be at TP1_N24 ). be at TP1_N24 ).
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL19) of node 24. Wait at least 12 FL20) of node 24. Wait at least 12 seconds. seconds
… …
Pass/Fail Criteria |iBP -5VShortMax | ≤ 100mA. |iBM -5VShortMax | ≤ 100mA.
… …
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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5.3.19.7 S/C BP to BM at node
5.3.19.7.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of both bus wires. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
5.3.19.7.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to BM. • Communication: Node 24 and 23 as transmitter.
5.3.19.7.3 Preamble (setup state) • Standard preamble. • Short circuit BP to BM (failure FL21) of node 24 at TP2_N24 .
5.3.19.7.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxEN of node 23. • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24.
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• Observe and acquire uRxD at TP_N23_RxD of node 23. • In case of an available RxEN signal observe and acquire uRxEN at TP_N23_RxEN of node 23. • Observe and acquire uRxD at TP_N24_RxD of node 24. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24.
• Observe and acquire iBM BPShortMax at TP_N24_RiBM of node 24 (shall be at TP1_N24 ). • Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by a short circuit current measurement pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples where taken by the data acquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 24. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP to BM (failure FL21) of node 24. Wait at least 12 seconds. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one TSS pattern, followed by one 50/50 pattern.
5.3.19.7.5 Postamble • Standard postamble.
5.3.19.7.6 Pass- / Fail Criteria Pass criteria:
• |iBM BPShortMax | ≤ 100mA. • The IUT of node 24 shall signal an error to the host after detecting the failure. • After switching off the failure: o uRxD of the IUT in node 24 must receive the patterns and signal at TP_N24_RxD and TP_N24_RxEN that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23. o uRxD of the IUT in node 23 must receive the patterns and signal at TP_N23_RxD and TP_N23_RxEN that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 24. o In case of an available RxEN signal uRxEN of the IUT in node 24 must receive the patterns and signal them at TP_N24_RxD and
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TP_N24_RxEN that are stimulated at TP_N23_TxD and TP_N23_TxEN of node 23. o In case of an available RxEN signal uRxEN of the IUT in node 23 must receive the patterns and signal them at TP_N23_RxD and TP_N23_RxEN that are stimulated at TP_N24_TxD and TP_N24_TxEN of node 24.
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5.3.19.8 S/C BP to BM at node with data frame
5.3.19.8.1 Test Purpose This test checks the ability of the IUT to signal an error to the host in case of a short circuit of both bus wires while actively transmitting a data frame.
5.3.19.8.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to BM. • Communication: Node 24 as transmitter.
5.3.19.8.3 Preamble (setup state) • Standard preamble. • Short circuit BP to BM (failure FL21) of node 24 at TP2_N24 .
5.3.19.8.4 Test execution • Observe and acquire uTxD at TP_N24_TxD of node 24. • Observe and acquire uTxEN at TP_N24_TxEN of node 24. • Observe and acquire the error signal of the host interface ( TP_N24_ERRN or TP_N24_INTN ) of node 24. • Stimulate IUT of node 24 at TP_N24_TxD and TP_N24_TxEN by one TSS pattern according to chapter 5.1.3.2 followed by eight 50/50 patterns according to chapter 5.1.3.9.
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• Switch off short circuit BP to BM (failure FL21) of node 24 after uTxEN is switched back to logical HIGH.
5.3.19.8.5 Postamble • Standard postamble.
5.3.19.8.6 Pass- / Fail Criteria Pass criteria: • The IUT of node 24 shall signal an error to the host latest 1ms after the transmission stops, i.e. TxEN switches from LOW to HIGH.
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5.3.20 Communication.Shortened Bit Times Hint: value of about 80ns is a snapshot of the current status. This value may change in the future if new results are available.
5.3.20.1 Shortened low pattern
5.3.20.1.1 Test Purpose This test checks the ability of the IUT to receive shortened bits according to the timing constraints chapter 12 in [01-PL Spec]. This test shall verify, that the IUT itself does receive the shortened bits correctly and signals them to the CC. The test hardware shall be calibrated for this test case.
5.3.20.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: Node 11 as transmitter.
5.3.20.1.3 Preamble (setup state) • Standard preamble.
5.3.20.1.4 Test execution • Observe and acquire uTxD at TP_N11_TxD of node 11. • Observe and acquire uTxEN at TP_N11_TxEN of node 11. • Observe and acquire uBus at TP4_N12 of node 12 according to the observation window described in chapter 5.1.4.3. • Observe and acquire uRxD at TP_N12_RxD of node 12 according to the observation window described in chapter 5.1.4.3. • Stimulate IUT in node 11 at TP_N11_TxD and TP_N11_TxEN by one TSS pattern, followed by three 10Bit Low patterns, followed by one 10/90 pattern, followed by two 10Bit Low patterns. The length of each single bit
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shall be 80ns measured at TP4_N12 of node 12. In case the bit length is too long the stimulated bits at the transmitter shall be shortened, otherwise the bits shall be elongated.
5.3.20.1.5 Postamble • Standard postamble.
5.3.20.1.6 Pass- / Fail Criteria Pass criteria: • the length of the received high bit in the 10/90 pattern as specified in the observation window in uRxD of node 12 shall be equal to the length of the high bit in uBus of the corresponding TP4_N12 of node 12 ±5ns, i.e. the receiver asymmetry shall be within the allowed range, according to chapter 8.9.3 in [01-PL Spec].
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5.3.20.2 Shortened high pattern
5.3.20.2.1 Test Purpose This test checks the ability of the IUT to receive shortened bits according to the timing constraints chapter 12 in [01-PL Spec]. This test shall verify, that the IUT itself does receive the shortened bits correctly and signals them to the CC. The test hardware shall be calibrated for this test case.
5.3.20.2.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: Node 11 as transmitter.
5.3.20.2.3 Preamble (setup state) • Standard preamble.
5.3.20.2.4 Test execution • Observe and acquire uTxD at TP_N11_TxD of node 11. • Observe and acquire uTxEN at TP_N11_TxEN of node 11. • Observe and acquire uBus at TP4_N12 of node 12 according to the observation window described in chapter 5.1.4.4. • Observe and acquire uRxD at TP_N12_RxD of node 12 according to the observation window described in chapter 5.1.4.4. • Stimulate IUT in node 11 at TP_N11_TxD and TP_N11_TxEN by one TSS pattern, followed by three 10Bit High patterns, followed by one 90/10 pattern, followed by two 10Bit High patterns. The length of each single bit shall be 80ns measured at TP4_N12 of node 12. In case the bit length is too long the stimulated bits at the transmitter shall be shortened, otherwise the bits shall be elongated.
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5.3.20.2.5 Postamble • Standard postamble.
5.3.20.2.6 Pass- / Fail Criteria Pass criteria: • the length of the received low bit in the 90/10 pattern as specified in the observation window in uRxD of node 12 shall be equal to the length of the low bit in uBus of the corresponding TP4_N12 of node 12 ±5ns, i.e. the receiver asymmetry shall be within the allowed range, according to chapter 8.9.3 in [01-PL Spec].
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5.3.21 Dynamic Ground Shift
5.3.21.1 Dynamic ground shift at transmitter
5.3.21.1.1 Test Purpose This test checks the ability of the IUT to transmit a test pattern while dynamic ground shift is present.
5.3.21.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: Node 23 as transmitter.
5.3.21.1.3 Preamble (setup state) • Standard preamble.
5.3.21.1.4 Test execution • Observe and acquire uGS_dyn at TP_N23_UGS of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N23_TxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N24_RxD of node 24 according to the observation window described in chapter 5.1.4.5. • In case of an available RxEN signal observe and acquire uRxEN at TP_N24_RxEN of node 24 according to the observation window described in chapter 5.1.4.5. • Stimulate IUT in node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High
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pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
5.3.21.1.5 Postamble • Standard postamble.
5.3.21.1.6 Pass- / Fail Criteria Pass criteria: • the IUT of node 24 shall receive all patterns after the trigger event in uTxD of node 23, i.e. the dynamic ground shift shall not disturb the communication. • in case of an available RxEN signal uRxEN of node 24 shall be in logical LOW state while uRxD of node 24 signals the received patterns.
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5.3.21.2 Dynamic ground shift at receiver
5.3.21.2.1 Test Purpose This test checks the ability of the IUT to receive a test pattern while dynamic ground shift is present.
5.3.21.2.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: Node 24 as transmitter.
5.3.21.2.3 Preamble (setup state) • Standard preamble.
5.3.21.2.4 Test execution • Observe and acquire uGS_dyn at TP_N23_UGS of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_N24_TxD of node 24 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N24_TxEN of node 24 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.5. • In case of an available RxEN signal observe and acquire uRxEN at TP_N23_RxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate IUT in node 24 at TP_N24_TxD and TP_N24_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
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5.3.21.2.5 Postamble • Standard postamble.
5.3.21.2.6 Pass- / Fail Criteria Pass criteria: • the IUT of node 23 shall receive all patterns after the trigger event in uTxD of node 24, i.e. the dynamic ground shift shall not disturb the communication. • in case of an available RxEN signal uRxEN of node 23 shall be in logical LOW state while uRxD of node 23 signals the received patterns.
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5.3.22 Eye Diagram
5.3.22.1 Eye diagram at receiver
5.3.22.1.1 Test Purpose This test checks the eye diagram at the receiver according to the eye diagram chapter 7.4 in [01-PL Spec]. In this test case the bandwidth of the oscilloscope shall be limited to 20MHz.
5.3.22.1.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o VCC power supply of all nodes: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
• VIO power supply of all nodes (in case of an available V IO supply input): depends on implementation. • Ground shift: 0V. • Failure: none. • Communication: Node 2 as transmitter.
5.3.22.1.3 Preamble (setup state) • Standard preamble.
5.3.22.1.4 Test execution • Limit the bandwidth of the oscilloscope to 20MHz. • Observe and acquire uTxD at TP_N1_TxD of node 2. • Observe and acquire uTxEN at TP_N1_TxEN of node 2. • Observe and acquire uBus at TPAS4_B3 of the AS according to the observation window described in chapter 5.1.4.6. • Stimulate IUT in the node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by ten 50/50 pattern.
5.3.22.1.5 Postamble • Standard postamble.
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5.3.22.1.6 Pass- / Fail Criteria Pass criteria: • The eye diagram obtained with the observed and acquired uBus signal at TPAS4_B3 of the AS shall not violate the mask of TP4 defined in Figure 7- 4 in [01-PL Spec].
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5.4 Test procedures
5.4.1 Signal shape, timing, delay
PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS .IDCPowerSupplyConfig.Output() * PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetGroundShift() * NetServices.ISwitch.SetTermination() ** PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() Scope.IConfiguration.Acquisition() Scope.IConfiguration.Channel() Scope.IConfiguration.Trigger() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only. ** * Test cases with specific termination, only.
Figure 5-43: Test Procedure for Signal Shape, Timing and Delay Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS .IDCPowerSupplyConfig.Output() * PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetGroundShift() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only.
Figure 5-44: Test Procedure for Truncation and Masks Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * PowerSupply_ALT_VIO .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VIO .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS .IDCPowerSupplyConfig.Output() ** PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) ** NetServices.ISwitch.SetGroundShift() ** PatternGenerator.IPatternGenerator.Configure() *** PatternGenerator.IPatternGenerator.CreateComposedPattern() *** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() **** PowerSupply_ALT_VIO .IDCPowerSupplyConfig.Output() **** NetServices.IControl.SetOperatingMode() ***** NetServices.IControl.SendLocalWakeup() ******
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * PowerSupply_ALT_VIO .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
****** Test cases with alternative power supply configuration, only. ** **** Test cases with ground shift, only. *** *** Required for setup state in some test cases, only. **** ** Test cases with alternative power supply output change during test execution, only. ***** * Test cases with operation mode change of IUT(s) during test execution, only. ****** Test cases with local wakeup of IUT(s) during test execution, only.
Figure 5-45: Test Procedure for Mode Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true) NetServices.ISwitch.SetSupplyConfiguration() * NetServices.ISwitch.SetInterruptionOnBoard() ** NetServices.ISwitch.SetShortCircuitOnBoard() ** PatternGenerator.IPatternGenerator.Configure() *** PatternGenerator.IPatternGenerator.CreateComposedPattern() *** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with alternative power supply configuration, only. ** * Test cases with on board interruptions or short circuits, only. *** Required for setup state, only.
Figure 5-46: Test Procedure for Failure Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(true) * PowerSupply_ALT_VIO .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VIO .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS .IDCPowerSupplyConfig.Output() ** PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) ** NetServices.ISwitch.SetGroundShift() ** PatternGenerator.IPatternGenerator.Configure() *** PatternGenerator.IPatternGenerator.CreateComposedPattern() *** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() **** PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() **** PowerSupply_ALT_VIO .IDCPowerSupplyConfig.Output() ****
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VIO .IDCPowerSupplyConfig.EnableOutput(false) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(false) * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
**** Test cases with alternative power supply configuration, only. ** ** Test cases with ground shift, only. *** * Required for setup state, only. **** Test cases with alternative power supply output change during test execution, only.
Figure 5-47: Test Procedure for Undervoltage Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.DynamicLowBattery() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
PowerSupply_VBAT .IBatterySupplyConfig.InitiateArbitraryFunction()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest() NetServices.IControl.SetOperatingMode() **
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
** Test cases with alternative power supply configuration, only. ** Test cases with op-mode change during test execution, only.
Figure 5-48: Test Procedure for Dynamic Low Battery Cases
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6 Test Cases for Active Stars These test case section is applicable to all active stars, independent from an implemented communication controller or bus guardian interface. In such case, TxD and TxEN of the communication controller interface and BGE of the bus guardian interface shall be set to logical HIGH state permanently, if implemented.
6.1 Configuration
6.1.1 Topology As specified in chapter 2.4. All IUT of the active star are of the same type and from the same manufacturer.
6.1.2 Test planes
6.1.2.1 Analog signals The active star has four specified test planes. Two test planes for the transmitting branch and two for the receiving branch.
Transmitter Active Star Receiver
BD AS BD ReceivingBranch Transmitting Branch
TPAS3_By TPAS4_ByTPAS1_By TPAS2_By
Figure 6-1: Test Planes @ the Active Star for analog Signals
TP Name Signal Description
TPAS1_By uBus Transmitting branch, test plane as close as possible to the IUT
TPAS1_By uBP Transmitting branch, test plane as close as possible to the IUT
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TP Name Signal Description
TPAS1_By uBM Transmitting branch, test plane as close as possible to the IUT
TPAS2_By uBus Transmitting branch, test plane as close as possible to the network
TPAS3_By uBus Receiving branch, test plane as close as possible to the network
TPAS4_By uBus Receiving branch, test plane as close as possible to the IUT
Table 6-1: Test Planes @ the Active Star for analog Signals
11
2 AS 4
3
Figure 6-2: 4: Branches of the Active Star The AS has 4 branches that are named for the test planes as TPASx_By where • x stands for the test plane • y stands for the branch of the AS Example: TPAS1_B2 represents the test plane 1 at the branch 2 of the AS.
6.1.2.2 Digital signals The test planes at the AS for digital signals (observation by logic analyzer) are specified as:
TP
AS
INH1
BD
Figure 6-3: Test Planes @ the AS
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TP Name Signals Description
TP_AS_INH1 INH1 INH1 signal of the IUT
Table 6-2: Test Planes @ the AS (digital Signals)
6.1.2.3 Test planes for current measurement A shunt shall be implemented in order to measure the current of the bus wires:
28 • TP_AS_B1 _RiBP
• TP_AS_B1_RiBM 6.1.2.4 Test planes for the oscilloscope The oscilloscope observes the following test planes: • TP_N23_RxD • TP_N23_TxEN • TP_N23_TxD • TP_N2_RxD • TP_N2_TxEN • TP_N2_TxD • TP4_N2 • TP4_N12 • TPAS1_By_BM • TPAS1_By_BP • TP_AS_UGS (dynamic ground shift voltage)
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Test Planes for Oscilloscope 1 UGS BP/BM GND AS
BP/BM 1m BP/BM 11
PS 11m 2 AS 4 1.5m 0.15m 10m
3 0 0 . . 0 BP/BM 2 m 2 .1 m .2 m m m 0 1 0.2m 0.2m 0.2m 3.5m
24 23 22 21 2 14 13 12 11
BP/BM BP/BM TxD, TxEN & RxD
Figure 6-4: Test Planes for the Oscilloscope
6.1.2.5 Test planes for the logic analyzer The logic analyzer observes the following test planes: • TP_Nx 29 _RxD • TP_Nx_RxEN • TP_Nx_TxD • TP_Nx_TxEN • TP_Nx_STBN • TP_Nx_ERRN • TP_Nx_INH1 • TP_Nx_WAKE • TP_Nx_BGE • TP_Nx_EN • TP_Nx_INTN • TP_Nx_SCSN 6.1.2.6 Test planes for the pattern generator The pattern generator stimulates the following test planes: • TP_Nx 30 _TxD • TP_Nx_TxEN • TP_Nx_BGE • TP_N24_WAKE
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6.1.3.1 Babbling idiot This test signal simulates a babbling idiot:
15000µs
1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs
TP_N12_TxD TP_N12_TxEN
800µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 700µs
TP_N13_TxD TP_N13_TxEN
500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1500µs 1000µs
TP_N14_TxD TP_N14_TxEN
Figure 6-5: Test Pattern for a Babbling Idiot Simulation
6.1.3.2 Star setup delay These test signals are specified to check the parameter dStarSetUpDelay . Test signal of node 1:
gdBit gdTSSTransmitter 0 1 2 3 4 5 6 7 8 TxD High Low
High TxEN Low
Figure 6-6: Test Signal for Node 1 (Star Setup Delay)
Test signal of node 2:
gdBit gdTSSTransmitter 0 1 2 3 4 5 6 7 8 TxD High Low
High TxEN Low
Figure 6-7: Test Signal for Node 2 (Star Setup Delay)
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6.1.4.1 Parameters dStarDelay and dStarDelay0
TSS gdWakeupSymbolTxLow gdWakeupSymbolTxIdle gdWakeupSymbolTxLow gdWakeupSymbolTxIdle 60gdBit 180gdBit 60gdBit 180gdBit 11gdBit High TxD Low
TxEN High Low 42.9µs 10 Bit HIGH/LOW 10gdBit Trigger Event Zoom
Zoom
0 1 2 3 4 5 6 7 8 9 10 11 12 High TxD Low 10 Bit LOW to HIGH High 10 Bit HIGH to LOW TxEN Low
High RxD Low
Observation Window
Figure 6-8: Observation Point for the Analysis of the Star Delay Trigger event: first negative edge of external trigger signal . Start acquisition point 1: 42.9µs after the trigger event. Start acquisition point 2: 65µs after the trigger event. Observation Window: 0.75µs. The [01-PL Spec] shows the measurement descriptions of the parameters [dStarDelay , dStarDelay0 ] in figure 9-3.
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TSS gdWakeupSymbolTxLow gdWakeupSymbolTxIdle gdWakeupSymbolTxLow gdWakeupSymbolTxIdle 60gdBit 180gdBit 60gdBit 180gdBit 11gdBit High TxD Low
TxEN High Low
41.8µs 50/50 Pattern 10gdBit Trigger Event Zoom Zoom – Observation Window
gdTSSTransmitter TxD High Low
High TxEN Low Observation Window
Figure 6-9: Observation point for the Analysis of the Active Star Truncation Trigger event: first negative edge of external trigger signal. Start acquisition point 1: 41.8µs after the trigger event. Start acquisition point 2: 63.9 µs after the trigger event. Observation Window : 1.75µs. The [01-PL Spec] shows the measurement description of the parameter dStarTruncation in figure 9-3.
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TSS gdWakeupSymbolTxLow gdWakeupSymbolTxIdle gdWakeupSymbolTxLow gdWakeupSymbolTxIdle 60gdBit 180gdBit 60gdBit 180gdBit 11gdBit High TxD Node A Low TxEN High Low dStarSetUpDelay High TxD Pattern A Node B Low TxEN High Low 41.0µs dStarSetUpDelay Zoom Pattern B Trigger Event 500 ns Zoom - Observation Window
gdTSSTransmitter 0 1 2 3 4 5 6 7 8 TxD High Low dStarSetUpDelay Pattern A High TxEN Low
gdTSSTransmitter 0 1 2 3 4 5 6 7 8 TxD High Low dStarSetUpDelay Pattern B High TxEN Low
Observation Window
Figure 6-10: Observation point for the Analysis of the Active Star SetUp Delay Trigger event: first negative edge of external trigger signal. Start acquisition point: 41µs after the trigger event. Observation Window : 4.2µs. The [01-PL Spec] shows the measurement description of the parameter dStarSetUpDelay in figure 9-6.
6.1.4.4 Parameter dStarWakeUpReaction after RWU This observation window is to verify the bus state change from Idle_LP to Idle after detection of a remote wake-up event. Trigger event: first negative edge of external trigger signal. Start acquisition point: 0µs after the trigger event. Observation Window : 100ms + 1ms security.
6.1.4.5 Parameter dStarWakeUpReaction before RWU This observation window is to verify the bus state Idle_LP before detection of a remote wake-up event. Trigger event: first negative edge of external trigger signal.
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Start acquisition point: 0µs after the trigger event. Observation Window : 25µs.
6.1.4.6 Parameter dStarGoToSleep This observation window is to verify the bus state change from Idle to Idle_LP when all branches are in Branch_Idle or Branch_FailSilent for longer than dStarGoToSleep . Trigger event: first negative edge of external trigger signal. Start acquisition point: 0µs after the trigger event. Observation Window : 64000ms + 1000ms.
6.1.4.7 Branch modes This observation window is to verify the branch modes of the branches of the active star, i.e. Branch_Idle (bus state Idle ) and Branch_Active (bus states Data_1 , Data_0 ). Trigger event: first negative edge of external trigger signal. Start acquisition point: 0µs after the trigger event. Observation Window : 5µs.
6.1.4.8 Parameter dBranchActive This observation window is to verify the branch noise detection time dBranchActive . Trigger event: first negative edge of external trigger signal. Start acquisition point: 0µs after the trigger event. Observation Window : 15000µs.
6.1.4.9 Dynamic low battery – AS_Sleep This observation window is to verify the bus state of the branches of the active star during the dynamic low battery pulse. All branches shall be in Idle_LP state. Trigger event: first negative edge of external trigger signal. Start acquisition point: 0s after the trigger event. Observation Window : 10.2s (ceiled duration of low battery voltage pulse).
6.1.5 Operation modes of the AS The AS has the following operation mode: • AS_Normal : receive/transmit possible, transition to AS_Sleep possible. • AS_Sleep : receive/transmit NOT possible, transition to AS_Normal possible via wake-up symbol on the bus. The AS reaches the operation modes by:
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Operation Enter by… mode AS_Normal • Switching on the supply • Wake-up pattern on the bus AS_Sleep • End of communication after a specified timeout • Undervoltage condition
6.1.6 Power supplies The used power supplies:
• The V CC supply is connected to the IUT with different voltages. VCC = VCCUndervoltage , +5.0V.
• The V BAT supply input of the AS is optional and may be connected to the IUT with different voltages. VBAT = default, +7.0V, +5.5V, VBATUndervoltage . 6.1.7 Stress The ground shift is located as shown in Figure 3-2. The low battery affects the active star only. Note that the common nodes including their bus drivers are not stressed at all in active star test cases! All nodes are always supplied with all implemented supply voltages and not stressed by low battery or ground shift.
6.1.8 Failures Failures of the AS are also described in chapter 3.5.
6.1.9 Optional features The following features are optional as specified in [01-PL Spec] and must be tested in the test cases if available in the IUT:
6.1.9.1 Functional class “Active Star - Voltage Regulator Control” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: o Signal INH1
o Power supply input VBAT
6.1.9.2 Functional class “Active Star - Internal Voltage Regulator”
• This Functional Class comprises the implementation of a “V BAT ” power supply input and requires that the AS is fully operational without a V CC supply.
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Message from Node FlexRay Data on the bus 1 2
t
Figure 6-11: Communication Matrix C Delay between the messages: 500ns. The second transmitter (node 2) starts transmission only 500ns after the first transmitter (node 1). So, the transmission of node 2 shall reach the active star slightly later than 500ns after the transmission of node 1, because the propagation delay between node 2 to the active star (3.5m) is greater than between node 1 and the active star (1m). Matrix E: Some test cases need a matrix for the passive networks:
Message from Node x
Transmitters 12 23
t
Figure 6-12: Communication Matrix E Pause between the messages: 20µs. Single Transmitter In some test cases only one transmitter is required; this is either node 1 or 2:
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Transmitter 1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter
Figure 6-13: Communication Single Transmitter
Node 1 and 2 as Transmitter In some test cases node 1 and 2 as transmitter are required:
Transmitter 1 Point of Observation
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter Point of Observation
Figure 6-14: Communication Node 1 and 2 as Transmitter
Node 23 as transmitter: In this communication node 23 is the transmitter.
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Message from Node
Transmitter 23
t
Figure 6-15: Communication with Node 23 as Transmitter (Time Diagram)
1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter
Figure 6-16: Communication with Node 23 as Transmitter (Topology)
6.1.11 Standard preamble 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD of all nodes shall be in logical HIGH (idle) state. 6. In case a BGE signal is available, this signal shall be in logical HIGH state in all nodes. 7. Stimulate bus drivers of all nodes via host command to enter BD_Normal . 8. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
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6.1.13 Standard postamble 1. Set ground shift to 0V. 2. Reset failures. 3. Switch off power supplies.
6.1.14 Services Services correspond to chapter 5.1.17.
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6.2 Static test cases The motivation of static test cases is to check the availability and the boundaries in the data sheet of the IUT (topology independent). Every parameter must be part of the data sheet and fulfill the specified boundaries. If at least one parameter does not pass this test, the result of the whole conformance test is failed.
Index Parameter SOVS Brace Description Min Max Unit
1. dBusTx01 Communication. Rise time differential 3.75 18.75 ns Signal Shape voltage (20% 80%)
2. dBusTx10 Communication. Fall time differential 3.75 18.75 ns Signal Shape voltage (80% 20%)
3. uStarTx active Communication. Absolute differential 600 2000 mV Signal Shape voltage while sending 31
4. uStarTx idle Communication. Absolute differential 0 30 mV Signal Shape voltage while Idle 31
5. uBus ActiveHigh Communication. Upper receiver 150 425 mV Threshold threshold for detecting activity
6. uBus ActiveLow Communication. Lower receiver -425 -150 mV Threshold threshold for detecting activity
7. dBranchActive Communication. Noise detection time 1500 15000 µs Timing
8. dBranch Communication. Timeout for recovery 10 µs FailSilentIdle Timing after failure
9. RCM1 , RCM2 Environment Common mode input 10 40 kΩ resistance
10. uCM Environment. Common mode -10 +15 V Ground Shift voltage range that does not disturb the receive function 32
11. uUV BAT Power Transition to low 2 5.5 V Supply operation mode when VBAT voltage falls below product specific threshold
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Index Parameter SOVS Brace Description Min Max Unit
12. uUV CC Power Transition to low 2 Product V Supply operation mode when specific VCC voltage falls below product specific threshold
13. dUV CC Power Reaction time for VCC 1000 ms Supply undervoltage detection
14. dStar Communication. Shortening of the TSS 450 ns Truncation Truncation
15. iBP Leak Mode. Leakage current when 25 µA Active.Star. all supplies are
Off.iBP Leak switched off
16. iBM Leak Mode. Leakage current when 25 µA Active.Star. all supplies are
Off.iBM Leak switched off
17. iBM GNDShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted to GND
18. iBP GNDShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted to GND
19. iBMBAT48ShortMax Failure. Maximum output 120 mA Short circuit.BP current when shorted
to V BAT =+48V
20. iBPBAT48ShortMax Failure. Maximum output 120 mA Short circuit.BM current when shorted
to V BAT =+48V
21. iBMBAT27ShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted
to V BAT =+27V
22. iBPBAT27ShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted
to V BAT =+27V
23. Functional Functional Class Checks the complete - Class implementation of all ”Active Star – specified options Bus Guardian interface”
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Index Parameter SOVS Brace Description Min Max Unit
24. Functional Functional Class Checks the complete - Class implementation of all ”Active Star – specified options Communi- cation controller interface” 25. dStarDelay Communication. Propagation delay 250 ns Delay trough an active star
26. dStarDelay 0 Communication. Propagation delay 250 ns Delay trough an active star
27. dStarAsym Communication. Asymmetric 8 ns Delay propagation delay for monolithic devices
28. dStarAsym Communication. Asymmetric 10 ns Delay propagation delay for non-monolithic devices
29. dStarSetUp Communication. Set up delay 500 ns Delay Timing
30. dStarGoTo Communication. Go-to-Sleep timeout 640 64000 ms Sleep Timing
31. dStarWakeUp Communication. Active star wake-up 100 ms Reaction Timing reaction time
32. T Environment Ambient temperature -40 +125 °C
33. iBM-5VShortMax Failure. Maximum output 100 mA Short circuit.BP current when shorted
to V BAT =-5V
34. iBP-5VShortMax Failure. Maximum output 100 mA Short circuit.BM current when shorted
to V BAT =-5V
35. Functional Functional Class Checks the complete - Class implementation of all ”Active Star – specified options Voltage regulator control” 36. Functional Functional Class Checks the complete - Class implementation of all ”Active Star – specified options Internal voltage regullator”
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Index Parameter SOVS Brace Description Min Max Unit
37. iBMBPShortMax Failure. Maximum output 100 mA Short current when BM circuit.BMBP shorted BP
38. iBPBMShortMax Failure. Maximum output 100 mA Short current when BP circuit.BPBM shorted BM
39. iBMBAT60ShortMax Failure. Maximum output 150 mA Short circuit.BP current when shorted 33 34 to V BAT =+60V
40. iBPBAT60ShortMax Failure. Maximum output 150 mA Short circuit.BM current when shorted 33 34 to V BAT =+60V
41. uBias – Mode. Voltage @ BP & BM 1800 3200 mV AS_Normal 35 Active.Star. during bus state Idle Normal
42. uBias – Mode. Voltage @ BP & BM -200 +200 mV Low Power 35 Active.Star. during bus state Low Power Idle_LP
43. dUV VBAT Power Supply Reaction time for 1000 ms VBAT undervoltage detection
44. uUV IO Power Supply Transition to low 0.75 Product V power when VIO specific voltage falls below product specific threshold
45. dUV IO Power Supply Reaction time for VIO 1000 ms undervoltage detection
Table 6-3: Static Test Cases
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6.3 Test cases
6.3.1 Communication.Delay. dStarDelay
6.3.1.1 to 6.3.1.4: Communication delay dStarDelay
6.3.1.1.1 Test Purpose This test checks the FlexRay parameter dStarDelay (propagation delay of a positive edge through the active star) in the test system while no stress condition is present.
6.3.1.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix E; the delay is measured twice for each transmitted data o 1st pass according to chapter 6.1.4.1 (42.9µs, N12) o 2nd pass according to chapter 6.1.4.1 (42.9µs + 22.1µs, N23)
6.3.1.1.3 Preamble (setup state) • Standard preamble.
6.3.1.1.4 Test execution • Observe and acquire uBus at TPAS4_B4/2 of the receiving branches according to the observation window described in chapter 6.1.4.1. • Observe and acquire uBus at TPAS1_B2/4 of the transmitting branches according to the observation window described in chapter 6.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of the first transmitting node according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern.
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• Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 10/90 pattern.
6.3.1.1.5 Postamble • Standard postamble.
6.3.1.1.6 Pass- / Fail Criteria Pass criteria: • dStarDelay ≤ 250ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.1.1.7 Test Instances Instance 6.3.1.1 6.3.1.2 6.3.1.3 6.3.1.4
Purpose Stress ground shift ground shift none low battery @ AS @ node
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS -5.0V @ N23
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.2 Communication.Delay. dStarDelay 0
6.3.2.1 to 6.3.2.4: Communication delay dStarDelay 0
6.3.2.1.1 Test Purpose
This test checks the FlexRay parameter dStarDelay 0 (propagation delay of a negative edge through the active star) in the test system while no stress condition is present.
6.3.2.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix E; the delay is measured twice for each transmitted data o 1st pass according to chapter 6.1.4.1 (42.9µs, N12) o 2nd pass according to chapter 6.1.4.1 (42.9µs + 22.1µs, N23)
6.3.2.1.3 Preamble (setup state) • Standard preamble.
6.3.2.1.4 Test execution • Observe and acquire uBus at TPAS4_B4/2 of the receiving branches according to the observation window described in chapter 6.1.4.1. • Observe and acquire uBus at TPAS1_B2/4 of the transmitting branches according to the observation window described in chapter 6.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of the first transmitting node according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 10/90 pattern.
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6.3.2.1.5 Postamble • Standard postamble.
6.3.2.1.6 Pass- / Fail Criteria Pass criteria:
• dStarDelay 0 ≤ 250ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.2.1.7 Test Instances Instance 6.3.2.1 6.3.2.2 6.3.2.3 6.3.2.4
Purpose Stress ground shift ground shift none low battery @ AS @ node
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS -5.0V @ N23
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.3 Communication.Delay. dStarAsym
6.3.3.1 to 6.3.3.4: AS asymmetry dStarAsym
6.3.3.1.1 Test Purpose This test checks the FlexRay parameter dStarAsym of the active star while no stress condition is present.
This parameter is calculated as dStarAsym = | dStarDelay – dStarDelay 0 | with dStarDelay as measured in test case 6.3.1.1 and dStarDelay 0 as measured in test case 6.3.2.1. The calculation is done twice: • In case that node 12 is the transmitter • In case that node 23 is the transmitter
6.3.3.1.2 Configuration • No configuration needed.
6.3.3.1.3 Preamble (setup state) • No preamble needed.
6.3.3.1.4 Test execution
• Calculation of dStarAsym = | dStarDelay – dStarDelay 0 | as measured in the test cases above.
6.3.3.1.5 Postamble • No postamble needed.
6.3.3.1.6 Pass- / Fail Criteria Pass criteria: • In case of a monolithic device: dStarAsym ≤ 8ns. • In case of a non-monolithic device: dStarAsym ≤ 10ns.
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6.3.3.1.7 Test Instances Instance 6.3.3.1 6.3.3.2 6.3.3.3 6.3.3.4
Purpose Stress ground shift @ ground shift @ none low battery AS node
Test This Test Case calculates dStarAsym = | dStarDelay – dStarDelay 0 | with description dStarDelay as dStarDelay as dStarDelay as dStarDelay as measured in test measured in test measured in test measured in test case 6.3.1.1 and case 6.3.1.2 and case 6.3.1.3 and case 6.3.1.4 and
dStarDelay 0 as dStarDelay 0 as dStarDelay 0 as dStarDelay 0 as measured in test measured in test measured in test measured in test case 6.3.2.1 case 6.3.2.2 case 6.3.2.3 case 6.3.2.4
Precondition
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.4 Communication.Delay. dStarSetUpDelay
6.3.4.1 to 6.3.4.4: Communication delay dStarSetUpDelay
6.3.4.1.1 Test Purpose This test checks the FlexRay parameter dStarSetUpDelay while no stress condition is present. This test case verifies that a second incoming data stream reaching the active star slightly after dStarSetUpDelay is ignored by the active star.
6.3.4.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix C.
6.3.4.1.3 Preamble (setup state) • Standard preamble.
6.3.4.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of the transmitting nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of the transmitting nodes. • Observe and acquire uRxD at TP_Nx_RxD of all receiving nodes in the branches B2 and B4 of the active star. • Observe and acquire uBus at TPAS4_B1 of the receiving branch according to the observation window described in chapter 6.1.4.3. • Observe and acquire uBus at TPAS1_B3 of the transmitting branch according to the observation window described in chapter 6.1.4.3. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of the first transmitting node according to the sequence described on matrix C at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern.
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• Stimulate the bus driver of the first transmitting node according to the sequence described on matrix C at TP_Nx_TxD and TP_Nx_TxEN by the Star Setup Delay 1 36 pattern. • Stimulate the bus driver of the second transmitting node according to the sequence described on matrix C at TP_Nx_TxD and TP_Nx_TxEN by the Star Setup Delay 2 pattern. Start stimulation delayed by 500ns to the first transmitting node.
6.3.4.1.5 Postamble • Standard postamble.
6.3.4.1.6 Pass- / Fail Criteria Hint: the pattern sent by the second transmitting node shall not be retransmitted by the active star because the incoming data stream shall be ignored after dStarSetUpDelay . Pass criteria: • branch 2 and 4 must retransmit the pattern transmitted by node 1, only. That means, that the RxD signal of nodes 11, 12, 13, 14, 21, 22, 23 and 24 shall contain the pattern applied to node 1. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.4.1.7 Test Instances Instance 6.3.4.1 6.3.4.2 6.3.4.3 6.3.4.4
Purpose Stress ground shift ground shift none low battery @ AS @ node
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS -5.0V @ N23
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.5 Communication.Truncation. dFrameTSSTruncation M,N
6.3.5.1 to 6.3.5.4: Communication truncation dFramTSSTruncation M,N
6.3.5.1.1 Test Purpose This test checks the overall channel truncation while no stress condition is present according to the sum of all allowed truncation effects specified in [01-PL Spec]. This test shall verify, that only the transmission start sequence is affected by truncation effects and that a protocol controller would decode the following data properly.
6.3.5.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
6.3.5.1.3 Preamble (setup state) • Standard preamble.
6.3.5.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of the first transmitting node according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 10/90 pattern.
6.3.5.1.5 Postamble
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• Standard postamble.
6.3.5.1.6 Pass- / Fail Criteria Pass criteria: • the width of all received TSS patterns (logical LOW phase from the falling edge of the received TSS pattern to the rising edge of the first bit of the following 10/90 pattern) in uRxD of all nodes except the corresponding transmitting node shall be at least 100ns, i.e. the channel truncation shall be within the allowed range. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.5.1.7 Test Instances Instance 6.3.5.1 6.3.5.2 6.3.5.3 6.3.5.4
Purpose Stress ground shift ground shift none low battery @ AS @ node
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS -5.0V @ N23
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.6 Communication.Truncation. dStarTruncation
6.3.6.1 to 6.3.6.4: Communication truncation dStarTruncation
6.3.6.1.1 Test Purpose This test checks the FlexRay parameter dStarTruncation while no stress condition is present.
6.3.6.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix E; the truncation is measured twice for each transmitted data o 1st pass (receiving branch 4, node 12 as transmitter) according to chapter 6.1.4.2 (41.8µs, N12) o 2nd pass (receiving branch 2, node 23 as transmitter) according to chapter 6.1.4.2 (41.8µs + 22.1µs, N23)
6.3.6.1.3 Preamble (setup state) • Standard preamble.
6.3.6.1.4 Test execution • Observe and acquire uBus at TPAS4_B4/2 of the receiving branches according to the observation window described in chapter 6.1.4.2. • Observe and acquire uBus at TPAS1_B2/4 of the transmitting branches according to the observation window described in chapter 6.1.4.2. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of the first transmitting node according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one wake-up pattern.
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• Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix E at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.6.1.5 Postamble • Standard postamble.
6.3.6.1.6 Pass- / Fail Criteria Pass criteria: • dStarTruncation ≤ 450ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.6.1.7 Test Instances Instance 6.3.6.1 6.3.6.2 6.3.6.3 6.3.6.4
Purpose Stress ground shift ground shift none low battery @ AS @ node
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS -5.0V @ N23
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.7 Mode.Active Star.Normal
6.3.7.1 to 6.3.7.2: Remain in AS_Normal while undervoltage of V BAT
6.3.7.1.1 Test Purpose This test checks the ability of the active star to remain in operation mode AS_Normal in case of an undervoltage on V BAT if V CC is still available according to table 9-4, footnote (**) in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.7.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.7.1.3 Preamble (setup state) • Standard preamble.
6.3.7.1.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of the nodes 1, 12 and 23.
• Set V BAT power supply of active star to VBATUndervoltage . • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by ten 37 10Bit Low patterns. Repeat this sequence with a pause between the messages of 20µs for at least 1000ms to verify that communication is not disturbed even after the maximal undervoltage detection timeout ( dUV ).
6.3.7.1.5 Postamble • Standard postamble.
6.3.7.1.6 Pass- / Fail Criteria Pass criteria: Hint: This test case requires acquisition of at least 1000ms by the logic state analyzer. A bit level resolution is not required.
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• uRxD of all observed nodes shall contain all logical LOW sequences transmitted by node 2, i.e. the active star shall not enter AS_Sleep mode and shall retransmit all patterns received on branch 3.
6.3.7.1.7 Test Instances Instance 6.3.7.1 6.3.7.2
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.7.3 to 6.3.7.4: Operation mode change to AS_Normal in case of
power on of V BAT and V CC
6.3.7.3.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V BAT and V CC while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented or a V CC supply input is not implemented.
6.3.7.3.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.7.3.3 Preamble (setup state) • Standard preamble.
• Set V BAT and V CC power supply of active star to 0V.
6.3.7.3.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set V BAT power supply of active star to default.
• Set V CC power supply of active star to +5.0V. • Wait 100ms. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.7.3.5 Postamble • Standard postamble.
6.3.7.3.6 Pass- / Fail Criteria Pass criteria:
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• uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2, i.e. the active star shall enter AS_Normal mode within 100ms after power on and re-transmit the test patterns of node 2. • uINH1 shall be in logical HIGH state (Not_Sleep ) 100ms after switching on the power supplies up to the end of the test execution.
6.3.7.3.7 Test Instances Instance 6.3.7.3 6.3.7.4
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.7.5 to 6.3.7.6: Operation mode change to AS_Normal in case of
power on of V CC (V BAT not implemeted)
6.3.7.5.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V CC while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is implemented.
6.3.7.5.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.7.5.3 Preamble (setup state) • Standard preamble.
• Set V CC power supply of active star to 0V.
6.3.7.5.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2.
• Set V CC power supply of active star to +5.0V. • Wait 100ms. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.7.5.5 Postamble • Standard postamble.
6.3.7.5.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2, i.e. the active star shall enter AS_Normal mode within 100ms after power on and re-transmit the test patterns of node 2.
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6.3.7.5.7 Test Instances Instance 6.3.7.5 6.3.7.6
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.7.7 to 6.3.7.8: Operation mode change to AS_Normal in case of
power on of V BAT (V BAT not implemeted)
6.3.7.7.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V BAT while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is not implemented or a V CC supply input is implemented.
6.3.7.7.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.7.7.3 Preamble (setup state) • Standard preamble.
• Set V BAT power supply of active star to 0V.
6.3.7.7.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set V BAT power supply of active star to default. • Wait 100ms. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.7.7.5 Postamble • Standard postamble.
6.3.7.7.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2, i.e. the active star shall enter AS_Normal mode within 100ms after power on and re-transmit the test patterns of node 2.
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• uINH1 shall be in logical HIGH state ( Not_Sleep ) 100ms after switching on the power supply up to the end of the test execution.
6.3.7.7.7 Test Instances Instance 6.3.7.7 6.3.7.8
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.8 Mode.Active Star.Normal.GoToSleep
6.3.8.1 to 6.3.8.3: Operation mode change to AS_Sleep after dStarGoToSleep
6.3.8.1.1 Test Purpose This test checks the ability of the active star to go to AS_Sleep mode if all branches are in Branch_Idle for longer than dStarGoToSleep according to figure 9-4, transition number 2 in [01-PL Spec] while no stress condition is present.
6.3.8.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and VCC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.8.1.3 Preamble (setup state) • Standard preamble. • Interrupt BP and BM of the nodes 21..24 (branch 2) and 11..14 (branch 4).
6.3.8.1.4 Test execution • Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBP at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBM at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.5. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 10Bit Low pattern.
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• Trigger the scope to start observation synchronously with the stimuli at TP_N2_TxEN of node 2. • Trigger the logic state analyzer to start observation synchronously with the stimuli at TP_N2_TxEN of node 2. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • Wait 64000ms for the AS to enter AS_Sleep .
6.3.8.1.5 Postamble • Standard postamble.
6.3.8.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The Go-To-Sleep timeout dStarGoToSleep shall be measured with an error of less than 1%. Hint: The bit rate must be chosen in that way that the oscilloscope is able to detect the re-transmission of the AS, e.g. 50ms. • for at least the first 640ms after the transmission of node 2, uBP and uBM of branch 2 and 4 shall indicate idle state, i.e. uBP and uBM of branch 2 and 4 shall be between 1800mV and 3200mV ( idle ). Between 640ms and 64000ms after the transmission of node 2, uBP and uBM of branch 2 and 4 shall change to idle_LP state, i.e. uBP and uBM of branch 2 and 4 shall change to a voltage level between -200mV and +200mV ( idle_LP ). • in case of an available INH1 signal uINH1 shall be initially in logical HIGH state for at least 640ms. Between 640ms and 64000ms after the start of the observation, uINH1 shall change to logical LOW state.
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6.3.8.1.7 Test Instances Instance 6.3.8.1 6.3.8.2 6.3.8.3
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.9 Mode.Active Star.Normal.GoToSleep_Fail
6.3.9.1 to 6.3.9.3: Operation mode change to AS_Sleep after dStarGoToSleep (FailSilent)
6.3.9.1.1 Test Purpose This test checks the ability of the active star to go to AS_Sleep mode if one branch is in Branch_FailSilent and all other branches are in Branch_Idle for longer than dStarGoToSleep according to figure 9-4, transition number 2 in [01-PL Spec] while no stress condition is present.
6.3.9.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: babbling idiot. • Communication: none.
6.3.9.1.3 Preamble (setup state) • Standard preamble. • Interrupt BP and BM of the nodes 21..24 (branch 2), node 1 (branch 1) and node 2 (branch 3).
6.3.9.1.4 Test execution • Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBus at TPAS4_B4 of the receiving branch 4 according to the observation window described in chapter 6.1.4.5. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxEN by one babbling idiot pattern as defined in chapter 6.1.3.1. Repeat this pattern for at least 64000ms+ 15000µs.
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• Trigger the scope to start observation synchronously with the begin of the babbling idiot stimuli. • Trigger the logic state analyzer to start observation synchronously with the begin of the babbling idiot stimuli.
6.3.9.1.5 Postamble • Standard postamble.
6.3.9.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The Go-To-Sleep timeout dStarGoToSleep shall be measured with an error of less than 1%. Hint: uBP and uBM of branch 2 indicate Data_0 state initially, i.e. the active star retransmits the babbling idiot pattern before branch 4 enters Branch_FailSilent . Then, branch 2 enters idle state. • Between 640ms and 64000ms after branch 2 has entered idle state, i.e. uBP and uBM of branch 2 are between 1800mV and 3200mV ( idle ), uBP and uBM of branch 2 shall change to idle_LP state, i.e. uBP and uBM of branch 2 and 4 shall change to a voltage level between -200mV and +200mV ( idle_LP ). • in case of an available INH1 signal uINH1 shall be initially in logical HIGH state for at least 640ms + 1500µs. Between 640ms + 1500µs and 64000ms + 15000µs after the start of the observation, uINH1 shall change to logical LOW state.
6.3.9.1.7 Test Instances Instance 6.3.9.1 6.3.9.2 6.3.9.3
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.10 Mode.Active Star.Low Power.Sleep
6.3.10.1 to 6.3.10.3: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V CC
6.3.10.1.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V CC according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.10.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o External VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
6.3.10.1.3 Preamble (setup state) • Standard preamble.
6.3.10.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set external VCC power supply of active star to VCCUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.10.1.5 Postamble • Standard postamble.
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6.3.10.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state during test execution, except if the node itself is transmitting its pattern, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches. • in case of an available INH1 signal uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep .
6.3.10.1.7 Test Instances Instance 6.3.10.1 6.3.10.2 6.3.10.3
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.10.4 to 6.3.10.5: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V BAT (VCC not implemented)
6.3.10.4.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V BAT in case of V CC is not implemented according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” or the Functional class “Active Star - Internal Voltage Regulator” is not implemented and a V CC supply input is available.
6.3.10.4.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
6.3.10.4.3 Preamble (setup state) • Standard preamble.
6.3.10.4.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set V BAT power supply of active star to VBATUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.10.4.5 Postamble • Standard postamble.
6.3.10.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active
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star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state during test execution, except if the node itself is transmitting its pattern, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches. • INH1 signal uINH1 shall be in logical LOW state not later than 1000ms (dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep .
6.3.10.4.7 Test Instances Instance 6.3.10.4 6.3.10.5
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.10.6 to 6.3.10.7: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V BAT and V CC
6.3.10.6.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V CC and V BAT at the same time according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.10.6.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
6.3.10.6.3 Preamble (setup state) • Standard preamble.
6.3.10.6.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set external VCC power supply of active star to VCCUndervoltage and set V BAT power supply of active star to VBATUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.10.6.5 Postamble • Standard postamble.
6.3.10.6.6 Pass- / Fail Criteria Pass criteria:
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• uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state during test execution, except if the node itself is transmitting its pattern, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches. • uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep .
6.3.10.6.7 Test Instances Instance 6.3.10.6 6.3.10.7
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.11 Mode.Active Star.Low Power.Sleep.Wake-up
6.3.11.1 to 6.3.11.3: Operation mode change from AS_Sleep to AS_Normal (after dStarWakeUpReaction )
6.3.11.1.1 Test Purpose This test checks the ability of the active star to wake-up after a wake-up reaction time of dStarWakeUpReaction and to change the operation mode from AS_Sleep to AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while no stress condition is present.
6.3.11.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.11.1.3 Preamble (setup state) • Sleep preamble. • Interrupt BP and BM of the nodes 21..24 (branch 2) and 11..14 (branch 4).
6.3.11.1.4 Test execution • Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBP at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBM at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.4. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star.
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• Stimulate the bus driver of node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N1_TxEN of node 1.
6.3.11.1.5 Postamble • Standard postamble.
6.3.11.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The wake-up reaction time dStarWakeUpReaction shall be measured with an error of less than 1%. • uBP and uBM of branch 2 and 4 shall indicate idle_LP initially, i.e. uBP and uBM of branch 2 and 4 shall be between -200mV and +200mV ( idle_LP ). After the detection of the remote wake-up event, uBP and uBM of branch 2 and 4 shall indicate idle state, i.e. uBP and uBM of branch 2 and 4 shall change to a voltage level between 1800mV and 3200mV ( idle ) within 100ms. • in case of an available INH1 signal uINH1 shall be in logical LOW state initially. Then, uINH1 shall change to logical HIGH state within 100ms, i.e. after the detection of the remote wake-up event.
6.3.11.1.7 Test Instances Instance 6.3.11.1 6.3.11.2 6.3.11.3
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.11.4 to 6.3.11.6: Operation mode change from AS_Sleep to AS_Normal (re-transmission of wake-up symbols
6.3.11.4.1 Test Purpose This test checks the ability of the active star to re-transmit a sufficient number of received wake-up symbols during the operation mode transition from AS_Sleep to AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while no stress condition is present.
6.3.11.4.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.11.4.3 Preamble (setup state) • Sleep preamble.
6.3.11.4.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 1. • Stimulate the bus driver of node 1 at TP_N1_TxD and TP_N1_TxEN by 32 wake-up patterns, i.e. a sequence of 64 wake-up symbols.
6.3.11.4.5 Postamble • Standard postamble.
6.3.11.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain at least 34 wake-up symbols, i.e. 34 logical low sequences corresponding to the wake-up symbols transmitted by node 1.
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6.3.11.4.7 Test Instances Instance 6.3.11.4 6.3.11.5 6.3.11.6
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.11.7 to 6.3.11.9: Ignore non suitable wake-up patterns (remain in AS_Sleep )
6.3.11.7.1 Test Purpose This test checks the ability of the IUT to ignore non suitable remote wake-up patterns with shortend idle phase and to remain in AS_Sleep mode according to section 8.11 in [01-PL Spec] on page 60 while no stress condition is present.
6.3.11.7.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Single transmitter.
6.3.11.7.3 Preamble (setup state) • Sleep preamble. • Interrupt BP and BM of the nodes 21..24 (branch 2) and 11..14 (branch 4).
6.3.11.7.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBP at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.4. • Observe and acquire uBM at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.4. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the AS. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one non wake-up short idle phase pattern as specified in chapter 5.1.3.10.
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6.3.11.7.5 Postamble • Standard postamble.
6.3.11.7.6 Pass- / Fail Criteria Pass criteria: Hint: the observation shall be at least 100ms, because the IUT may wake-up within this time. • uBP and uBM of branch 2 and 4 shall indicate idle_LP initially, i.e. uBP and uBM of branch 2 and 4 shall be between -200mV and +200mV ( idle_LP ). • In case of an available INH1 signal uINH1 of the AS shall be in logical LOW state (Sleep ) during test execution, i.e. the AS shall remain in AS_Sleep .
6.3.11.7.7 Test Instances Instance 6.3.11.7 6.3.11.8 6.3.11.9
Purpose Stress
Precondition
Configuration Power Supply
Ground Shift
Failure
Preamble
Test Execution … … … Stimulate IUT in Stimulate IUT in Stimulate IUT in node 1 at TP_N1_TxD node 1 at TP_N1_TxD node 1 at TP_N1_TxD and TP_N1_TxEN by and TP_N1_TxEN by and TP_N1_TxEN by one non wake-up short one non wake-up short one non wake-up idle phase pattern as low phase pattern as prolonged pattern as specified in chapter specified in chapter specified in chapter 5.1.3.10. 5.1.3.11 5.1.3.12 … … … Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.11.10 to 6.3.11.12: Operation mode change from AS_Sleep to AS_Normal due to detection of RWU while undervoltage of
VCC
6.3.11.10.1 Test Purpose
This test checks the ability of the IUT to detect a remote wake-up when V CC in undervoltage condition according to section 8.11 on page 60 in [01-PL Spec] and figure 9-4, transition 1 in [01-PL Spec] on page 73. This test case is skipped if the Functional class “Active Star - Voltage Regulator
Control” is not implemented or the V CC supply input is not available.
6.3.11.10.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of the active star: +5.0V. • Ground shift: 0V.
• Failure: V CC in undervoltage condition. • Communication: Single transmitter.
6.3.11.10.3 Preamble (setup state) • Sleep preamble.
• Switch V CC of the AS to external power supplies and set uV CC = VCCUndervoltage . • Interrupt BP and BM of the nodes 21..24 (branch 2) and nodes 11..14 (branch 4).
6.3.11.10.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uBP at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBM at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBP at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uBM at TPAS1_B4 of the transmitting branch 4 according to the observation window described in chapter 6.1.4.5. • Observe and acquire uINH1 at TP_AS_INH1 of the AS.
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• Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N1_TxEN of node 1.
6.3.11.10.5 Postamble • Standard postamble.
6.3.11.10.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The wake-up reaction time dStarWakeUpReaction shall be measured with an error of less than 1%. • uBP and uBM of branch 2 and 4 shall indicate idle_LP initially, i.e. uBP and uBM of branch 2 and 4 shall be between -200mV and +200mV ( idle_LP ). • uINH1 shall be in logical LOW state initially. Then, uINH1 shall change to logical HIGH state within 100ms, i.e. after the detection of the remote wake-up event.
6.3.11.10.7 Test Instances Instance 6.3.11.10 6.3.11.11 6.3.11.12
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V (if V CC impl.)
VBAT = 5.5V (if V CC not impl.)
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.12 Mode.Active Star.Branch.Active
6.3.12.1 to 6.3.12.3: Operating state change from Branch_Idle to Branche_Active
6.3.12.1.1 Test Purpose This test checks the ability of the active star to change its branch mode from Branch_Idle to Branch_Active according to figure 9-5, transition number 1 in [01-PL Spec] while no stress condition is present.
6.3.12.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.12.1.3 Preamble (setup state) • Standard preamble.
6.3.12.1.4 Test execution • Observe and acquire uBus at TPAS1_B1 of the transmitting branch according to the observation window described in chapter 6.1.4.7. • Observe and acquire uBus at TPAS4_B3 of the receiving branch according to the observation window described in chapter 6.1.4.7. • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. • Trigger the scope synchronously with the stimuli at TP_N2_TxD and TP_N2_TxEN of node 2.
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6.3.12.1.5 Postamble • Standard postamble.
6.3.12.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2, i.e. the active star repeats the patterns received at branch 3 at all other branches. • uBus at TPAS1_B1 of the transmitting branch 1 shall be within idle range at the beginning of the observation window, i.e. the absolute bus voltage shall be smaller than 30mV (uBDTx idle ) – the branches are in Branch_Idle state. uBus at TPAS1_B1 shall exceed idle range within 700ns ( dStarDelay + dStarTruncation = 250ns + 450ns) after uBus at TPAS4_B3 has exceeded idle range, i.e. all transmitting branches enter Branch_Active . • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.12.1.7 Test Instances Instance 6.3.12.1 6.3.12.2 6.3.12.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.13 Mode.Active Star.Branch.Idle
6.3.13.1 to 6.3.13.3: Operating state change from Branch_Active to Branche_Idle
6.3.13.1.1 Test Purpose This test checks the ability of the active star to change its branch mode from Branch_Active to Branch_Idle according to figure 9-5, transition number 2 in [01-PL Spec] while no stress condition is present.
6.3.13.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.13.1.3 Preamble (setup state) • Standard preamble.
6.3.13.1.4 Test execution • Observe and acquire uBus at TPAS1_B1 of the transmitting branch according to the observation window described in chapter 6.1.4.7. • Observe and acquire uBus at TPAS4_B3 of the receiving branch according to the observation window described in chapter 6.1.4.7. • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. • Trigger the scope synchronously with the stimuli at TP_N2_TxD and TP_N2_TxEN of node 2.
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6.3.13.1.5 Postamble Standard postamble.
6.3.13.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2, i.e. the active star repeats the patterns received at branch 3 at all other branches. • uBus at TPAS1_B1 of transmitting branch 1 shall exceed idle range while the patterns received at branch 3 are retransmitted, i.e. the absolute bus voltage shall exceed 30mV ( uBDTx idle ) – the branches are in Branch_Active state. uBus at TPAS1_B1y shall re-enter idle range within a timespan of 50ns to 500ns (dIdleDetection min + dStarDelay min to dIdleDetection max + dStarDelay = 50ns + 0ns to 250ns + 250ns) after uBus at TPAS4_B3 has dropped below 30mV ( uBDTx idle ) again, i.e. the receiving branch is in idle state again and all transmitting branches re-enter Branch_Idle after the transmission. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.13.1.7 Test Instances Instance 6.3.13.1 6.3.13.2 6.3.13.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.13.4 to 6.3.13.6: Operating state change from Branch_FailSilent to Branche_Idle
6.3.13.4.1 Test Purpose This test checks the ability of the active star to change its branch mode from Branch_FailSilent to Branch_Idle according to figure 9-5, transition number 4 in [01- PL Spec] while no stress condition is present.
6.3.13.4.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: babbling idiot. • Communication: single transmitter.
6.3.13.4.3 Preamble (setup state) • Standard preamble.
6.3.13.4.4 Test execution • Observe and acquire uTxD at TP_N12_TxD of node 12, TP_N13_TxD of node 13 and TP_N14_TxD of node 14. • Observe and acquire uTxEN at TP_N12_TxEN of node 12, TP_N13_TxEN of node 13 and TP_N14_TxEN of node 14. • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 2. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxEN by one babbling idiot pattern as defined in chapter 6.1.3.1. • After 15000µs from the start of the babbling idiot sequence stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern.
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• 10µs after the end of the babbling idiot sequence stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.13.4.5 Postamble • Standard postamble.
6.3.13.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes except nodes 11..14 (branch 4) shall contain the 50/50 patterns transmitted by node 2 after 15000µs from the start of the babbling idiot sequence, i.e. the active star has switched branch 4 to Branch_FailSilent within the maximal noise detection timeout of dBranchActive max = 15000µs and has excluded this branch from communication. • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by node 2 after the end of the babbling idiot sequence, i.e. the active star switches branch 4 back to Branch_Idle within the failure recovery timeout of dBranchFailSilentIdle ≤ 10µs. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.13.4.7 Test Instances Instance 6.3.13.4 6.3.13.5 6.3.13.6
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.14 Mode.Active Star.Branch.FailSilent
6.3.14.1 to 6.3.14.3: Operating state change from Branch_Active to Branch_FailSilent
6.3.14.1.1 Test Purpose This test checks the parameter dBranchActive and the ability of the active star to change its branch mode from Branch_Active to Branch_FailSilent according to figure 9-5, transition number 3 in [01-PL Spec] while no stress condition is present.
6.3.14.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: babbling idiot. • Communication: none.
6.3.14.1.3 Preamble (setup state) • Standard preamble.
6.3.14.1.4 Test execution • Observe and acquire uBus at TPAS1_B2 of the transmitting branch 2 according to the observation window described in chapter 6.1.4.8. • Observe and acquire uBus at TPAS4_B4 of the receiving branch 4 according to the observation window described in chapter 6.1.4.8. • Observe and acquire uTxD at TP_N12_TxD of node 12, TP_N13_TxD of node 13 and TP_N14_TxD of node 14. • Observe and acquire uTxEN at TP_N12_TxEN of node 12, TP_N13_TxEN of node 13 and TP_N14_TxEN of node 14. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxEN by one babbling idiot pattern as defined in chapter 6.1.3.1.
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6.3.14.1.5 Postamble • Standard postamble.
6.3.14.1.6 Pass- / Fail Criteria Pass criteria: • uBus of all observed transmitting branches shall change to Data_0 state, i.e. uBus shall raise above 600mV ( uBDTx active ), and shall remain in Data_0 state for at least 1500µs and not more than 15000µs and shall return to idle state afterwards, i.e. the absolute bus voltage shall no more exceed 30mV ( uBDTx idle ). This means than the active star shall switch branch 4 from Branch_Active to Branch_FailSilent within the allowed range of the noise detection timeout of dBranchActive min = 1500µs to dBranchActive max = 15000µs. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
6.3.14.1.7 Test Instances Instance 6.3.14.1 6.3.14.2 6.3.14.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.15 Failure.Loss
6.3.15.1 Interruption of V CC (V BAT implemented)
6.3.15.1.1 Test Purpose
This test checks the behaviour of the active star in case of loss of the V CC supply
power if V BAT is still available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: loss of V CC . • Communication: matrix A (round robin test).
6.3.15.1.3 Preamble (setup state) • Standard preamble.
6.3.15.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Interrupt supply wire V CC of the active star according to chapter 3.5.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC (undervoltage condition). • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.1.5 Postamble • Standard postamble.
6.3.15.1.6 Pass- / Fail Criteria Pass criteria:
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• uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches. • uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the loss of V CC , i.e. the active star shall enter AS_Sleep .
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6.3.15.2 Interruption of V CC (V BAT not implemented)
6.3.15.2.1 Test Purpose
This test checks the behaviour of the active star in case of loss of the V CC supply
power if V BAT is not implemented according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is implemented.
6.3.15.2.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: loss of V CC . • Communication: matrix A (round robin test).
6.3.15.2.3 Preamble (setup state) • Standard preamble.
6.3.15.2.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes.
• Interrupt supply wire V CC of the active star according to chapter 3.5.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC . • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.2.5 Postamble • Standard postamble.
6.3.15.2.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active
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star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
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6.3.15.3 Interruption of V BAT (V CC implemented)
6.3.15.3.1 Test Purpose
This test checks the behaviour of the active star in case of loss of the V BAT supply power if V CC is still available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.3.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• External V CC power supply of AS: +5.0V • Ground shift: 0V.
• Failure: loss of V BAT . • Communication: single transmitter.
6.3.15.3.3 Preamble (setup state) • Standard preamble.
6.3.15.3.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1, 12 and 23.
• Interrupt supply wire V BAT of the active star according to chapter 3.5. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by ten 38 10Bit Low patterns. Repeat this sequence with a pause between the messages of 20µs for at least 1000ms to verify that communication is not disturbed even after the maximal undervoltage detection timeout ( dUV ).
6.3.15.3.5 Postamble • Standard postamble.
6.3.15.3.6 Pass- / Fail Criteria Pass criteria: Hint: This test case requires acquisition of at least 1000ms by the logic state analyzer. A bit level resolution is not required.
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• uRxD of all observed nodes shall contain all logical LOW sequences transmitted by node 2, i.e. the active star shall not enter AS_Sleep mode and shall retransmit all patterns received on branch 3.
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6.3.15.4 Interruption of V BAT (V CC not implemented)
6.3.15.4.1 Test Purpose
This test checks the behaviour of the active star in case of loss of the V BAT supply power if V CC is not implemented according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Internal Voltage
Regulator” is not implemented or a V CC supply input is although available.
6.3.15.4.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default. • Ground shift: 0V.
• Failure: loss of V BAT . • Communication: matrix A (round robin test).
6.3.15.4.3 Preamble (setup state) • Standard preamble.
6.3.15.4.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Interrupt supply wire V BAT of the active star according to chapter 3.5.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V BAT . • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.4.5 Postamble • Standard postamble.
6.3.15.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active
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star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
• uINH1 shall break down to logical LOW state after the loss of V BAT , i.e. the active star shall shut down.
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6.3.15.5 Interruption of V BAT and V CC
6.3.15.5.1 Test Purpose
This test checks the behaviour of the active star in case of loss of the V CC and V BAT supply power if both supply inputs are available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.5.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: loss of V CC and V BAT . • Communication: matrix A (round robin test).
6.3.15.5.3 Preamble (setup state) • Standard preamble.
6.3.15.5.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Interrupt supply wires V CC and V BAT of the active star according to chapter 3.5.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC and V BAT . • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.5.5 Postamble • Standard postamble.
6.3.15.5.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active
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star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
• uINH1 shall break down to logical LOW state after the loss of V CC and VBAT , i.e. the active star shall shut down.
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6.3.15.6 GND unconnected
6.3.15.6.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected GND connection of the IUT according to table 8-27 in [01-PL Spec].
6.3.15.6.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: GND of IUT unconnected. • Communication: single transmitter.
6.3.15.6.3 Preamble (setup state) • Switch GND connection of all IUTs in the AS to unconnected according to Figure 3-9 and Table 3-4, failure FL15. • Standard preamble.
6.3.15.6.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uBus at TPAS1_B1 of the transmitting branch of the AS according to the observation window described in chapter 5.1.4.2 but with a length of 52µs. • Observe and acquire uBus at TPAS4_B3 of the receiving branch of the AS according to the observation window described in chapter 5.1.4.2 but with a length of 52µs. • Stimulate node 2 at TP_N2_TxD and TP_N2_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
6.3.15.6.5 Postamble • Standard postamble.
6.3.15.6.6 Pass- / Fail Criteria Pass criteria:
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• uBus of branch 1 of the AS shall be in idle range | uBus |<30mV.
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6.3.15.7 VCC = 0V (V BAT available)
6.3.15.7.1 Test Purpose
This test checks the behaviour of the active star in case of VCC =0V supply power if
VBAT is still available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.7.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: V CC =0V according to Figure 3-5 and Table 3-4, failure FL23. • Communication: matrix A (round robin test).
6.3.15.7.3 Preamble (setup state) • Standard preamble.
6.3.15.7.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set supply V CC of the active star according to chapter 3.5 to 0V.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC (undervoltage condition). • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.7.5 Postamble • Standard postamble.
6.3.15.7.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active
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star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches. • uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the loss of V CC , i.e. the active star shall enter AS_Sleep .
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6.3.15.8 VCC = 0V (V BAT not available)
6.3.15.8.1 Test Purpose
This test checks the behaviour of the active star in case of VCC =0V supply power if
VBAT is not implemented according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is implemented.
6.3.15.8.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: V CC =0V according to Figure 3-5 and Table 3-4, failure FL23. • Communication: matrix A (round robin test).
6.3.15.8.3 Preamble (setup state) • Standard preamble.
6.3.15.8.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes.
• Set supply VCC of the active star according to chapter 3.5 to 0V.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC . • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.8.5 Postamble • Standard postamble.
6.3.15.8.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active
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star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
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6.3.15.9 VBAT = 0V (V CC available)
6.3.15.9.1 Test Purpose
This test checks the behaviour of the active star in case of VBAT =0V supply power if
VCC is still available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.9.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• External V CC power supply of AS: +5.0V • Ground shift: 0V.
• Failure: V BAT =0V according to Figure 3-5 and Table 3-4, failure FL22. • Communication: single transmitter.
6.3.15.9.3 Preamble (setup state) • Standard preamble.
6.3.15.9.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1, 12 and 23.
• Set supply V BAT of the active star according to chapter 3.5 to 0V. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by ten 39 10Bit Low patterns. Repeat this sequence with a pause between the messages of 20µs for at least 1000ms to verify that communication is not disturbed even after the maximal undervoltage detection timeout ( dUV ).
6.3.15.9.5 Postamble • Standard postamble.
6.3.15.9.6 Pass- / Fail Criteria Pass criteria: Hint: This test case requires acquisition of at least 1000ms by the logic state analyzer. A bit level resolution is not required.
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• uRxD of all observed nodes shall contain all logical LOW sequences transmitted by node 2, i.e. the active star shall not enter AS_Sleep mode and shall retransmit all patterns received on branch 3.
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6.3.15.10 VBAT = 0V (V CC not available)
6.3.15.10.1 Test Purpose
This test checks the behaviour of the active star in case of VBAT =0V supply power if
VCC is not implemented according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Internal Voltage
Regulator” is not implemented or a V CC supply input is although available.
6.3.15.10.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default. • Ground shift: 0V.
• Failure: V BAT =0V according to Figure 3-5 and Table 3-4, failure FL22. • Communication: matrix A (round robin test).
6.3.15.10.3 Preamble (setup state) • Standard preamble.
6.3.15.10.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set supply V BAT of the active star according to chapter 3.5 to 0V.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V BAT • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.10.5 Postamble • Standard postamble.
6.3.15.10.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active
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star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
• uINH1 shall break down to logical LOW state after the loss of V BAT , i.e. the active star shall shut down.
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6.3.15.11 VBAT =0V, V CC = 0V
6.3.15.11.1 Test Purpose
This test checks the behaviour of the active star in case of V CC =0V and V BAT =0V supply power if both supply inputs are available according to section 9.2.3 Active star – power supply interface in [01-PL Spec] while no other stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
6.3.15.11.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of active star: default.
• VCC power supply of active star: +5.0V. • Ground shift: 0V.
• Failure: V CC =0V and V BAT =0V according to Figure 3-5 and Table 3-4, failure FL24. • Communication: matrix A (round robin test).
6.3.15.11.3 Preamble (setup state) • Standard preamble.
6.3.15.11.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 of the active star.
• Set supplies V CC and V BAT of the active star according to chapter 3.5 to 0V.
• Wait 1000ms ( dUV ) to let the active star detect the loss of V CC and V BAT . • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.15.11.5 Postamble • Standard postamble.
6.3.15.11.6 Pass- / Fail Criteria Pass criteria: • uRxD of nodes 11..14 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 11..14 only, i.e. the active
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star shall not disturb the communication on the passive bus (branch 4) and shall not retransmit patterns received on other branches. • uRxD of nodes 21..24 except the corresponding transmitting node shall contain the 50/50 patterns transmitted by nodes 21..24 only, i.e. the active star shall not disturb the communication on the passive star (branch 2) and shall not retransmit patterns received on other branches. • uRxD of nodes 1 and 2 shall be in logical HIGH state if other nodes are stimulated to transmit, i.e. the active star shall not disturb branch 1 and branch 3 and shall not retransmit patterns received on other branches.
• uINH1 shall break down to logical LOW state after the loss of V CC and VBAT , i.e. the active star shall shut down.
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6.3.16 Dynamic Low Battery Voltage
6.3.16.1 to 6.3.16.2: Dynamic low battery occuring in AS_Normal mode
6.3.16.1.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in AS_Normal mode. Hint: This test case intends to test the capability of the active star to return to the operating state that was active before the dynamic low battery pulse. This test case is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC voltage regulator (the battery voltage) is stressed by the dynamic low battery voltage pulse.
6.3.16.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: 11.6V.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: 11.6V. • Ground shift: 0V. • Failure: none. • Communication: matrix A (round robin test).
• Test signal: U S/tf1 as specified in chapter 3.4.
6.3.16.1.3 Preamble (setup state) • Standard preamble.
6.3.16.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of all nodes. • Observe and acquire uTxEN at TP_Nx_TxEN of all nodes. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus drivers of the transmitting nodes according to the sequence described on matrix A at TP_Nx_TxD and TP_Nx_TxEN by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low
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battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
6.3.16.1.5 Postamble • Standard postamble.
6.3.16.1.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC voltage regulator is present: o uRxD of all nodes except the corresponding transmitting node shall contain all 50/50 patterns transmitted by all nodes (according to uTxD and uTxEN of all nodes), i.e. all data shall be retransmitted by the active star. o in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH.
6.3.16.1.7 Test Instances Instance 6.3.16.1 6.3.16.2
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.16.3 to 6.3.16.4: Dynamic low battery occuring in AS_Sleep mode
6.3.16.3.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in AS_Sleep mode. Hint: This test case intends to test the capability of the active star to return to the operating state that was active before the dynamic low battery pulse. This test case is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC voltage regulator (the battery voltage) is stressed by the dynamic low battery voltage pulse.
6.3.16.3.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: 11.6V.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: 11.6V. • Ground shift: 0V. • Failure: none. • Communication: none.
• Test signal: U S/t f1 as specified in chapter 3.4.
6.3.16.3.3 Preamble (setup state) • Sleep preamble. • Stimulate bus drivers in all nodes via host command to enter BD_Sleep .
6.3.16.3.4 Test execution • Observe and acquire uBP at TPASx_B2 of branch 2 according to the observation window described in chapter 6.1.4.9. • Observe and acquire uBM at TPASx_B2 of branch 2 according to the observation window described in chapter 6.1.4.9. • Observe and acquire uBP at TPASx_B4 of branch 4 according to the observation window described in chapter 6.1.4.9. • Observe and acquire uBM at TPASx_B4 of branch 4 according to the observation window described in chapter 6.1.4.9. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star.
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• Trigger the dynamic low battery voltage pulse. • Trigger scope observation synchonously with the dynamic low battery voltage pulse.
6.3.16.3.5 Postamble • Standard postamble.
6.3.16.3.6 Pass- / Fail Criteria Pass criteria: • uBP and uBM of branch 2 and 4 shall be in idle_LP state, i.e. shall have a voltage level between -200mV and +200mV ( idle_LP ). • in case of an available INH1 signal uINH1 of the active star shall be in logical LOW.
6.3.16.3.7 Test Instances Instance 6.3.16.3 6.3.16.4
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.17 Failure.Short Circuit Bus Wires
6.3.17.1 to 6.3.17.2: Short circuit bus wires to GND
6.3.17.1.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to GND. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
6.3.17.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to GND. • Communication: single transmitter.
6.3.17.1.3 Preamble (setup state) • Standard preamble.
6.3.17.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of node 1 and 2. • Observe and acquire uTxEN at TP_Nx_TxEN of node 1 and 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1 and 2.
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• Observe and acquire iBP GNDShortMax at TP_AS_B1_RiBP of the AS (shall be at TPAS1_B1 ). • Short circuit BP (failure FL11) of the AS to GND at TPAS2_B1 . • Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and TP_N2_TxEN by a short circuit pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples were taken by the data aquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 2. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL11) of the AS at TPAS2_B1 . Wait at least 12 seconds. • Stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.17.1.5 Postamble • Standard postamble.
6.3.17.1.6 Pass- / Fail Criteria Pass criteria:
• |iBP GNDShortMax | ≤ 100mA. • After switching off the failure the IUT in node 1 must receive the patterns and signal them accordingly: o TP_N1_RxD of node1 as stimulated at TP_N2_TxD at node 2. o In case RxEN is implemented TP_N1_RxEN of node 1 as stimulated at TP_N2_TxEN at node 2. • After switching off the failure the IUT in node 2 must receive the patterns and signal them accordingly: o TP_N2_RxD of node2 as stimulated at TP_N1_TxD at node 1. o In case RxEN is implemented TP_N2_RxEN of node 2 as stimulated at TP_N1_TxEN at node 1.
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6.3.17.1.7 Test Instances Instance 6.3.17.1 6.3.17.2
Purpose Stress S/C BP to GND at AS S/C BM to GND at AS
Precondition
Configuration Power Supply
Ground Shift
Failure
Preamble
Test Execution … …
Observe and acquire iBP GNDShortMax Observe and acquire iBM GNDShortMax
at TP_AS_B1_R iBP of the AS (shall at TP_AS_B1_RiBM of the AS (shall be at TPAS1_B1 ). be at TPAS1_B1 ).
Short circuit BP (failure FL11) of the Short circuit BM (failure FL12) of the AS to GND at TPAS2_B1 . AS to GND at TPAS2_B1
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL11) of the AS at TPAS2_B1 . Wait FL12) of the AS at TPAS2_B1 . Wait at least 12 seconds. at least 12 seconds
… …
Pass/Fail Criteria |iBPGNDShortMax | ≤ 100mA. |iBM GNDShortMax | ≤ 100mA.
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.17.3 to 6.3.17.4: Short circuit bus wires to V BAT
6.3.17.3.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to +48V 40 . Additionally it is checked that the IUT is not permanently damaged by the short circuit.
6.3.17.3.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 24: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
o VCC power supply of all nodes: +5.0V.
o External V CC power supply of IUT in node 23, 24 and AS: +5.0V.
• In case that only V BAT is implemented:
o VBAT power supply of all nodes: default.
o External V BAT power supply of IUT in node 23, 24 and AS: default.
• In case of an available V IO supply input:
o VIO power supply of all nodes: depends on implementation.
o External V IO power supply of IUT in node 23, 24 and AS: depends on implementation • Ground shift: 0V. • Failure: S/C BP to +48V 40 . • Communication: Node 1 and 2 as transmitter.
6.3.17.3.3 Preamble (setup state) • Standard preamble.
6.3.17.3.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of node 1 and 2. • Observe and acquire uTxEN at TP_Nx_TxEN of node 1 and 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1 and 2. 41 42 • Observe and acquire iBP BAT48ShortMax or iBP BAT27ShortMax at TP_AS_B1_RiBP of the AS (shall be at TPAS1_B1 ).
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• Short circuit BP (failure FL13) of the AS to +48V 40 at TPAS2_B1 . • Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and TP_N2_TxEN by a short circuit pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples were taken by the data aquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 2. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL13) of the AS at TPAS2_B1 . Wait at least 12 seconds. • Stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.17.3.5 Postamble • Standard postamble.
6.3.17.3.6 Pass- / Fail Criteria Pass criteria:
• In case the IUT does not support 42V systems: |iBP BAT27ShortMax | ≤ 100mA.
• In case the IUT does support 42V systems: |iBP BAT48ShortMax | ≤ 120mA. • After switching off the failure the IUT in node 1 must receive the patterns and signal them accordingly: o TP_N1_RxD of node1 as stimulated at TP_N2_TxD at node 2. o In case RxEN is implemented TP_N1_RxEN of node 1 as stimulated at TP_N2_TxEN at node 2. • After switching off the failure the IUT in node 2 must receive the patterns and signal them accordingly: o TP_N2_RxD of node2 as stimulated at TP_N1_TxD at node 1. o In case RxEN is implemented TP_N2_RxEN of node 2 as stimulated at TP_N1_TxEN at node 1.
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6.3.17.3.7 Test Instances Instance 6.3.17.3 6.3.17.4
Purpose Stress S/C BP to +48V at AS S/C BM to +48V at AS
Precondition
Configuration Power Supply
Ground Shift
40 40 Failure S/C BP to +48V S/C BM to +48V
Preamble
Test Execution … …
Observe and acquire Observe and acquire 43 44 43 44 iBP BAT48ShortMax or iBP BAT27ShortMax iBM BAT48ShortMax or iBM BAT27ShortMax
at TP_AS_B1_R iBP of the AS (shall at TP_AS_B1_RiBM of the AS (shall be at TPAS1_B1 ). be at TPAS1_B1 ).
Short circuit BP (failure FL13) of the Short circuit BM (failure FL14) of the AS to +48V 40 at TPAS2_B1 . AS to +48V 40 at TPAS2_B1
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL13) of the AS at TPAS2_B1 . Wait FL14) of the AS at TPAS2_B1 . Wait at least 12 seconds. at least 12 seconds
… …
Pass/Fail Criteria In case the IUT does not support In case the IUT does not support 42V systems: 42V systems:
|iBP BAT27ShortMax | ≤ 100mA. |iBM BAT27ShortMax | ≤ 100mA
In case the IUT does support 42V In case the IUT does support 42V
systems: | iBP BAT48ShortMax | ≤ 120mA. systems: | iBM BAT48ShortMax | ≤ 120mA
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.17.5 to 6.3.17.6: Short circuit bus wires to -5V
6.3.17.5.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of the bus wire to -5V. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
6.3.17.5.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: S/C BP to -5V. • Communication: Node 1 and 2 as transmitter.
6.3.17.5.3 Preamble (setup state) • Standard preamble.
6.3.17.5.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of node 1 and 2. • Observe and acquire uTxEN at TP_Nx_TxEN of node 1 and 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1 and 2.
• Observe and acquire iBP -5VShortMax at TP_AS_B1_RiBP of the AS (shall be at TPAS1_B1 ). • Short circuit BP (failure FL19) of the AS to -5V at TPAS2_B1 . • Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and TP_N2_TxEN by a short circuit pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples were taken by the data aquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 2. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP (failure FL19) of the AS at TPAS2_B1 . Wait at least 12 seconds.
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• Stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.17.5.5 Postamble • Standard postamble.
6.3.17.5.6 Pass- / Fail Criteria Pass criteria:
• |iBP -5VShortMax | ≤ 100mA. • After switching off the failure the IUT in node 1 must receive the patterns and signal them accordingly: o TP_N1_RxD of node1 as stimulated at TP_N2_TxD at node 2. o In case RxEN is implemented TP_N1_RxEN of node 1 as stimulated at TP_N2_TxEN at node 2. • After switching off the failure the IUT in node 2 must receive the patterns and signal them accordingly: o TP_N2_RxD of node2 as stimulated at TP_N1_TxD at node 1. o In case RxEN is implemented TP_N2_RxEN of node 2 as stimulated at TP_N1_TxEN at node 1.
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6.3.17.5.7 Test Instances Instance 6.3.17.5 6.3.17.6
Purpose Stress S/C BP to -5V at AS S/C BM to -5V at AS
Precondition
Configuration Power
Supply
Ground
Shift
Failure S/C BP to -5V S/C BM to -5V
Preamble
Test Execution … …
Observe and acquire iBP -5VShortMax at Observe and acquire iBM -5VShortMax at
TP_AS_B1_R iBP of the AS (shall be TP_AS_B1_RiBM of the AS (shall be at TPAS1_B1 ). at TPAS1_B1 ).
Short circuit BP (failure FL19) of the Short circuit BM (failure FL20) of the AS to -5V at TPAS2_B1 . AS to -5V at TPAS2_B1
… …
Switch off short circuit BP (failure Switch off short circuit BM (failure FL19) of the AS at TPAS2_B1 . Wait FL20) of the AS at TPAS2_B1 . Wait at least 12 seconds. at least 12 seconds
… …
Pass/Fail Criteria |iBP -5VShortMax | ≤ 100mA. |iBM -5VShortMax | ≤ 100mA
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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6.3.17.6 S/C BP to BM at AS
6.3.17.6.1 Test Purpose This test checks the ability of the IUT to limit the absolute current in case of a short circuit of both bus wires. Additionally it is checked that the IUT is not permanently damaged by the short circuit.
6.3.17.6.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: S/C BM to -5V. • Communication: Node 1 and 2 as transmitter.
6.3.17.6.3 Preamble (setup state) • Standard preamble.
6.3.17.6.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of node 1 and 2. • Observe and acquire uTxEN at TP_Nx_TxEN of node 1 and 2. • Observe and acquire uRxD at TP_Nx_RxD of node 1 and 2.
• Observe and acquire iBM BPShortMax at TP_AS_B1_R iBM of the AS (shall be at TPAS1_B1 ). • Short circuit BP to BM (failure FL21) of the AS at TPAS2_B1 . • Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and TP_N2_TxEN by a short circuit pattern according to chapter 5.1.3.9. Repeat this sequence until at least 500 samples were taken by the data aquisition unit. • Trigger the data aquisition unit to start the measurement 100µs after the stimuli at node 2. Aquire at least 500 samples, while the IUT transmits Data_0 , Idle and Data_1 . • Switch off short circuit BP to BM (failure FL21) of the AS at TPAS2_B1 . Wait at least 12 seconds.
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• Stimulate IUT in node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by one 50/50 pattern. Wait 500µs. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by one 50/50 pattern.
6.3.17.6.5 Postamble • Standard postamble.
6.3.17.6.6 Pass- / Fail Criteria Pass criteria:
• |iBM BPShortMax | ≤ 100mA. • After switching off the failure the IUT in node 1 must receive the patterns and signal them at TP_N1_RxD and TP_N1_RxEN that are stimulated at TP_N2_TxD and TP_N2_TxEN of node 2. • After switching off the failure the IUT in node 2 must receive the patterns and signal them at TP_N2_RxD and TP_N2_RxEN that are stimulated at TP_N1_TxD and TP_N1_TxEN of node 1.
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6.3.18 Dynamic Ground Shift
6.3.18.1 Receiveability of test pattern during ground shift at transmitter
6.3.18.1.1 Test Purpose This test checks the ability of the AS to receive a test pattern while dynamic ground shift is present at the transmitter.
6.3.18.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: Node 23 as transmitter.
6.3.18.1.3 Preamble (setup state) • Standard preamble.
6.3.18.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N23_TxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N2_RxD of node 2 according to the observation window described in chapter 5.1.4.5. • Observe and acquire the dynamic ground shift pulse at TP_AS_UGS applied to node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate the bus driver of the transmitting node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
6.3.18.1.5 Postamble
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• Standard postamble.
6.3.18.1.6 Pass- / Fail Criteria Pass criteria: • Node 2 shall receive all patterns transmitted by node 23, i.e. the dynamic ground shift in the receiving branch of the active star shall not disturb the communication.
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6.3.18.2 Receiveability of test pattern during ground shift at the AS
6.3.18.2.1 Test Purpose This test checks the ability of the IUT to receive and re-transmit a test pattern while dynamic ground shift is present at the AS.
6.3.18.2.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at the AS. • Failure: None. • Communication: Node 23 as transmitter.
6.3.18.2.3 Preamble (setup state) • Standard preamble.
6.3.18.2.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N23_TxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire the dynamic ground shift pulse at TP_AS_UGS applied to node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate the bus driver of the transmitting node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
6.3.18.2.5 Postamble • Standard postamble.
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6.3.18.2.6 Pass- / Fail Criteria Pass criteria: • All observed nodes shall receive all patterns transmitted by node 23, i.e. the dynamic ground shift at the active star shall not disturb the communication.
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6.3.18.3 Re-transmitting of test pattern during ground shift at the receiver
6.3.18.3.1 Test Purpose This test checks the ability of the IUT to receive and transmit a test pattern while dynamic ground shift is present at the receiver.
6.3.18.3.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: Node 2 as transmitter.
6.3.18.3.3 Preamble (setup state) • Standard preamble.
6.3.18.3.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N2_TxEN of node 2 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire the dynamic ground shift pulse at TP_AS_UGS applied to node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate the bus driver of the transmitting node 2 at TP_N2_TxD and TP_N2_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
6.3.18.3.5 Postamble • Standard postamble.
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6.3.18.3.6 Pass- / Fail Criteria Pass criteria: • Node 23 shall receive all patterns transmitted by node 2, i.e. the dynamic ground shift in the transmitting branch of the active star shall not disturb the communication.
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6.3.19 Eye Diagram
6.3.19.1 Eye diagram at receiver
6.3.19.1.1 Test Purpose This test checks the eye diagram at the receiver according to the eye diagram chapter 7.4 in [01-PL Spec]. In this test case the bandwidth of the oscilloscope shall be limited to 20MHz.
6.3.19.1.2 Configuration • Topology: as specified in previous configuration section 6.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
6.3.19.1.3 Preamble (setup state) • Standard preamble.
6.3.19.1.4 Test execution • Limit the bandwidth of the oscilloscope to 20MHz. • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uBus at TP4_N2 of node 2 according to the observation window described in chapter 5.1.4.6. • Stimulate the bus driver of the transmitting node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by ten 50/50 patterns.
6.3.19.1.5 Postamble • Standard postamble.
6.3.19.1.6 Pass- / Fail Criteria Pass criteria:
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• The eye diagram obtained with the observed and acquired uBus signal at TP4_N2 of node 2 at the transmitting branch 3 of the AS shall not violate the mask of TP4 defined in Figure 7-4 in [01-PL Spec].
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6.4 Test procedures
6.4.1 Delay
PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS .IDCPowerSupplyConfig.Output() * PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetGroundShift() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() ** PatternGenerator.IPatternGenerator.CreateParticularPattern() ** Scope.IConfiguration.Configure() Scope.IConfiguration.Acquisition() Scope.IConfiguration.Channel() Scope.IConfiguration.Trigger() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only. ** * Some test cases require particular patterns, the other ones standard patterns.
Figure 6-17: Test Procedure for Delay Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS .IDCPowerSupplyConfig.Output() * PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetGroundShift() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() ** Scope.IConfiguration.Acquisition() ** Scope.IConfiguration.Channel() ** Scope.IConfiguration.Trigger() ** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate() **
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() ** NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only. ** * Test cases with oscilloscope acquisition, only.
Figure 6-18: Test Procedure for Truncation Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS .IDCPowerSupplyConfig.Output() ** PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) ** NetServices.ISwitch.SetGroundShift() ** PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() *** PatternGenerator.IPatternGenerator.CreateParticularPattern() *** Scope.IConfiguration.Configure() **** Scope.IConfiguration.Acquisition() **** Scope.IConfiguration.Channel() **** Scope.IConfiguration.Trigger() **** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate() ****
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() ***** PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() *****
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() **** NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
****** Test cases with alternative power supply configuration, only. ** **** Test cases with ground shift, only. *** *** Some test cases require particular patterns, the other ones standard patterns. **** ** Test cases with oscilloscope acquisition, only. ***** * Test cases with alternative power supply output change during test execution, only.
Figure 6-19: Test Procedure for Mode Test Cases
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6.4.4 Failure
PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true) NetServices.ISwitch.SetInterruptionOnBoard() PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() Scope.IConfiguration.Acquisition() Scope.IConfiguration.Channel() Scope.IConfiguration.Trigger() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
Scope.AcquireBusData.GetWaveform() NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
Figure 6-20: Test Procedure for Failure Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.DynamicLowBattery() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() * PatternGenerator.IPatternGenerator.Configure() ** PatternGenerator.IPatternGenerator.CreateComposedPattern() ** Scope.IConfiguration.Configure() *** Scope.IConfiguration.Acquisition() *** Scope.IConfiguration.Channel() *** Scope.IConfiguration.Trigger() *** LogicAnalyzer.ILogicAnalyzer.Configure() **** NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate() ***
PowerSupply_VBAT .IBatterySupplyConfig.InitiateArbitraryFunction()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest() NetServices.IControl.SetOperatingMode() *****
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() *** NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
***** Test cases with alternative power supply configuration, only. ** *** Required for setup state in some test cases, only. *** ** Test cases with oscilloscope acquisition, only. **** * In some test cases required for observation of pattern generator, only. ***** Test cases with op-mode change during test execution, only.
Figure 6-21: Test Procedure for Dynamic Low Battery Test Cases
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7 Test Cases for Active Stars with CC Interface These test cases apply to active stars with communication controller interface or bus guardian interface, only. This test case chapter is skipped if neither the Functional class “Active Star - Communication Controller Interface” nor the Functional class “Active Star - Bus Guardian Interface” is implemented.
7.1 Configuration
7.1.1 Topology The topology corresponds to chapter 6.1.1.
7.1.2 Test planes
7.1.2.1 Analog signals The test planes at the FlexRay active star for analog signal measurement are specified as:
Transmitter Active Star Receiver
BD AS BD Receiving Branch Receiving TransmittingBranch
TPAS3_By TPAS4_ByTPAS1_By TPAS2_By
Figure 7-1: Test Planes @ the analog Interface
TP Name Signals Description
TPAS1_By 45 uBus Differential bus signal of the transmitting branch, as close as possible to the IUT
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TP Name Signals Description
TPAS4_By 45 uBus Differential bus signal of the receiving branch, as close as possible to the IUT
Table 7-1: Test Planes @ the analog Interface The naming of the branches corresponds to chapter 6.1.2.1.
7.1.2.2 Digital signals The test planes at the FlexRay active star for digital signals are specified as:
TxEN TxD RxEN RxD BGE INH1 IUT
Figure 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer
TP Name Signals Description
TP_AS_TxD TxD Transmit Data signal of the IUT
TP_AS_TxEN TxEN Transmit Enable Not signal of the IUT
TP_AS_RxD RxD Receive Data signal of the IUT
TP_AS_BGE BGE Bus Guardian Enable signal of the IUT (optional)
TP_AS_RxEN RxEN Receive Enable Not signal of the IUT (optional)
TP_AS_INH1 INH1 Inhibit signal of the IUT (optional)
Table 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer
7.1.2.3 Naming convention This chapter corresponds to chapter 5.1.2.3 where “Nx ” shall be read as “ AS ”.
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7.1.3 Test patterns This chapter corresponds to chapters 5.1.3 and 6.1.3.
7.1.4 Observation windows This chapter corresponds to chapter 5.1.3.10 where “ BD ” shall be read as “ AS ”.
7.1.5 Operation modes of the AS This chapter corresponds to chapter 6.1.5.
7.1.6 Power supplies This chapter corresponds to chapter 6.1.6.
7.1.7 Stress This chapter corresponds to chapter 6.1.7.
7.1.8 Failures Failures of the AS are also described in chapter 3.5.
7.1.9 Optional features The following features are optional as specified in [01-PL Spec] and must be tested in the test cases if available in the IUT:
7.1.9.1 Functional class “Active Star - Communication Controller Interface” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: o Signal RxD o Signal TxD
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o Signal TxEN
7.1.9.2 Functional class “Active Star - Bus Guardian Interface” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: o Signal RxEN o Signal BGE
7.1.9.3 Functional class “Active Star - Voltage Regulator Control” • This Functional Class groups the following optional features, that must all be implemented, if one of them is present in the IUT: o Signal INH1
o Power supply input VBAT
7.1.9.4 Functional class “Active Star - Internal Voltage Regulator”
• This Functional Class comprises the implementation of a “V BAT ” power supply input and requires that the AS is fully operational without a V CC supply. 7.1.10 Definition of communication Matrix F: (round robin test only with terminated node): In some test instances it is necessary that every terminated node and the AS are the transmitter and all other terminated nodes and the AS are the receivers. This matrix is used for observation of bus signals.
Message from Node x and AS
Transmitters 1 2 AS 12 23 t
Receivers *) *) *) *) *) t *) all terminated nodes except the transmitter
Figure 7-3: Communication Matrix F Pause between the messages: 20µs.
Active Star as transmitter: In some test instances it is necessary that the AS is the transmitter (digital interface) and all other terminated nodes are the receivers.
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This communication is used for testing the digital interface.
Message from Node
Transmitter AS
t
Receivers All
t
Figure 7-4: Communication Active Star as transmitter (Timing)
1
Transmitter Point of Observation 11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Figure 7-5: Communication Active Star as transmitter (Topology)
Single transmitter In some test cases only one transmitter is required to stimulate one receiving branch of the active star:
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1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter
Figure 7-6: Communication Single Transmitter
Node 1 and AS as transmitter In some test cases node 1 and the AS are required for collision scenarios in the AS:
Message
Transmitters AS, N1 t
Receivers All
t
Figure 7-7: Communication Node 1 and AS (Timing)
1
Transmitters
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
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Figure 7-8: Communication Node 1 and AS (Topology)
Node 23 as transmitter: In this communication node 23 is the transmitter.
Message from Node
Transmitter 23
t
Figure 7-9: Communication with Node 23 as Transmitter (Time Diagram)
1
11
PS 2 AS 4
3
24 23 22 21 2 14 13 12 11
Transmitter
Figure 7-10: Communication with Node 23 as Transmitter (Topology)
7.1.11 Standard preamble 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD of all nodes shall be in logical HIGH (idle) state. 6. In case a BGE signal is available, this signal shall be in logical HIGH state in all nodes.
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7. Stimulate bus drivers of all nodes via host command to enter BD_Normal . 8. Make sure that the active star is in AS_Normal mode when this preamble is left and the test execution is entered, e.g. by switching on the power supply of the active star just before the end of the preamble.
7.1.12 Sleep preamble 1. Switch on power supplies and initialize them according to the values defined for each test case in the configuration. 2. Set ground shift and initialize it according to the values defined for each test case in the configuration. 3. Set failure and initialize it according to the values defined for each test case in the configuration. 4. Wait for 500ms in order to have a stable failure condition. 5. TxEN and TxD of all nodes shall be in logical HIGH (idle) state. 6. In case a BGE signal is available, this signal shall be in logical HIGH state in all nodes. 7. Stimulate bus drivers of all nodes via host command to enter BD_Normal . 8. Wait 64000ms to make sure that the AS enters AS_Sleep .
7.1.13 Services Services correspond to chapter 5.1.17.
7.2 Static test cases The motivation of static test cases is to check the availability and the boundaries in the data sheet of the IUT (topology independent). Every parameter must be part of the data sheet and fulfill the specified boundaries. If at least one parameter does not pass this test, the result of the whole conformance test is failed.
Index Parameter SOVS Brace Description Min Max Unit
1. dRxAsym Communication. Receiver delay 5 ns Delay mismatch
2. dStarRx10 Communication. Receiver delay, 100 ns Delay positive edge
3. dStarRx01 Communication. Receiver delay, 100 ns Delay negative edge
4. dStarRxai Communication. Idle reaction time 50 400 ns Timing
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Index Parameter SOVS Brace Description Min Max Unit
5. dStarRxia Communication. Activity reaction time 100 450 ns Timing
6. dTxAsym Communication. Transmitter delay 4 ns Delay mismatch
7. dStarTx10 Communication. Transmitter delay, 100 ns Delay positive edge
8. dStarTx01 Communication. Transmitter delay, 100 ns Delay negative edge
9. dStarTxai 46 Communication. Propagation delay 400 ns Delay active idle
10. dStarTxia 46 Communication. Propagation delay 450 ns Delay idle active
11. dBusTxai 46 Communication. Transition time 30 ns Signal Shape active idle
12. dBusTxia 46 Communication. Transition time 30 ns Signal Shape idle active
48 48 13. uV DIG-OUT-HIGH Communication. Output voltage on a 0.8xuV DIG 1.0xuV DIG - Threshold digital output, when in logical high state 47
48 14. uV DIG-OUT-LOW Communication. Output voltage on a 0.2xuV DIG - Threshold digital output, when in logical high state 47
48 15. uV DIG-IN-HIGH Communication. Threshold for 0.7xuV DIG - Threshold detecting a digital input as on logical high
48 16. uV DIG-IN-LOW Communication. Threshold for 0.3xuV DIG - Threshold detecting a digital input as on logical low
17. VBAT for Power Supply Battery voltage 7 V WU detector required for wake-up detector operation
18. uData0 Communication. Receiver threshold for -300 49 -150 49 mV Threshold detecting Data_0
19. uData1 Communication. Receiver threshold for 150 49 300 49 mV Threshold detecting Data_1
20. ∆uData Communication. Mismatch of receiver 10 49b % Threshold thresholds
21. dRxSlope Communication. Fall and rise time 5 Ns Timing 20%-80%, 15pF load
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Index Parameter SOVS Brace Description Min Max Unit
22. dActivity Communication. Allowed time for 100 300 ns Detection Timing receiver to detect bus activity
23. dIdle Communication. Allowed time for 50 250 ns Detection Timing receiver to detect bus Idle
Table 7-3: Static Test Cases
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7.3 Test cases
7.3.1 Communication.Delay. dStarTx01
7.3.1.1 to 7.3.1.6: Transmitter delay dStarTx01
7.3.1.1.1 Test Purpose This test checks the transmitter delay dStarTx01 from low to high according to figure 8-8 in [01-PL Spec] while no stress condition is present.
7.3.1.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Active Star as transmitter.
7.3.1.1.3 Preamble (setup state) • Standard preamble.
7.3.1.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TPAS1_B2 of the active star according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate IUT (the active star) at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
7.3.1.1.5 Postamble • Standard postamble.
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7.3.1.1.6 Pass- / Fail Criteria Pass criteria: • dStarTx01 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
7.3.1.1.7 Test Instances Instance 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.5 7.3.1.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition AS_VRC
impl.
Configuration Power VBAT =
Supply 5.5V
Ground -5.0V @ -5.0V @
Shift AS N23
Failure FL7 @ N23 FL8 @ N23
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.2 Communication.Delay. dStarTx10
7.3.2.1 to 7.3.2.6: Transmitter delay dStarTx10
7.3.2.1.1 Test Purpose This test checks the transmitter delay dStarTx10 from high to low according to figure 8-8 in [01-PL Spec] while no stress condition is present.
7.3.2.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Active Star as transmitter.
7.3.2.1.3 Preamble (setup state) • Standard preamble.
7.3.2.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star according to the observation window described in chapter 5.1.4.1. • Observe and acquire uBus at TPAS1_B2 of the active star according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate IUT (the active star) at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
7.3.2.1.5 Postamble • Standard postamble.
7.3.2.1.6 Pass- / Fail Criteria Pass criteria:
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• dStarTx10 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
7.3.2.1.7 Test Instances Instance 7.3.2.1 7.3.2.2 7.3.2.3 7.3.2.4 7.3.2.5 7.3.2.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition AS_VRC
impl.
Configuration Power VBAT =
Supply 5.5V
Ground -5.0V @ -5.0V @
Shift AS N23
Failure FL7 @ N23 FL8 @ N23
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.3 Communication.Delay. dTxAsym
7.3.3.1 to 7.3.3.6: Transmitter asymmetry dTxAsym
7.3.3.1.1 Test Purpose This test case calculates the asymmetric transmitter delay that is measured by the parameters dStarTx01 (chapter 7.3.1.1) and dStarTx10 (chapter 7.3.2.1) according to figure 8-8 in [01-PL Spec] while no stress condition is present. All acquired asymmetric transmitter delays for positive and negative edges are used to calculate the resulting asymmetry in pairs according to the applied test condition.
7.3.3.1.2 Configuration • No configuration needed.
7.3.3.1.3 Preamble (setup state) • No preamble necessary.
7.3.3.1.4 Test execution • Calculation of | dStarTx10 -dStarTx01 | as measured in the test cases above.
7.3.3.1.5 Postamble • No postamble necessary.
7.3.3.1.6 Pass- / Fail Criteria Pass criteria: • |dStarTx10 -dStarTx01 | ≤ 4ns.
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7.3.3.1.7 Test Instances Instance 7.3.3.1 7.3.3.2 7.3.3.3 7.3.3.4 7.3.3.5 7.3.3.6
Purpose Stress ground ground min. bus max. bus none shift @ shift @ low battery load load transmitter receiver
Test dStarTx01 dStarTx01 Description dStarTx01 (chapter dStarTx01 dStarTx01 dStarTx01 (chapter (chapter 7.3.1.2) (chapter (chapter (chapter 7.3.1.3) 7.3.1.1) and 7.3.1.4) 7.3.1.5) 7.3.1.6) and and dStarTx10 and and and dStarTx10 dStarTx10 (chapter dStarTx10 dStarTx10 dStarTx10 (chapter (chapter 7.3.2.2) (chapter (chapter (chapter 7.3.2.3) 7.3.2.1) while 7.3.2.4) 7.3.2.5) 7.3.2.6) while while no ground while low while while ground stress shift at the battery minimal maximal shift at a condition transmitter voltage is bus load is bus load is receiver is is present (AS) is present present present present present
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.4 Communication.Delay. dStarRx01
7.3.4.1 to 7.3.4.6: Receiver delay dStarRx01
7.3.4.1.1 Test Purpose This test checks the receiver delay dStarRx01 from low to high according to figure 8- 6 in [01-PL Spec] while no stress condition is present.
7.3.4.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
7.3.4.1.3 Preamble (setup state) • Standard preamble.
7.3.4.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxD of node 23. • Observe and acquire uBus at TPAS4_B2 of the active star according to the observation window described in chapter 5.1.4.1. • Observe and acquire uRxD at TP_AS_RxD of the active star according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver in node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
7.3.4.1.5 Postamble • Standard postamble.
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7.3.4.1.6 Pass- / Fail Criteria Pass criteria: • dStarRx01 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
7.3.4.1.7 Test Instances Instance 7.3.4.1 7.3.4.2 7.3.4.3 7.3.4.4 7.3.4.5 7.3.4.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition AS_VRC
impl.
Configuration Power VBAT =
Supply 5.5V
Ground -5.0V @ -5.0V @
Shift N23 AS
Failure FL7 @ N23 FL8 @ N23
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.5 Communication.Delay. dStarRx10
7.3.5.1 to 7.3.5.6: Receiver delay dStarRx10
7.3.5.1.1 Test Purpose This test checks the receiver delay dStarRx10 from low to high according to figure 8- 6 in [01-PL Spec] while no stress condition is present.
7.3.5.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: node 23 as transmitter.
7.3.5.1.3 Preamble (setup state) • Standard preamble.
7.3.5.1.4 Test execution • Observe and acquire uTxD at TP_N23_TxD of node 23. • Observe and acquire uTxEN at TP_N23_TxD of node 23. • Observe and acquire uBus at TPAS4_B2 of the active star according to the observation window described in chapter 5.1.4.1. • Observe and acquire uRxD at TP_AS_RxD of the active star according to the observation window described in chapter 5.1.4.1. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus driver in node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit High pattern, followed by one 10Bit Low pattern.
7.3.5.1.5 Postamble • Standard postamble.
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7.3.5.1.6 Pass- / Fail Criteria Pass criteria: • dStarRx10 ≤ 100ns. • in case of an available INH1 signal uINH1 shall be in logical HIGH state during test execution.
7.3.5.1.7 Test Instances Instance 7.3.5.1 7.3.5.2 7.3.5.3 7.3.5.4 7.3.5.5 7.3.5.6
Purpose Stress ground ground low min. bus max. bus none shift @ shift @ battery load load transmitter receiver
Precondition AS_VRC
impl.
Configuration Power VBAT =
Supply 5.5V
Ground -5.0V @ -5.0V @
Shift N23 AS
Failure FL7 @ N23 FL8 @ N23
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.6 Communication.Delay. dRxAsym
7.3.6.1 to 7.3.6.6: Receiver asymmetry dRxAsym
7.3.6.1.1 Test Purpose This test case calculates the asymmetric receiver delay that is measured by the parameters dStarRx01 (chapter 7.3.4.1) and dStarRx10 (chapter 7.3.5.1) according to figure 8-6 in [01-PL Spec] while no stress condition is present. All acquired asymmetric receiver delays for positive and negative edges are used to calculate the resulting asymmetry in pairs according to the applied test condition.
7.3.6.1.2 Configuration • No configuration needed.
7.3.6.1.3 Preamble (setup state) • No preamble necessary.
7.3.6.1.4 Test execution • Calculation of | dStarRx10 -dStarRx01 | as measured in the test cases above.
7.3.6.1.5 Postamble • No postamble necessary.
7.3.6.1.6 Pass- / Fail Criteria Pass criteria: • |dStarRx10 -dStarRx01 | ≤ 5ns.
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7.3.6.1.7 Test Instances Instance 7.3.6.1 7.3.6.2 7.3.6.3 7.3.6.4 7.3.6.5 7.3.6.6
Purpose Stress ground ground min. bus max. bus none shift @ shift @ low battery load load transmitter receiver
Test dStarTx01 dStarTx01 Description dStarTx01 (chapter dStarTx01 dStarTx01 dStarTx01 (chapter (chapter 7.3.4.2) (chapter (chapter (chapter 7.3.4.3) 7.3.4.1) and 7.3.4.4) 7.3.4.5) 7.3.4.6) and and dStarTx10 and and and dStarTx10 dStarTx10 (chapter dStarTx10 dStarTx10 dStarTx10 (chapter (chapter 7.3.5.2) (chapter (chapter (chapter 7.3.5.3) 7.3.5.1) while 7.3.5.4) 7.3.5.5) 7.3.5.6) while while no ground while low while while ground stress shift at the battery minimal maximal shift at a condition transmitter voltage is bus load is bus load is receiver is is present (AS) is present present present present present
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.7 Mode.Active Star.Normal
7.3.7.1 to 7.3.7.2: Remain in AS_Normal while undervoltage of VBAT
(V CC available)
7.3.7.1.1 Test Purpose This test checks the ability of the active star to remain in operation mode AS_Normal in case of an undervoltage on V BAT if V CC is still available according to table 9-4, footnote (**) in [01-PL Spec] while no other stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
7.3.7.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VBAT power supply of active star: default.
• External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
7.3.7.1.3 Preamble (setup state) • Standard preamble.
7.3.7.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of nodes 1, 2, 12 and 23. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star.
• Set V BAT power supply of active star to VBATUndervoltage . • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by three 50 10Bit Low patterns, followed by three 51 10Bit High patterns, followed by four 52 10Bit Low patterns. Repeat
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this sequence for at least 1000ms to verify that communication is not disturbed even after the maximal undervoltage detection timeout ( dUV ).
7.3.7.1.5 Postamble • Standard postamble.
7.3.7.1.6 Pass- / Fail Criteria Pass criteria: Hint: This test case requires acquisition of at least 1000ms by the logic state analyzer. A bit level resolution is not required. • uRxD of all observed nodes shall contain all logical LOW sequences transmitted by the active star, i.e. the active star shall not enter AS_Sleep mode and shall transmit all patterns received on the local communication controller interface. • uRxD of the active star shall contain all logical LOW sequences transmitted by node 1, 2, 12 and 23, i.e. the active star shall not enter AS_Sleep mode and shall signal all patterns received on all branches at the local communication controller interface. • in case of an available RxEN signal uRxEN of the active star shall be in logical HIGH state before the first node according to the sequence described on matrix F is stimulated (falling edge of uTxD and uTxEN of node 1) and shall be in logical LOW state while uRxD of the active star signals the received patterns.
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7.3.7.1.7 Test Instances Instance 7.3.7.1 7.3.7.2
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.7.3 to 7.3.7.4: Operation mode change to AS_Normal in case of
power on of V BAT and V CC
7.3.7.3.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V BAT and V CC while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented or a V CC supply input is not implemented.
7.3.7.3.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VBAT power supply of active star: default.
• External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: AS as transmitter.
7.3.7.3.3 Preamble (setup state) • Standard preamble.
7.3.7.3.4 Test execution
• Set V BAT and V CC power supply of active star to 0V. • Observe and acquire uTxD at TP_AS_TxD of the AS. • Observe and acquire uTxEN at TP_AS_TxEN of the AS. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 .
• Set VBAT power supply of active star to default.
• Set V CC power supply of active star to +5.0V. • Wait 100ms. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.7.3.5 Postamble • Standard postamble.
7.3.7.3.6 Pass- / Fail Criteria Pass criteria:
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• uRxD of all observed nodes shall contain the 50/50 pattern transmitted by the AS, i.e. the active star shall enter AS_Normal mode within 100ms after power on and transmit the test patterns of the AS. • uINH1 shall be in logical HIGH state ( Not_Sleep ) 100ms after switching on the power supplies up to the end of the test execution.
7.3.7.3.7 Test Instances Instance 7.3.7.3 7.3.7.4
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.7.5 to 7.3.7.6: Operation mode change to AS_Normal in case of
power on of V CC
7.3.7.5.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V CC while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is implemented.
7.3.7.5.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: AS as transmitter.
7.3.7.5.3 Preamble (setup state) • Standard preamble.
7.3.7.5.4 Test execution
• Set V CC power supply of active star to 0V. • Observe and acquire uTxD at TP_AS_TxD of the AS. • Observe and acquire uTxEN at TP_AS_TxEN of the AS. • Observe and acquire uRxD at TP_Nx_RxD of all nodes.
• Set V CC power supply of active star to +5.0V. • Wait 100ms. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.7.5.5 Postamble • Standard postamble.
7.3.7.5.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by the AS, i.e. the active star shall enter AS_Normal mode within 100ms after power on and transmit the test patterns.
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7.3.7.5.7 Test Instances Instance 7.3.7.5 7.3.7.6
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.7.7 to 7.3.7.8: Operation mode change to AS_Normal in case of
power on of V BAT
7.3.7.7.1 Test Purpose This test checks the ability of the active star to go to AS_Normal in case of power on of V BAT while no stress condition is present. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is not implemented or a V CC supply input is implemented.
7.3.7.7.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: AS as transmitter.
7.3.7.7.3 Preamble (setup state) • Standard preamble.
7.3.7.7.4 Test execution
• Set V BAT power supply of active star to 0V. • Observe and acquire uTxD at TP_AS_TxD of the AS. • Observe and acquire uTxEN at TP_AS_TxEN of the AS. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uINH1 at TP_AS_INH1 .
• Set V BAT power supply of active star to default. • Wait 100ms. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.7.7.5 Postamble • Standard postamble.
7.3.7.7.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain the 50/50 pattern transmitted by the AS, i.e. the active star shall enter AS_Normal mode within 100ms after power on and transmit the test patterns of the AS.
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• uINH1 shall be in logical HIGH state ( Not_Sleep ) 100ms after switching on the power supply up to the end of the test execution.
7.3.7.7.7 Test Instances Instance 7.3.7.7 7.3.7.8
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.8 Mode.Active Star.Normal.GoToSleep
7.3.8.1 to 7.3.8.3: Operation mode change to AS_Sleep after dStarGoToSleep
7.3.8.1.1 Test Purpose This test checks the ability of the active star to go to AS_Sleep mode if all branches are in Branch_Idle for longer than dStarGoToSleep according to figure 9-4, transition number 2 in [01-PL Spec] while no stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified.
7.3.8.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o External VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Active Star as transmitter.
7.3.8.1.3 Preamble (setup state) • Standard preamble.
7.3.8.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 10Bit Low pattern. • Trigger the logic state analyzer to start observation synchronously with the stimuli at TP_AS_TxEN of the active star.
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7.3.8.1.5 Postamble • Standard postamble.
7.3.8.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The Go-To-Sleep timeout dStarGoToSleep shall be measured with an error of less than 1%. • uRxD of the active star shall be in logical HIGH state after the stimuli at uTxD and uTxEN and during the rest of the test execution. • in case of an available INH1 signal uINH1 shall initially be in logical HIGH state for at least 640ms. Between 640ms and 64000ms after the start of the observation, uINH1 shall change to logical LOW state. • in case of an available RxEN signal uRxEN of the active star shall be in logical HIGH state after the stimuli at uTxD and uTxEN and during the rest of the test execution.
7.3.8.1.7 Test Instances Instance 7.3.8.1 7.3.8.3 7.3.8.4
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.9 Mode.Active Star.Normal.GoToSleep_Fail
7.3.9.1 to 7.3.9.3: Operation mode change to AS_Sleep after dStarGoToSleep (FailSilent)
7.3.9.1.1 Test Purpose This test checks the ability of the active star to go to AS_Sleep mode if one branch is in Branch_FailSilent and all other branches are in Branch_Idle for longer than dStarGoToSleep according to figure 9-4, transition number 2 in [01-PL Spec] while no stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified.
7.3.9.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o External VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: babbling idiot. • Communication: none.
7.3.9.1.3 Preamble (setup state) • Standard preamble.
7.3.9.1.4 Test execution • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxD and TP_Nx_TxEN by one babbling idiot pattern as defined in chapter 6.1.3.1. Repeat this pattern for at least 64000ms + 15000µs. • Trigger the logic state analyzer to start observation synchronously with the begin of the babbling idiot stimuli.
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7.3.9.1.5 Postamble • Standard postamble.
7.3.9.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The Go-To-Sleep timeout dStarGoToSleep shall be measured with an error of less than 1%. • uRxD of the active star shall be in logical LOW state for at least 1500µs initially, i.e. the active star signals the babbling idiot pattern received at branch 4 on the local communication controller interface. • uRxD of the active star shall change to logical HIGH state between 1500µs and 15000µs after the start of the babbling idiot sequence. Then, uRxD of the active star shall remain in logical HIGH state during test execution, i.e. branch 4 is excluded from communication by the active star after the noise detection timeout dBranchActive . • in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state for at least 1500µs initially, i.e. the active star signals the babbling idiot pattern received at branch 4 on the local communication controller interface. • in case of an available RxEN signal uRxEN of the active star shall change to logical HIGH state between 1500µs and 15000µs after the start of the babbling idiot sequence. Then, uRxD of the active star shall remain in logical HIGH state during test execution, i.e. branch 4 is excluded from communication by the active star after the noise detection timeout dBranchActive . • in case of an available INH1 signal uINH1 shall be in logical HIGH state for at least 640ms after the first rising edge in uRxD of the AS, i.e. after branch 4 is excluded from communication. Between 640ms and 64000ms after this edge, uINH1 shall change to logical LOW state, i.e. the active star shall enter AS_Sleep mode if all branches are in Branch_Idle or Branch_FailSilent for dStarGoToSleep .
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7.3.9.1.7 Test Instances Instance 7.3.9.1 7.3.9.2 7.3.9.3
Purpose Stress none ground shift low battery
Precondition AS_VRC impl.
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.10 Mode.Active Star.Low Power.Sleep
7.3.10.1 to 7.3.10.3: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V CC
7.3.10.1.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V CC according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified. This test case is skipped if the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
7.3.10.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o External VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
7.3.10.1.3 Preamble (setup state) • Standard preamble.
7.3.10.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of nodes 1, 2, 12 and 23. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star.
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• Set external VCC power supply of active star to VCCUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.10.1.5 Postamble • Standard postamble.
7.3.10.1.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC voltage at the IUTs (ASs) supply input has dropped to VCCUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of nodes 1, 2, 12, 23 shall not contain the 50/50 patterns transmitted by the active star, i.e. the active star shall not retransmit patterns received on the local communication controller interface. • uRxD of of the active star shall not contain the 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall not signal patterns received on any branch to the local communication controller interface. • in case of an available INH1 signal uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep . • in case of an available RxEN signal uRxEN of the active star shall be in logical HIGH state while the nodes 1,2,12 and 23 are stimulated to transmit, i.e. the AS shall not detect the transmitted pattern as valid wake- up patterns.
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7.3.10.1.7 Test Instances Instance 7.3.10.1 7.3.10.2 7.3.10.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.10.4 to 7.3.10.5: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V BAT (VCC not implemented)
7.3.10.4.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V BAT in case of V CC is not implemented according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” or the Functional class “Active Star - Internal Voltage Regulator” is not implemented and a V CC supply input is available.
7.3.10.4.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
7.3.10.4.3 Preamble (setup state) • Standard preamble.
7.3.10.4.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of nodes 1, 2, 12 and 23. • Observe and acquire uRxD at TP_AS_RxD of the active star. • Observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star.
• Set V BAT power supply of active star to VBATUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
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7.3.10.4.5 Postamble • Standard postamble.
7.3.10.4.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VBAT voltage at the IUTs (ASs) supply input has dropped to VBATUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of nodes 1, 2, 12, 23 shall not contain the 50/50 patterns transmitted by the active star, i.e. the active star shall not retransmit patterns received on the local communication controller interface. • uRxD of of the active star shall not contain the 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall not signal patterns received on any branch to the local communication controller interface. • uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep . • in case of an available RxEN signal uRxEN of the active star shall be in logical HIGH state while the nodes 1,2,12 and 23 are stimulated to transmit, i.e. the AS shall not detect the transmitted pattern as valid wake- up patterns.
7.3.10.4.7 Test Instances Instance 7.3.10.4 7.3.10.5
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.10.6 to 7.3.10.7: Operation mode change from AS_Normal to
AS_Sleep due to undervoltage V BAT and V CC
7.3.10.6.1 Test Purpose This test checks the ability of the active star to change its operation mode from
AS_Normal to AS_Sleep in case of an undervoltage on V CC and V BAT at the same time according to figure 9-4, transition number 3 in [01-PL Spec] while no other stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified. This test case is skipped if the Functional class “Active Star - Voltage Regulator Control” is not implemented or the Functional class “Active Star - Internal Voltage
Regulator” is implemented and a V CC supply input is not available.
7.3.10.6.2 Configuration • Topology: as specified in previous configuration section 7.1.
• External VBAT power supply of active star: default.
• External VCC power supply of active star: +5.0V. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
7.3.10.6.3 Preamble (setup state) • Standard preamble.
7.3.10.6.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of nodes 1, 2, 12 and 23. • Observe and acquire uRxD at TP_AS_RxD of the active star. • Observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star.
• Set external V CC power supply of active star to VCCUndervoltage and set V BAT power supply of active star to VBATUndervoltage . • Wait 1000ms ( dUV ) to let the active star detect the undervoltage condition. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
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7.3.10.6.5 Postamble • Standard postamble.
7.3.10.6.6 Pass- / Fail Criteria Pass criteria: Hint: Undervoltage detection timeout measurement requires a trigger event when
VCC /V BAT voltages at the IUTs (ASs) supply inputs have dropped to
VCCUndervoltage /VBATUndervoltage . Adaptation of thresholds for digital signals may be required. • uRxD of nodes 1, 2, 12, 23 shall not contain the 50/50 patterns transmitted by the active star, i.e. the active star shall not retransmit patterns received on the local communication controller interface. • uRxD of of the active star shall not contain the 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall not signal patterns received on any branch to the local communication controller interface. • uINH1 shall change to logical LOW state not later than 1000ms ( dUV ) after the undervoltage is applied, i.e. the active star shall enter AS_Sleep . • in case of an available RxEN signal uRxEN of the active star shall be in logical HIGH state while the nodes 1,2,12 and 23 are stimulated to transmit, i.e. the AS shall not detect the transmitted pattern as valid wake- up patterns.
7.3.10.6.7 Test Instances Instance 7.3.10.6 7.3.10.7
Purpose Stress none ground shift
Precondition
Configuration Power Supply
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.11 Mode.Active Star.Low Power.Sleep.Wake-up
7.3.11.1 to 7.3.11.3: Operation mode change from AS_Sleep to AS_Normal (after dStarWakeUpReaction )
7.3.11.1.1 Test Purpose This test checks the ability of the active star to wake-up after a wake-up reaction time of dStarWakeUpReaction and to change the operation mode from AS_Sleep to AS_Normal according to figure 9-4, transition number 1 in [01-PL Spec] while no stress condition is present. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified.
7.3.11.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o External VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o External VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
7.3.11.1.3 Preamble (setup state) • Sleep preamble.
7.3.11.1.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2. • Observe and acquire uTxEN at TP_N2_TxEN of node 2. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the bus driver of node 2 at TP_N2_TxD and TP_N2_TxEN by one wake-up pattern.
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7.3.11.1.5 Postamble • Standard postamble.
7.3.11.1.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The wake-up reaction time dStarWakeUpReaction shall be measured with an error of less than 1%. • uRxD of the AS shall be in logical HIGH state before the wake-up pattern is transmitted by node 2. Then, uRxD of the AS shall change to logical LOW state not earlier than 31µs (6µs + 18µs + 6µs + 1µs) after the begin of the wake-up pattern and not later than 100034µs (100ms + 6µs + 18µs + 6µs + 4µs). • in case of an available RxEN signal uRxEN of the AS shall be in logical HIGH state before the wake-up pattern is transmitted by node 2. Then, uRxEN of the AS shall change to logical LOW state not earlier than 31µs (6µs + 18µs + 6µs + 1µs) after the begin of the wake-up pattern and not later than 100034µs (100ms + 6µs + 18µs + 6µs + 4µs). • in case of an available INH1 signal uINH1 of the AS shall be in logical LOW state before the wake-up pattern is transmitted by node 2. Then, uINH1 of the AS shall change to logical HIGH state not earlier than 31µs (6µs + 18µs + 6µs + 1µs) after the beginning of the wake-up pattern and not later than 100034µs (100ms + 6µs + 18µs + 6µs + 4µs), i.e. the AS enters AS_Normal after the detection of the remote wake-up event.
7.3.11.1.7 Test Instances Instance 7.3.11.1 7.3.11.2 7.3.11.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 7.0V (if VCC impl.)
VBAT = 5.5V (if VCC not impl.)
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.11.4 to 7.3.11.6: Operation mode change from AS_Sleep to AS_Normal (re-transmission of wake-up symbols)
7.3.11.4.1 Test Purpose
This test checks the ability of the IUT to detect a remote wake-up when V CC in undervoltage condition according to section 8.11 on page 60 in [01-PL Spec] and figure 9-4, transition 1 in [01-PL Spec] on page 73. This test case is skipped if the Functional class “Active Star - Voltage Regulator
Control” is not implemented or the V CC supply input is not available.
7.3.11.4.2 Configuration • Topology: as specified in previous configuration section 6.1.
• VBAT power supply of all nodes: default.
• VCC power supply of all nodes: +5.0V.
• External V CC power supply of IUT in node 24: +5.0V. • Ground shift: 0V.
• Failure: V CC in undervoltage condition. • Communication: Single transmitter.
7.3.11.4.3 Preamble (setup state) • Sleep preamble.
• Switch V CC of the AS to external power supplies and set uV CC =VCCUndervoltage .
7.3.11.4.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uRxD at TP_AS_RxD of the AS. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the AS. • Observe and acquire uINH1 at TP_AS_INH1 of the AS. • Stimulate IUT in node 1 at TP_N1_TxD and TP_N1_TxEN by one wake-up pattern. • Trigger the scope to start observation synchronously with the stimuli at TP_N1_TxEN of node 1.
7.3.11.4.5 Postamble • Standard postamble.
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7.3.11.4.6 Pass- / Fail Criteria Pass criteria: Hint: The period to observe is very long in this test case. But a bit level resolution is not required. The wake-up reaction time dStarWakeUpReaction shall be measured with an error of less than 1%. • uRxD of all observed nodes shall be in logical LOW state between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • In case of an available RxEN signal uRxEN all observed nodes shall be in logical LOW state between 31µs after the beginning of the wake-up pattern and 100.034ms after the beginning of the wake-up pattern. • uINH1 shall be in logical LOW state initially. Then, uINH1 shall change to logical HIGH state within 100ms, i.e. after the detection of the remote wake-up event.
7.3.11.4.7 Test Instances Instance 7.3.11.4 7.3.11.5 7.3.11.6
Purpose Stress none ground shift low battery
Precondition
Configuration Power Supply VBAT = 7.0V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.12 Mode.Active Star.Branch.Idle
7.3.12.1 to 7.3.12.3: Check AS transmitter activation via TxEN (Branch_Idle )
7.3.12.1.1 Test Purpose This test checks the activation of the transmitter of the active star via the TxEN signal of the local communication controller interface according to section 9.2.1 in [01-PL Spec] while no stress condition is present and the branches of the active star are in Branch_Idle state and signal idle to the central logic of the active star respectively.
7.3.12.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Active Star as transmitter.
7.3.12.1.3 Preamble (setup state) • Standard preamble.
7.3.12.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.12.1.5 Postamble • Standard postamble.
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7.3.12.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all nodes shall be in logical HIGH state before the IUT is stimulated to transmit. • uRxD of all nodes shall contain the 50/50 pattern transmitted by the IUT. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution.
7.3.12.1.7 Test Instances Instance 7.3.12.1 7.3.12.2 7.3.12.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.12.4 to 7.3.12.6: Check dStarSetUpDelay
7.3.12.4.1 Test Purpose This test checks the FlexRay parameter dStarSetUpDelay while no stress condition is present. This test case verifies that a second incoming data stream reaching the active star (to a branch of the AS) slightly after dStarSetUpDelay is ignored by the active star while the CC interface receives already a data stream.
7.3.12.4.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Node 1 and AS as transmitter.
7.3.12.4.3 Preamble (setup state) • Standard preamble.
7.3.12.4.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 1 (branch 1). • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN with the pattern A as defined in chapter 6.1.4.3. • Stimulate node 1 at TP_N1_TxD and TP_N1_TxEN with the pattern B as defined in chapter 6.1.4.3. Start stimulation of node 1 500ns after the start of the transmission at the CC interface of the AS.
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7.3.12.4.5 Postamble • Standard postamble.
7.3.12.4.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain pattern A applied to the communication controller interface of the Active Star, only. • the pattern that was stimulated at node 1 shall not be retransmitted by the active star because the incoming data stream at branch 1 shall be ignored after dStarSetUpDelay . • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution.
7.3.12.4.7 Test Instances Instance 7.3.12.4 7.3.12.5 7.3.12.6
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.13 Mode.Active Star.Branch.Active
7.3.13.1 to 7.3.13.3: Check AS transmitter activation via TxEN (Branch_Active )
7.3.13.1.1 Test Purpose This test checks the activation of the transmitter of the active star via the TxEN signal of the local communication controller interface according to section 9.2.1 in [01-PL Spec] while no stress condition is present. Activation shall not be possible when the branches of the active star are in Branch_Active already, i.e. it shall not be possible to disturb ongoing communication via the local communication controller interface.
7.3.13.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: Node 1 and Active Star as transmitter.
7.3.13.1.3 Preamble (setup state) • Standard preamble.
7.3.13.1.4 Test execution • Observe and acquire uTxD at TP_N1_TxD of node 1. • Observe and acquire uTxEN at TP_N1_TxEN of node 1. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_AS_RxD of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except node 1. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star.
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• Stimulate the bus driver in node 1 at TP_N1_TxD and TP_N1_TxEN by one TSS pattern, followed by five 50/50 patterns. • Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 10Bit HIGH pattern. Start stimulation delayed by 1µs to node 1, i.e. the stimulus at the local communication controller interface of the active star occurs while the branches are in Branch_Active already.
7.3.13.1.5 Postamble • Standard postamble.
7.3.13.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes shall contain all 50/50 patterns transmitted by node 1, i.e. the stimulus at the local communication controller interface of the active star does not disturb ongoing communication. • uRxD of the active star shall contain all 50/50 patterns transmitted by node 1, i.e. the stimulus at the local communication controller interface of the active star does not disturb ongoing communication. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the patterns received from node 1 and in logical HIGH state otherwise.
7.3.13.1.7 Test Instances Instance 7.3.13.1 7.3.13.2 7.3.13.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.14 Mode.Active Star.Branch.FailSilent
7.3.14.1 to 7.3.14.3: Check AS transmitter activation via TxEN (Branch_Idle or Branch_FailSilent )
7.3.14.1.1 Test Purpose This test checks the activation of the transmitter of the active star via the TxEN signal of the local communication controller interface according to section 9.2.1 in [01-PL Spec] while no stress condition is present. Activation shall solely be possible when the branches of the active star are in Branch_Idle state or Branch_FailSilent state and signal idle to the central logic of the active star respectively.
7.3.14.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: babbling idiot. • Communication: Active Star as transmitter.
7.3.14.1.3 Preamble (setup state) • Standard preamble.
7.3.14.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes except nodes 11, 12, 13 and 14 (branch 4). • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Stimulate the bus drivers of nodes 12, 13 and 14 at TP_Nx_TxEN by one babbling idiot pattern as defined in chapter 6.1.3.1. • Stimulate the IUT (AS) at TP_AS_TxD and TP_AS_TxEN by one TSS pattern, followed by one 50/50 pattern. Start stimulation 15000µs after the
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start of the babbling idiot sequence, i.e. after branch 4 shall have been excluded from communication and shall have entered Branch_FailSilent .
7.3.14.1.5 Postamble • Standard postamble.
7.3.14.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of all observed nodes in branches 1 to 3 shall contain the 50/50 pattern transmitted by the IUT (AS), i.e. activation of the transmitter of the active star via the TxEN signal of the local communication controller interface shall be possible while branch 4 is in Branch_FailSilent mode. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution.
7.3.14.1.7 Test Instances Instance 7.3.14.1 7.3.14.2 7.3.14.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.15 Failure.Loss
7.3.15.1 TxEN unconnected
7.3.15.1.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected TxEN signal according to table 8-28 in [01-PL Spec]. This test case considers only the AS_Normal mode.
7.3.15.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: TxEN unconnected. • Communication: matrix F (round robin including AS).
7.3.15.1.3 Preamble (setup state) • Standard preamble. • Switch TxEN signal of the active star to unconnected according to chapter 3.5, failure FL5.
7.3.15.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star.
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• Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.15.1.5 Postamble • Standard postamble.
7.3.15.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of the active star shall contain all 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall signal all patterns received on all branches at the local communication controller interface. • uRxD of all nodes (except the active star) shall not contain the 50/50 pattern applied to the communication controller interface of the active star, i.e. the active star shall read the unconnected TxEN input as logical HIGH and shall not be able to transmit anything. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the received patterns and shall be logical HIGH state otherwise.
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7.3.15.2 TxD unconnected
7.3.15.2.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected TxD signal according to table 8-28 in [01-PL Spec]. This test case considers only the AS_Normal mode.
7.3.15.2.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: TxD unconnected. • Communication: matrix F (round robin including AS).
7.3.15.2.3 Preamble (setup state) • Standard preamble. • Switch TxD signal of the active star to unconnected according to chapter 3.5, failure FL6.
7.3.15.2.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
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7.3.15.2.5 Postamble • Standard postamble.
7.3.15.2.6 Pass- / Fail Criteria Pass criteria: • uRxD of the active star shall contain all 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall signal all patterns received on all branches at the local communication controller interface. • uRxD of all nodes (except the active star) shall contain a logical LOW sequence with the length of the 50/50 pattern instead of the 50/50 pattern applied to the communication controller interface of the active star, i.e. the active star shall read the unconnected TxD input as logical LOW and shall transmit sequences of logical LOW if enabled to transmit. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the received patterns and shall be logical HIGH state otherwise.
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7.3.15.3 BGE unconnected
7.3.15.3.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected BGE signal according to table 8-28 in [01-PL Spec]. This test is skipped if the Functional class “Active Star - Bus Guardian Interface” is not implemented. This test case considers only the AS_Normal mode.
7.3.15.3.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: BGE unconnected. • Communication: matrix F (round robin including AS).
7.3.15.3.3 Preamble (setup state) • Standard preamble. • Switch BGE signal of the active star to unconnected according to chapter 3.5, failure FL10.
7.3.15.3.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxD at TP_AS_RxD of the active star. • Observe and acquire uRxEN at TP_AS_RxEN of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star.
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• Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern.
7.3.15.3.5 Postamble • Standard postamble.
7.3.15.3.6 Pass- / Fail Criteria Pass criteria: • uRxD of the active star shall contain all 50/50 patterns transmitted by nodes 1, 2, 12 and 23, i.e. the active star shall signal all patterns received on all branches at the local communication controller interface. • uRxD of all nodes (except the active star) shall not contain the 50/50 pattern applied to the communication controller interface of the active star, i.e. the active star shall read the unconnected BGE input as logical LOW and shall not be able to transmit anything. • uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the received patterns and shall be logical HIGH state otherwise. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution.
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7.3.15.4 GND unconnected
7.3.15.4.1 Test Purpose This test checks the behaviour of the IUT in case of an unconnected GND connection of the IUT according to table 8-27 in [01-PL Spec].
7.3.15.4.2 Configuration • Topology: as specified in previous configuration section 5.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: GND of IUT unconnected. • Communication: AS as transmitter.
7.3.15.4.3 Preamble (setup state) • Switch GND connection of all IUTs in the AS to unconnected according to Figure 3-9 and Table 3-4, failure FL15. • Standard preamble.
7.3.15.4.4 Test execution • Observe and acquire uBus at TPAS1_B1 of the AS according to the observation window described in chapter 6.1.4.7, but the observation window shall be 52µs. • Observe and acquire uTxD at TP_AS_TxD of the AS according to the observation window described in chapter 6.1.4.7, but the observation window shall be 52µs. • Observe and acquire uTxEN at TP_AS_TxEN of the AS according to the observation window described in chapter 6.1.4.7, but the observation window shall be 52µs. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern, followed by one TSS pattern, followed by one 50/50 pattern.
7.3.15.4.5 Postamble • Standard postamble.
7.3.15.4.6 Pass- / Fail Criteria
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Pass criteria: • uBus of branch 1 of the AS shall be in idle range | uBus |<30mV.
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7.3.16 Failure.Short Circuits
7.3.16.1 Short circuit betweenTxEN to GND
7.3.16.1.1 Test Purpose This test checks the behaviour of the IUT in case of TxEN is shortenend to GND according to table 8-27 in [01-PL Spec].
7.3.16.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: short-circuit TxEN to GND. • Communication: Active Star as transmitter.
7.3.16.1.3 Preamble (setup state) • Standard preamble.
7.3.16.1.4 Test execution • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • Short-circuit TxEN and GND of the IUT (AS) according to chapter 3.5, failure FL4. • Beginning with the falling edge of uTxEN of the active star, stimulate IUT (AS) at TP_AS_TxD by a logical LOW state sequence of at least 15000µs.
7.3.16.1.5 Postamble • Standard postamble.
7.3.16.1.6 Pass- / Fail Criteria Pass criteria:
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Hint: For BranchActive timeout measurement, a trigger event on the falling edge of uTxEN is required. • uRxD of all nodes shall be in logical HIGH state before the falling edge of uTxEN of the active star. After the falling edge of uTxEN of the active star, uRxD of all nodes shall change to logical LOW state and shall remain in logical LOW state for at least 1500µs and not more than 15000µs. After this logical LOW state phase, uRxD of all nodes shall return to and remain in logical HIGH state. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution.
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7.3.17 Dynamic Low Battery Voltage
7.3.17.1 to 7.3.17.2: Dynamic low battery voltage
7.3.17.1.1 Test Purpose This test checks the behaviour of the IUT after a dynamic low battery voltage pulse according to chapter 3.4 in AS_Normal mode. Additionally, the behaviour at the local communication controller interface and, if available, the local bus guardian interface is verified. Hint: This test case intends to test the capability of the active star to return to the operating state that was active before the dynamic low battery pulse. This test case is applicable to all IUTs, even if no V BAT supply input is implemented. In this case, the input voltage of the VCC voltage regulator (the battery voltage) is stressed by the dynamic low battery voltage pulse.
7.3.17.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: 11.6V.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: 11.6V. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
• Test signal: U S/t f1 as specified in chapter 3.4.
7.3.17.1.3 Preamble (setup state) • Standard preamble.
7.3.17.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxD at TP_AS_RxD of the active star.
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• In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 50/50 pattern. Repeat this sequence. At least one more sequence shall be transmitted after the end of the dynamic low battery voltage pulse. Hint: the bit duration in this test case shall be gdBit =50µs, because the memory depth of the logic analyzer is much too small to acquire 10 seconds with a 100ns bit time. The gap between the messages in matrix A shall be 8.95ms. • After the first communication round trigger the dynamic low battery pulse.
7.3.17.1.5 Postamble • Standard postamble.
7.3.17.1.6 Pass- / Fail Criteria Pass criteria:
• while V BAT ≥ +5.5V, i.e. sufficient supply voltage at V BAT and for the V CC voltage regulator is present: o uRxD of all observed nodes shall contain all 50/50 patterns applied to the local communication controller interface of the active star (according to uTxD and uTxEN of the active star), i.e. all data shall be transmitted by the active star. o uRxD of the active star shall contain all 50/50 patterns transmitted by nodes 1, 2, 12 and 23 (according to uTxD and uTxEN of the corresponding node), i.e. the active star shall signal all patterns received on all branches to the local communication controller interface. o in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state. o in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the received patterns and shall be logical HIGH state otherwise.
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7.3.17.1.7 Test Instances Instance 5.3.17.1 5.3.17.2
Purpose Stress tf1 ramp tf6 ramp
Precondition
Configuration Power Supply
Ground Shift
Failure
Test Signal US/t f1 as specified in chapter 3.4 US/t f6 as specified in chapter 3.4
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.18 Communication.Truncation
7.3.18.1 to 7.3.18.3: Path truncation
7.3.18.1.1 Test Purpose This test checks the overall channel truncation if no stress condition is present according to the sum of all allowed truncation effects specified in [01-PL Spec]. This test shall verify, that only the transmission start sequence is affected by truncation effects and that a protocol controller would decode the following data properly.
7.3.18.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: matrix F (round robin including AS).
7.3.18.1.3 Preamble (setup state) • Standard preamble.
7.3.18.1.4 Test execution • Observe and acquire uTxD at TP_Nx_TxD of nodes 1, 2, 12 and 23. • Observe and acquire uTxD at TP_AS_TxD of the active star. • Observe and acquire uTxEN at TP_Nx_TxEN of nodes 1, 2, 12 and 23. • Observe and acquire uTxEN at TP_AS_TxEN of the active star. • Observe and acquire uRxD at TP_Nx_RxD of all nodes. • Observe and acquire uRxD at TP_AS_RxD of the active star. • In case of an available INH1 signal observe and acquire uINH1 at TP_AS_INH1 of the active star. • In case of an available RxEN signal observe and acquire uRxEN at TP_AS_RxEN of the active star. • Stimulate the bus drivers and the IUT (active star) according to the sequence described on matrix F at TP_Nx/AS_TxD and TP_Nx/AS_TxEN by one TSS pattern, followed by one 10/90 pattern.
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7.3.18.1.5 Postamble • Standard postamble.
7.3.18.1.6 Pass- / Fail Criteria Pass criteria: • the width of the received TSS pattern transmitted by the active star (logical LOW phase from the falling edge of the received TSS pattern to the rising edge of the first bit of the following 10/90 pattern) in uRxD of all nodes shall be at least 100ns, i.e. the channel truncation shall be within the allowed range. • the width of all received TSS patterns transmitted by nodes 1, 2, 12 and 23 (logical LOW phase from the falling edge of the received TSS pattern to the rising edge of the first bit of the following 10/90 pattern) in uRxD of the active star shall be at least 100ns, i.e. the channel truncation shall be within the allowed range. • in case of an available INH1 signal uINH1 of the active star shall be in logical HIGH state during test execution. • in case of an available RxEN signal uRxEN of the active star shall be in logical LOW state while uRxD of the active star signals the received patterns and shall be logical HIGH state otherwise.
7.3.18.1.7 Test Instances Instance 7.3.18.1 7.3.18.2 7.3.18.3
Purpose Stress none ground shift low battery
Precondition AS_VRC implemented
Configuration Power Supply VBAT = 5.5V
Ground Shift -5.0V @ AS
Failure
Preamble
Test Execution
Pass/Fail Criteria
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.3.19 Dynamic Ground Shift
7.3.19.1 Active star receives pattern during ground shift at transmitter
7.3.19.1.1 Test Purpose This test checks the ability of the IUT to receive a test pattern while dynamic ground shift is present at the transmitting node.
7.3.19.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: Node 23 as transmitter.
7.3.19.1.3 Preamble (setup state) • Standard preamble.
7.3.19.1.4 Test execution • Observe and acquire uGS_dyn at TP_N23_GND of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N23_TxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_AS_RxD of the AS according to the observation window described in chapter 5.1.4.5. • Stimulate node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
7.3.19.1.5 Postamble • Standard postamble.
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7.3.19.1.6 Pass- / Fail Criteria Pass criteria: • uRxD of the AS shall contain all patterns transmitted by node 23, i.e. the dynamic ground shift at node 23 shall not disturb the communication.
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7.3.19.2 Active star transmits pattern during ground shift at AS
7.3.19.2.1 Test Purpose This test checks the ability of the IUT to transmit a test pattern while dynamic ground shift is present at the AS.
7.3.19.2.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at the AS. • Failure: None. • Communication: AS as transmitter.
7.3.19.2.3 Preamble (setup state) • Standard preamble.
7.3.19.2.4 Test execution • Observe and acquire uGS_dyn at TP_AS_UGS of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_AS_TxD of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_AS_TxEN of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
7.3.19.2.5 Postamble • Standard postamble.
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7.3.19.2.6 Pass- / Fail Criteria Pass criteria: • uRxD of node 23 shall contain all patterns transmitted by the AS, i.e. the dynamic ground shift at the AS shall not disturb the communication.
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7.3.19.3 Active star receives pattern during ground shift at AS
7.3.19.3.1 Test Purpose This test checks the ability of the IUT to receive a test pattern while dynamic ground shift is present at the AS.
7.3.19.3.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at the AS. • Failure: None. • Communication: Node 23 as transmitter.
7.3.19.3.3 Preamble (setup state) • Standard preamble.
7.3.19.3.4 Test execution • Observe and acquire uGS_dyn at TP_AS_UGS of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_N23_TxD of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_N23_TxEN of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_AS_RxD of the AS according to the observation window described in chapter 5.1.4.5. • Stimulate node 23 at TP_N23_TxD and TP_N23_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by nine 50/50 patterns, followed by one 10Bit High pattern. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
7.3.19.3.5 Postamble • Standard postamble.
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7.3.19.3.6 Pass- / Fail Criteria Pass criteria: • uRxD of the AS shall contain all patterns transmitted by node 23, i.e. the dynamic ground shift at the AS shall not disturb the communication.
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7.3.19.4 Active star transmits pattern to shifted receiver
7.3.19.4.1 Test Purpose This test checks the ability of the IUT to transmit a test pattern while dynamic ground shift is present at the receiving node.
7.3.19.4.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: Dynamic at node 23. • Failure: None. • Communication: AS as transmitter.
7.3.19.4.3 Preamble (setup state) • Standard preamble.
7.3.19.4.4 Test execution • Observe and acquire uGS_dyn at TP_N23_GND of node 23 according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxD at TP_AS_TxD of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uTxEN at TP_AS_TxEN of the AS according to the observation window described in chapter 5.1.4.5. • Observe and acquire uRxD at TP_N23_RxD of node 23 according to the observation window described in chapter 5.1.4.5. • Stimulate the AS at TP_AS_TxD and TP_AS_TxEN by one wake-up pattern as described in chapter 5.1.3.1, followed by one TSS pattern, followed by ten 50/50 patterns. Trigger the dynamic ground shift curve synchronously with the first rising edge after the TSS pattern.
7.3.19.4.5 Postamble • Standard postamble.
7.3.19.4.6 Pass- / Fail Criteria Pass criteria:
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• uRxD of node 23 shall contain all 50/50 patterns transmitted by the AS, i.e. the dynamic ground shift at node 23 shall not disturb the communication.
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7.3.20 Communication.Shortened Bit Times Hint: value of about 80ns is a snapshot of the current status. This value may change in the future if new results are available
7.3.20.1 to 7.3.20.2: Shortened high and low pattern
7.3.20.1.1 Test Purpose This test checks the ability of the IUT to receive shortened bits according to the system timing constraints chapter 12 in [01-PL Spec]. This test shall verify, that the IUT itself does receive the shortened bits correctly and signals them to the CC. The test hardware shall be calibrated for this test case.
7.3.20.1.2 Configuration • Topology: as specified in previous configuration section 7.1.
• In case that only V CC is implemented:
o VCC power supply of active star: +5.0V.
• In case that V BAT and V CC are both implemented:
o VBAT power supply of active star: default.
o VCC power supply of active star: +5.0V.
• In case that only VBAT is implemented:
o VBAT power supply of active star: default. • Ground shift: 0V. • Failure: none. • Communication: single transmitter.
7.3.20.1.3 Preamble (setup state) • Standard preamble.
7.3.20.1.4 Test execution • Observe and acquire uTxD at TP_N2_TxD of node 2 according to the observation window described in chapter 5.1.4.3. • Observe and acquire uTxEN at TP_N2_TxEN of node 2 according to the observation window described in chapter 5.1.4.3. • Observe and acquire uBus at TPAS4_B3 of the AS according to the observation window described in chapter 5.1.4.3. • Observe and acquire uRxD at TP_AS_RxD of the AS according to the observation window described in chapter 5.1.4.3. • Stimulate node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, followed by three 10Bit Low patterns, followed by one 10/90 pattern, followed by two 10Bit Low patterns. The length of each single bit shall be
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80ns measured at TPAS4_B3 of the AS. In case the bit length is too long the stimulated bits at the transmitter shall be shortened, otherwise the bits shall be elongated.
7.3.20.1.5 Postamble • Standard postamble.
7.3.20.1.6 Pass- / Fail Criteria Pass criteria: • The length of the received high bit in the 10/90 pattern as specified in the observation window in uRxD of the AS shall be equal to the length of the high bit in uBus of the corresponding TPAS4_B3 of the AS ±5ns, i.e. the receiver asymmetry shall be within the allowed range, according to chapter 8.9.3 in [01-PL Spec].
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7.3.20.1.7 Test Instances Instance 7.3.20.1 7.3.20.2
Purpose Stress Low Pattern High Pattern
Precondition
Configuration Power
Supply
Ground
Shift
Failure
Preamble
Test Execution … … Stimulate node 2 at TP_N2_TxD and Stimulate node 2 at TP_N2_TxD and TP_N2_TxEN by one TSS pattern, TP_N2_TxEN by one TSS pattern, followed by three 10Bit Low patterns, followed by three 10Bit High patterns, followed by one 10/90 pattern, followed by one 90/10 pattern, followed by two 10Bit Low patterns. followed by two 10Bit High patterns. The length of each single bit shall be The length of each single bit shall be 80ns measured at TPAS4_B3 of the 80ns measured at TPAS4_B3 of the AS. In case the bit length is too long AS. In case the bit length is too long the stimulated bits at the transmitter the stimulated bits at the transmitter shall be shortened, otherwise the bits shall be shortened, otherwise the bits shall be elongated. shall be elongated
Pass/Fail Criteria The length of the received high bit in The length of the received low bit in the 10/90 pattern as specified in the the 90/10 pattern as specified in the observation window in uRxD of the observation window in uRxD of the AS shall be equal to the length of the AS shall be equal to the length of the high bit in uBus of the corresponding low bit in uBus of the corresponding TPAS4_B3 of the AS ±5ns, i.e. the TPAS4_B3 of the AS ±5ns, i.e. the receiver asymmetry shall be within receiver asymmetry shall be within the allowed range, according to the allowed range, according to chapter 8.9.3 in [01-PL Spec]. chapter 8.9.3 in [01-PL Spec]
█ - no changes in comparison to first test case █ - changes in comparison to first test case
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7.4 Test procedures
7.4.1 Signal shape, timing, delay
PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS .IDCPowerSupplyConfig.Output() ** PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) ** NetServices.ISwitch.SetGroundShift() ** PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() Scope.IConfiguration.Acquisition() Scope.IConfiguration.Channel() Scope.IConfiguration.Trigger() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest() NetServices.ISwitch.SetTermination() ***
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * Scope.AcquireBusData.GetWaveform() NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with alternative power supply configuration, only. ** * Test cases with ground shift, only. *** Test cases with termination change during test execution, only.
Figure 7-11: Test Procedure for Signal Shape, Timing and Delay Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true) NetServices.ISwitch.SetInterruptionOnBoard() * NetServices.ISwitch.SetShortCircuitOnBoard() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() Scope.IConfiguration.Acquisition() Scope.IConfiguration.Channel() Scope.IConfiguration.Trigger() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
Scope.AcquireBusData.GetWaveform() NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with on board interruptions or short circuits, only.
Figure 7-12: Test Procedure for Failure Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.DynamicLowBattery() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true) PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() Scope.IConfiguration.Configure() * Scope.IConfiguration.Acquisition() * Scope.IConfiguration.Channel() * Scope.IConfiguration.Trigger() * LogicAnalyzer.ILogicAnalyzer.Configure() ** NetServices.IControl.SetOperatingMode() Scope.IAcquireBusData.Initiate() *
PowerSupply_VBAT .IBatterySupplyConfig.InitiateArbitraryFunction()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest() NetServices.IControl.SetOperatingMode() ***
Scope.AcquireBusData.GetWaveform() * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with oscilloscope acquisition, only. ** * In some test cases required for observation of pattern generator, only. *** Test cases with op-mode change during test execution, only.
Figure 7-13: Test Procedure for Dynamic Low Battery Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(true) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetSupplyConfig() *
PowerSupply_VGS .IDCPowerSupplyConfig.Output() ** PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) ** NetServices.ISwitch.SetGroundShift() ** PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() *** LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.Output() **** PowerSupply_ALT_VCC .IDCPowerSupplyConfig.Output() ****
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) **
PowerSupply_ALT_VBAT .IDCPowerSupplyConfig.EnableOutput(false) * PowerSupply_ALT_VCC .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
**** Test cases with alternative power supply configuration, only. ** ** Test cases with ground shift, only. *** * In some test cases required for setup state, only. **** Test cases with alternative power supply output change during test execution, only.
Figure 7-14: Test Procedure for Mode Test Cases
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PowerSupply_VBAT .IBatterySupplyConfig.Output() PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(true)
PowerSupply_VGS .IDCPowerSupplyConfig.Output() * PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(true) * NetServices.ISwitch.SetGroundShift() * PatternGenerator.IPatternGenerator.Configure() PatternGenerator.IPatternGenerator.CreateComposedPattern() LogicAnalyzer.ILogicAnalyzer.Configure() NetServices.IControl.SetOperatingMode()
LogicAnalysisSystem.ILogicAnalysisSystem.ExecuteLogicTest()
PowerSupply_VGS .IDCPowerSupplyConfig.EnableOutput(false) * NetServices.ISwitch.ResetNet()
PowerSupply_VBAT .IBatterySupplyConfig.EnableOutput(false)
*** Test cases with ground shift, only.
Figure 7-15: Test Procedure for Truncation Test Cases
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8 Appendix
8.1 FlexRay parameters Used version: FlexRay Communications System Electrical Physical Layer Specification V2.1 Rev B.
FlexRay Parameter Description Min Max Unit gdBit Nominal duration of one bit time 100 53 ns
Number of repetitions of Number of repetitions 2 63 - pWakeupPattern gdTSSTransmitter Overall truncation with one AS 200 1100 54 ns See also [09-EPLAN] and [08-Prot Spec]
gdWakeupSymbol Length of the low part of the wake-up 6 µs TxLow symbol gdWakeupSymbol Length of the idle part of the wake-up 18 µs TxIdle symbol dPropagationDelayM,N Propagation delay from node M to N 2500 ns dFrameTSS Truncation on path from node M to N 100 1350 ns Truncation M,N
RDCLoad DC bus load 40 55 Ω iBP Leak , iBM Leak Absolute leakage current, when 25 µA unpowered uBus ActiveHigh Upper receiver threshold for 150 425 mV detecting activity uBus ActiveLow Lower receiver threshold for -425 -150 mV detecting activity uData1 Receiver threshold for detecting 150 300 mV Data_1 uData0 Receiver threshold for detecting -300 -150 mV Data_0
∆uData Mismatch of receiver thresholds 10 % dIdleDetection Idle detection time 50 250 ns dActivityDetection Activity detection time 100 300 ns
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FlexRay Parameter Description Min Max Unit dBDRxai Idle reaction time 50 400 ns dBDRxia Activity reaction time 100 450 ns uRx uBus @ TP4 425 435 mV dRxia Transition time Idle Data_0 18 22 ns dRxai Transition time Data_0 Idle 18 22 ns dActive Minimum time Data_0 590 610 ns dIdle Minimum time Idle 590 610 ns dBDRx10 Receiver delay, negative edge 100 ns dBDRx01 Receiver delay, positive edge 100 ns dRxAsym Receiver delay mismatch 5 ns uRx Data uBus @ TP4 400 410 mV uRx10 Transition time Data_1 Data_0 21.5 22.5 ns uRx01 Transition time Data_0 Data_1 21.5 22.5 ns dRx0 Minimum time Data_0 80 120 ns dRx1 Minimum time Data_1 80 120 ns uBDTx active Absolute differential voltage, while 600 2000 mV sending uBDTx idle Absolute differential voltage, while 0 30 mV idle iBP GNDShortMax Maximum output current when 100 mA shorted to GND iBM GNDShortMax Maximum output current when 100 mA shorted to GND iBP BAT27ShortMax Absolute maximum output current 100 mA when shorted to 27V iBM BAT27ShortMax Absolute maximum output current 100 mA when shorted to 27V iBP BAT48ShortMax Absolute maximum output current 120 mA when shorted to 48V
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FlexRay Parameter Description Min Max Unit iBM BAT48ShortMax Absolute maximum output current 120 mA when shorted to 48V iBP BAT60ShortMax Absolute maximum output current 150 mA when shorted to 60V iBM BAT60ShortMax Absolute maximum output current 150 mA when shorted to 60V iBM BPShortMax Absolute maximum output current 100 mA when BM shorted to BP iBP BMShortMax Absolute maximum output current 100 mA when BP shorted to BM iBM -5VShortMax Absolute maximum output current 100 mA when shorted to -5V iBP -5VShortMax Absolute maximum output current 100 mA when shorted to -5V dBDTx10 Transmitter delay, negative edge 100 ns dBDTx01 Transmitter delay, positive edge 100 ns dTxAsym Transmitter delay mismatch 4 ns dBusTx10 Fall time differential bus voltage 3.75 18.75 ns dBusTx01 Rise time differential bus voltage 3.75 18.75 ns dBDTxia Propagation delay idle to active 100 ns dBDTxai Propagation delay active to idle 100 ns dBusTxia Signal slope idle to active (BD) 30 ns dBusTxai Signal slope active to idle (BD) 30 ns dTxEN0 Time span of bus activity 550 650 ns dWU 01 , dWU 02 Duration of Data_0 phase in WU >4 µs dWU Idle1 , dWU Idle2 Duration of Idle phase in WU >4 µs dWU Duration of valid wake-up pattern >16 <48 µs dWU 0Detect Time for detection of a Data_0 phase 1 4 µs in WU symbol dWU IdleDetect Time for detection of a Idle phase in 1 4 µs
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FlexRay Parameter Description Min Max Unit
WU symbol dWU Timeout Acceptance timeout for WU 48 140 µs recognition dWakePulseFilter Duration of the wake pulse filter time 1 500 µs dUV Undervoltage detection filter time 1000 ms dStarDelay Propagation delay trough an active 0 250 ns star dStarDelay 0 Propagation delay trough an active 0 250 ns star dStarAsym Asymmetric propagation delay for 8 ns monolithic devices dStarAsym Asymmetric propagation delay for 10 ns non-monolithic devices dStarTruncation Truncation 450 ns dStarGoToSleep Go-to-Sleep timeout 640 64000 ms dStarWakeUpReaction Active star wake-up reaction time 100 ms dBranchActive Noise detection time 1500 15000 µs dBranchFailSilentIdle Timeout for recovery after failure 10 µs dStarSetUpDelay Set up delay 500 ns uV DIG-IN-HIGH Threshold for detecting a digital input 0.7xuV DIG - as on logical high
uV DIG-IN-LOW Threshold for detecting a digital input 0.3xuV DIG - as on logical low
uV DIG-OUT-HIGH Threshold for detecting a digital 0.8xuV DIG 1.0xuV DIG - output, when in logical high state
uV DIG-OUT-LOW Threshold for detecting a digital 0.2xuV DIG - output, when in logical low state
RCM1 , RCM2 Common mode input resistance 10 40 kΩ
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FlexRay Parameter Description Min Max Unit uCM Common mode voltage range -10 +15 V
SPI interface speed Characteristics of the optional SPI 0.01 1 MBit/s bus driver to host interface uBias – BD_Normal Voltage @ BP & BM during bus state 1800 3200 Idle uBias – Low Power Voltage @ BP & BM during bus state -200 +200 Idle_LP
VBAT for WU detector Battery voltage required for wake-up 7 V detector operation uUV BAT Transition to low power when voltage 2 5.5 V falls below product specific threshold
uUV CC Transition to low power when voltage 2 Product V falls below product specific threshold specific
uUV IO Transition to low power when voltage 0.75 Product V falls below product specific threshold specific
iBP Leak Leakage current when all supplies 25 µA are switched off iBM Leak Leakage current when all supplies 25 µA are switched off
T Ambient temperature -40 +125 °C dBDTxDM Transmitter on/off delay mismatch 50 ns |dBDTxia -dBDTxai | dSymbolLength Change of length of a symbol on path -1200 900 ns Change M,N from node module M to node module N dStarTxia Propagation delay idle active 450 ns dStarTxai Propagation delay active idle 400 ns dRxSlope Fall and rise time 5 ns 20%-80%, 15pF load uRx Data uBus @ TP4 400 410 mV dRx10 Transition time 21.5 22.5 ns Data_1 → Data_0
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FlexRay Parameter Description Min Max Unit dRx01 Transition time 21.5 22.5 ns Data_0 → Data_1 dRx0 Transition span Data_0 80 120 ns dRx1 Transition span Data_1 80 120 ns dRxia Transition time Idle → Data_0 18 22 ns dRxai Transition time Data_0 → Idle 18 22 ns dActive Minimum time Data_0 590 610 ns dIdle Minimum time Idle 590 610 Ns dErrorIndicationNode Error indication of a node bus driver 1 ms dErrorIndicationAS Error indication of an active star 4 ms
Table 8-1: FlexRay Parameters
8.2 References to the EPL specification Used version: FlexRay Communications System Electrical Physical Layer Specification V2.1 Rev B.
Reference description Table Figure Chapter Page
Cable termination 4-1 4.4 22
DC bus load 4-5 4.7 24
Eye diagram at TP4 7-4 7.4 36
Power on 8.3.1.1 38
Bus Driver - Host interface 8.6 43
Receiver timing characteristics 8-18 8-6 8.9.3 52
Transmitter characteristics 8-22 8-8 8.9.5 56
Operating mode transitions (of BD) 8-1 8-2 8.3 39
Signalling on ERRN (only with STBN) 8-8 8.6.2.2 44
Signalling on ERRN (with STBN and EN) 8-9 8.6.2.2 45
Bus Driver - power supply interface 8-10 8.7 46
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Reference description Table Figure Chapter Page
Time span Data_0 and Data_1 8-19 8-6 8.9.3 53
Remote wake-up event 8.11 60
Local wake-up event 8.10 60
Voltage monitoring 8.7 46
Behaviour of unconnected digital input pins 8-28 8.12.2 62
Bus Driver behaviour under fault conditions 8-27 8.12.1 61
Active Star - CC interface 9.2.1 69
Active Star - power supply interface 9.2.3 69 dStarTruncation 9-2 9-3 9.3 70
Active Star operation mode transitions 9-4 9-4 9.7 73
Operating states of branches 9-7 9-5 9.9 75
Collisions 9-6 9.10 76
Active Star behaviour under fault conditions 9-9 9.11 78
General features for FlexRay parts 11 81
Bahaviour of unconnected digital input pins 11-5 11.7.1 83 (SPI interface)
System timing constraints 12 84
Table 8-2: FlexRay EPL Specification References
8.3 Index battery splice ...... 21 DIN 40839...... 45 Bus Cable...... 33 EMC...... 53 Bus Connector ...... 34 ESD...... 25 cable shield ...... 24 ground shift...... 37 chassis ...... 21 ISO 7637 ...... 45 CMC...... 28 local test method...... 15 Common mode choke ...... 18 lower tester ...... 15
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Passive Bus ...... 32 supervisor ...... 15 Passive Star ...... 30 Temperature Test ...... 53 physical channel...... 18 test coordination procedure ...... 15 Power Supply Cable...... 34 test planes ...... 337 SOVS...... 54 test topology ...... 18 SOVS Communication ...... 55 unterminated node...... 27 SOVS Failure ...... 64 upper tester...... 15
SOVS Ground Shift ...... 64 VBAT splice ...... 21
SOVS Mode ...... 60 VCC splice...... 21
SOVS Power Supply ...... 63 VECU ...... 43 split termination ...... 26 VIO splice...... 21 Static Tests ...... 55
8.4 List of tables Table 2-1: Test Topology Description...... 19 Table 2-2: Cable Overview of Test Topology ...... 24 Table 2-3: Shield Connection Components...... 25 Table 2-4: ESD Load Circuit...... 26 Table 2-5: Split Termination Components...... 27 Table 2-6: Passive Star Implementation...... 31 Table 2-7: Bus Cable Impedance...... 33 Table 2-8: Bus Cable Characteristics...... 33 Table 2-9: Supply Cable Characteristics ...... 34 Table 2-10: Connectors Characteristics ...... 34
Table 2-11: V BAT Power Supply Characteristics ...... 35
Table 2-12: V CC Power Supply Characteristics...... 36
Table 2-13: V IO Power Supply Characteristics ...... 37 Table 2-14: Ground Shift Generator Characteristics ...... 37 Table 2-15: Low Battery Generator Characteristics ...... 38 Table 2-16: Signal Generator Characteristics ...... 39 Table 2-17: Analog Measurement Device Characteristics...... 39
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Table 2-18: Digital Measurement Device Characteristics...... 40 Table 2-19: Data Acquisition Unit...... 40 Table 2-20: Broadband Amplifier...... 41 Table 2-21: Arbitrary Function Generator...... 41 Table 3-1: Ground Shift...... 42 Table 3-2: Stress Condition Static Low Battery Voltage inside operational Range .. 44 Table 3-3: Stress signal 4’...... 45 Table 3-4: Faulty Lines Test Parameter ...... 48 Table 5-1: Test Planes @ the Nodes (analog Signals) ...... 68 Table 5-2: Test Planes @ the Nodes (digital Signals)...... 70 Table 5-3: Operation modes of the Bus Driver ...... 79 Table 5-4: Static Test Cases ...... 103 Table 6-1: Test Planes @ the Active Star for analog Signals...... 338 Table 6-2: Test Planes @ the AS (digital Signals) ...... 339 Table 6-3: Static Test Cases ...... 354 Table 7-1: Test Planes @ the analog Interface...... 453 Table 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer ...... 453 Table 7-3: Static Test Cases ...... 461 Table 8-1: FlexRay Parameters ...... 543 Table 8-2: FlexRay EPL Specification References...... 544
8.5 List of figures Figure 2-1: Local Test Method ...... 15 Figure 2-2: Upper Tester...... 16 Figure 2-3: Lower Tester...... 17 Figure 2-4: Conformance Test Topology...... 20 Figure 2-5: Cable Shield Connection...... 25 Figure 2-6: ESD Load Circuit ...... 26 Figure 2-7: Terminated Node ...... 27 Figure 2-8: Unterminated Node...... 28
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Figure 2-9: Common Mode Choke Implementation...... 28 Figure 2-10: Passive Star Implementation ...... 30 Figure 2-11: Passive Bus Implementation...... 32 Figure 3-1: Usage of Ground Shift ...... 42 Figure 3-2: Location of Ground Shift ...... 43
Figure 3-3: Description of V BAT and V ECU ...... 44 Figure 3-4: Stress signal 4’...... 46 Figure 3-5: Location of the onboard Failures...... 47 Figure 3-6: Failure/Loss of Supplies...... 49 Figure 3-7: Failures of digital Signals TxEN, TxD, BGE, STBN and EN...... 49 Figure 3-8: Failures of Bus Wires BP and BM...... 51 Figure 3-9: Failures of GND Wire...... 51 Figure 3-10: Location of Termination Changes inside a Node ...... 51 Figure 3-11: Dynamic Ground Shift Curve - Input ...... 52 Figure 3-12: Dynamic Ground Shift Curve - possible Output ...... 52 Figure 4-1: Overview of the SOVS Parameters...... 54 Figure 4-2: SOVS Static Tests ...... 55 Figure 4-3: SOVS Communication with Sub Items...... 55 Figure 4-4: SOVS Delay with FlexRay Parameters...... 56 Figure 4-5: SOVS Signal Shape with FlexRay Parameters...... 57 Figure 4-6: SOVS Threshold with FlexRay Parameters ...... 58 Figure 4-7: SOVS Timing with FlexRay Parameters ...... 59 Figure 4-8: SOVS Masks...... 59 Figure 4-9: SOVS Truncation with FlexRay Parameters ...... 60 Figure 4-10: SOVS Mode with Sub Items...... 61 Figure 4-11: SOVS Branch with Sub Items ...... 62 Figure 4-12: SOVS Low Power with Sub Items...... 62 Figure 4-13: SOVS Normal with Sub Items...... 62 Figure 4-14: SOVS Normal with Sub Items...... 63 Figure 4-15: SOVS Normal with Sub Item...... 63 Figure 4-16: SOVS ReceiveOnly...... 63
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Figure 4-17: SOVS Power Supply...... 63 Figure 4-18: SOVS Environment...... 64 Figure 4-19: SOVS Dynamic Low Battery Voltage ...... 64 Figure 4-20: SOVS Ground Shift...... 64 Figure 4-21: SOVS Failure with Sub Items...... 65 Figure 4-22: SOVS Babbling Idiot ...... 65 Figure 4-23: SOVS Loss with several Sub Items ...... 66 Figure 4-24: SOVS Short Circuit with Sub Items...... 66 Figure 4-25: SOVS Termination ...... 66 Figure 4-26: SOVS Functional Class...... 67 Figure 5-1: Test Planes @ the Nodes (analog Signals) ...... 68 Figure 5-2: Test Planes @ the Nodes (digital Signals)...... 69 Figure 5-3: Test Planes for the Oscilloscope...... 71 Figure 5-4: Wake-up Symbol for the Test Pattern ...... 72 Figure 5-5: Test Pattern for the TSS Symbol ...... 73 Figure 5-6: Test Pattern for Data Signal 50/50...... 73 Figure 5-7: Test Pattern for Data Signal 10/90...... 73 Figure 5-8: Test Pattern for Data Signal 90/10...... 74 Figure 5-9: Test Pattern 10Bit Low...... 74 Figure 5-10: Test Pattern 10Bit High...... 74 Figure 5-11: Test Pattern SymbolTxLow_Idle ...... 75 Figure 5-12: Test Pattern for Current Measurement of Bus Wires ...... 75 Figure 5-13: Test Pattern for non suitable Wake-up short idle Phase ...... 75 Figure 5-14: Test Pattern for non suitable Wake-up short low Phase ...... 76 Figure 5-15: Test Pattern for non suitable Wake-up prolonged Pattern ...... 76 Figure 5-16: Observation Point for the Analysis of the Timing Characteristics...... 76 Figure 5-17: Observation Point for the shortened Bits with Low State ...... 77 Figure 5-18: Observation Point for the shortened Bits with High State ...... 78 Figure 5-19: Observation Point for Dynamic Ground Shift ...... 78 Figure 5-20: Observation Window for Eye Diagram ...... 79 Figure 5-21: Communication Matrix A...... 81
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Figure 5-22: Communication with Node 11 as Transmitter (Time Diagram)...... 82 Figure 5-23: Communication with Node 11 as Transmitter (Topology) ...... 82 Figure 5-24: Communication with Node 12 as Transmitter (Time Diagram)...... 83 Figure 5-25: Communication with Node 12 as Transmitter (Topology) ...... 83 Figure 5-26: Communication with Node 1 as Transmitter (Time Diagram)...... 84 Figure 5-27: Communication with Node 1 as Transmitter (Topology) ...... 84 Figure 5-28: Communication with Node 23 as Transmitter (Time Diagram)...... 84 Figure 5-29: Communication with Node 23 as Transmitter (Topology) ...... 85 Figure 5-30: Communication with Node 24 as Transmitter (Time Diagram)...... 86 Figure 5-31: Communication with Node 24 as Transmitter (Topology) ...... 86 Figure 5-32: Communication with Node 24 as observed Transmitter (Time Diagram) ...... 87 Figure 5-33: Communication with Node 24 as observed Transmitter (Topology)..... 87 Figure 5-34: Communication with Node 24 and 1 as Transmitter (Time Diagram)... 88 Figure 5-35: Communication with Node 24 and 1 as Transmitter (Topology) ...... 88 Figure 5-36: Host Command to IUTs...... 89 Figure 5-37: Oscilloscope Services...... 92 Figure 5-38: Pattern Generator Services...... 93 Figure 5-39: Logic Analyzer Services...... 94 Figure 5-40: Logic Analysis System Services ...... 95 Figure 5-41: Power Supply Services ...... 96 Figure 5-42: Network Services ...... 97 Figure 5-43: Test Procedure for Signal Shape, Timing and Delay Test Cases ...... 331 Figure 5-44: Test Procedure for Truncation and Masks Test Cases ...... 332 Figure 5-45: Test Procedure for Mode Test Cases ...... 333 Figure 5-46: Test Procedure for Failure Test Cases ...... 334 Figure 5-47: Test Procedure for Undervoltage Test Cases...... 335 Figure 5-48: Test Procedure for Dynamic Low Battery Cases ...... 336 Figure 6-1: Test Planes @ the Active Star for analog Signals...... 337 Figure 6-2: 4: Branches of the Active Star...... 338 Figure 6-3: Test Planes @ the AS...... 338
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Figure 6-4: Test Planes for the Oscilloscope...... 340 Figure 6-5: Test Pattern for a Babbling Idiot Simulation...... 341 Figure 6-6: Test Signal for Node 1 (Star Setup Delay)...... 341 Figure 6-7: Test Signal for Node 2 (Star Setup Delay)...... 341 Figure 6-8: Observation Point for the Analysis of the Star Delay ...... 342 Figure 6-9: Observation point for the Analysis of the Active Star Truncation ...... 343 Figure 6-10: Observation point for the Analysis of the Active Star SetUp Delay .... 344 Figure 6-11: Communication Matrix C...... 347 Figure 6-12: Communication Matrix E...... 347 Figure 6-13: Communication Single Transmitter ...... 348 Figure 6-14: Communication Node 1 and 2 as Transmitter...... 348 Figure 6-15: Communication with Node 23 as Transmitter (Time Diagram)...... 349 Figure 6-16: Communication with Node 23 as Transmitter (Topology) ...... 349 Figure 6-17: Test Procedure for Delay Test Cases ...... 447 Figure 6-18: Test Procedure for Truncation Test Cases ...... 448 Figure 6-19: Test Procedure for Mode Test Cases ...... 449 Figure 6-20: Test Procedure for Failure Test Cases ...... 450 Figure 6-21: Test Procedure for Dynamic Low Battery Test Cases ...... 451 Figure 7-1: Test Planes @ the analog Interface...... 452 Figure 7-2: Test Planes @ Digital Interfaces of the Active Star for the Logic Analyzer ...... 453 Figure 7-3: Communication Matrix F ...... 455 Figure 7-4: Communication Active Star as transmitter (Timing) ...... 456 Figure 7-5: Communication Active Star as transmitter (Topology) ...... 456 Figure 7-6: Communication Single Transmitter ...... 457 Figure 7-7: Communication Node 1 and AS (Timing)...... 457 Figure 7-8: Communication Node 1 and AS (Topology)...... 458 Figure 7-9: Communication with Node 23 as Transmitter (Time Diagram)...... 458 Figure 7-10: Communication with Node 23 as Transmitter (Topology) ...... 458 Figure 7-11: Test Procedure for Signal Shape, Timing and Delay Test Cases ...... 533 Figure 7-12: Test Procedure for Failure Test Cases ...... 534
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Figure 7-13: Test Procedure for Dynamic Low Battery Test Cases ...... 535 Figure 7-14: Test Procedure for Mode Test Cases ...... 536 Figure 7-15: Test Procedure for Truncation Test Cases ...... 537
8.6 Footnotes 1...... The switch shall be on the nodes and the AS. The connections from the switch to the terminals shall be as short as possible. 2...... Positive terminal of the Ground Shift Generator 3...... Negative terminal of the Ground Shift Generator
4 ...... Z0: impedance characteristic of the used cable. See also chapter 2.4.9.1. 5...... Including passive stars and splices 6...... To be measured from end to end of untwisted area in the connected cables 7...... The time limit reflects the state of the art measurements techniques and potentially needs to be lower 8...... Only if this signal is available 9...... FL means Failure 10 ...... Interruption means floating 11 ...... This termination is done in node 23 12 ...... In case the IUT is able to operate with 42V, otherwise the short circuit voltage is +27V 13 ...... The number of the node depends on the test case 14 ...... The number of the node depends on the test case 15 ...... Only available if Functional Class "BD voltage regulator control" is implemented 16 ...... This combination of mode control signals of the hard wired signals (host interface A) is product specific and is given as an example 17 ...... A message is the whole test pattern (wake-up, TSS and data signal) which is sent by the transmitter and received by the receivers. See also chapter 5.1.2.7. 18 ...... Load on BP/BM: 45 Ω || 100pF 19 ...... Load on BP/BM: 40 Ω || 100pF 20 ...... Load conditions are product specific and documented in the product datasheet.
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21 ...... In case a reference voltage for digital IO is available via a V IO pin, then uV DIG =
uV IO , otherwise uV DIG = uV CC 22 ...... Take into account the footnotes of the electrical physical layer specification for this parameter 23 ...... The values represent the range of the transfer speed which shall be guaranteed by the IUT. 24 ...... Load on BP/BM: 40 Ω || 100pF
25 ...... In case the IUT does not support 42V systems the V BAT shall be +27V 26 ...... In case the IUT does support 42V systems 27 ...... In case the IUT does not support 42V systems 28 ...... Only branch 1 is affected 29 ...... The number of the node depends on the test case 30 ...... The number of the node depends on the test case 31 ...... Load on BP/BM: 40 Ω || 100pF 32 ...... 2×(|| uData0 | - |uData1 ||) / (| uData0 |+| uData1 |) × 100%, Test with (uBP + uBM )/2 = uCM = 2.5V 33 ...... These limitations are only valid for devices that are meant to be used in 42V systems 34 ...... 400ms originated from load dump conditions 35 ...... Load on BP/BM: 40 Ω || 100pF 36 ...... Test signals “Star Setup Delay 1 and 2" are specified in chapter 6.1.3.2 37 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms 38 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms 39 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms
40 ...... In case the IUT does not support 42V systems the V BAT shall be +27V 41 ...... In case the IUT does support 42V systems 42 ...... In case the IUT does not support 42V systems 43 ...... In case the IUT does support 42V systems 44 ...... In case the IUT does not support 42V systems 45 ...... y stands for the number of the branch of the AS
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46 ...... Load on BP/BM: 45 Ω || 100pF 47 ...... Load conditions are product specific and documented in the product datasheet
48 ...... In case a reference voltage for digital IO is available via a V IO pin, then uV DIG =
uV IO , otherwise uV DIG = uV CC 49 ...... Take into account the footnotes of the electrical physical layer specification for this parameter 49b ...... 2×(|| uData0 | - |uData1 ||) / (| uData0 |+| uData1 |) × 100%, Test with (uBP + uBM )/2 = uCM = 2.5V 50 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms 51 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms 52 ...... The low phase shall be long enough to allow the logic state analyzer to detect each received low phase in an observation period of at least 1000ms 53 ...... Currently there is only one data rate specified: 10Mbit/s 54 ...... In the CT the maximum truncation is limited because there is only one AS in the topology
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