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Stacked-FET Based Gaas Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends

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Stacked-FET Based Gaas Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends Stacked-FET based GaAs Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends Gijsbert van der Bent PROMOTIECOMMISSIE: Voorzitter/secretaris prof. dr. J.N. Kok Universiteit Twente Promotor prof. dr. ir. F.E. van Vliet Universiteit Twente Referent dr. ir. W.J.A de Heij Thales Netherlands Leden prof. dr. ir. B. Nauta Universiteit Twente prof. dr. A.A. Stoorvogel Universiteit Twente prof. S. Mahon Macquarie University prof. dr. D.M.W. Leenaerts Technische Universiteit Eindhoven The work presented in this thesis has been supported by the Dutch Radar Centre of Expertise (D-RACE), a strategic alliance of Thales Netherlands and TNO. Cover: Ilse Modder, www.ilsemodder.nl Printed by Gildeprint Drukkerijen. ISBN: 978-90-365-4766-6 DOI: 10.3990/1.9789036547666 Copyright © 2019 by Gijsbert van der Bent All rights reserved. No parts of this thesis may be reproduced, stored in a retrieval system or transmitted in any form or by any means without permission of the author. Alle rechten voorbehouden. Niets uit deze uitgave mag worden vermenigvuldigd, in enige vorm of op enige wijze, zonder voorafgaande schriftelijke toestemming van de auteur. Stacked-FET based GaAs Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. T.T.M. Palstra, volgens besluit van het College voor Promoties in het openbaar te verdedigen op vrijdag 3 mei 2019 om 16:45 uur door Gijsbert van der Bent geboren op 11 februari 1975 te Leiden Dit proefschrift is goedgekeurd door: De promotor: prof. dr. ir. F.E. van Vliet Contents 1 Introduction 1 1.1 Historical Context . .1 1.1.1 Active Electronically Scanned Arrays . .2 1.1.2 Monolithic Microwave Integrated Circuits . .3 1.2 Power amplification in AESA radar front-ends . .3 1.3 This thesis . .5 2 Power Amplifiers Employing Stacked-FETs 7 2.1 Introduction . .7 2.1.1 Semiconductor Technology Overview . .7 2.1.2 Radar applications . .8 2.1.3 Power Amplifier Terminology . .9 2.1.4 State of the Art in AESA Power Amplifiers . 12 2.1.5 Packaging . 15 2.2 Power Amplifier Classes . 16 2.2.1 Classification . 16 2.2.2 Class-B Analysis . 17 2.2.3 Drain Bias Voltage Reduction . 20 2.3 The Concept of Transistor Stacking . 21 2.3.1 Introduction . 21 2.3.2 Stacked-FETs in Microwave PAs . 22 2.3.3 Prior Art . 24 2.4 Modelling and Simulation . 25 2.4.1 Transistor modelling and characterisation . 26 2.4.2 Simulation Methods . 27 2.4.3 Stability analysis . 28 2.5 Conclusion . 32 3 Stacked-FET dimensioning 33 3.1 Introduction . 33 3.2 Transistor 1, Common Source (CS) transistor . 35 i CONTENTS 3.2.1 Optimum load . 35 3.2.2 Voltage relations . 37 3.3 Transistor 2 to N, Degenerated Common Gate transistors . 37 3.3.1 DCG excitation . 37 3.3.2 Voltage equalisation . 39 3.3.3 Current equalisation . 40 3.3.4 Load of transistor N . 44 3.4 Parasitic capacitances . 45 3.4.1 Translation of CS transistor load . 46 3.4.2 Effect on voltage equalisation . 47 3.4.3 Effect on current equalisation . 47 3.4.4 Stacked-FET load . 48 3.5 Power dependency of model parameter values . 49 3.5.1 Effective model parameter values from harmonic balance simulation . 49 3.5.2 Effective model parameter values from small-signal measurements . 50 3.5.3 Comparison of the simulated and extracted model parameters . 53 3.6 Numerical example . 54 3.6.1 Gate admittance for voltage equalisation . 54 3.6.2 Component values for current equalisation . 55 3.6.3 Stacked-FET load . 57 3.7 Bandwidth of Stacked-FET . 59 3.7.1 Bode-Fano limit . 59 3.7.2 Bode-Fano limit in practise . 62 3.7.3 Influence of matching ratio . 64 3.8 Demonstration . 65 3.8.1 Selection of current equalisation option . 65 3.8.2 Gate biasing of the Stacked-FET . 65 3.8.3 Layout . 68 3.8.4 Results . 69 3.9 Load mapping of DCG transistors . 71 3.9.1 Out-of-band termination . 71 3.9.2 Effect on harmonic load . 72 3.10 Conclusion . 78 4 Custom-Transistor Modelling 81 4.1 Introduction . 81 4.2 Modelling methodology . 83 4.3 Gate-Finger Model Extraction . 87 4.3.1 Simulation of extrinsic reactances . 87 ii CONTENTS 4.3.2 Access resistances . 89 4.3.3 Intrinsic parameters extraction . 90 4.4 Custom-transistor model construction . 92 4.5 Conclusion . 97 5 Stability analysis 99 5.1 Introduction . 99 5.2 Stability of constitutive transistors . 100 5.2.1 CS-FET . 102 5.2.2 DCG-FET . 104 5.3 Stability of Stacked-FET . 112 5.3.1 Conditional stability evaluation in transistor stacks . 112 5.3.2 Implications for Stacked-FET design . 116 5.4 Amplifier stability . 117 5.4.1 Stability analysis on amplifier . 118 5.4.2 Biasing of DCG gates . 118 5.5 Conclusion . 119 6 Stacked-FET Power Amplifiers 121 6.1 Introduction . 121 6.2 Amplifier design . 122 6.2.1 Design procedure . 122 6.2.2 Power stages . 125 6.2.3 HPA topology . 126 6.2.4 A priori amplifier performance estimation . 128 6.2.5 Interpretation of WIN reliability data . 130 6.2.6 Thermal model . 131 6.2.7 Practical gate biasing . 132 6.3 HPA 1: 20 W, Single-stage amplifier . 135 6.3.1 CS transistor performance . 135 6.3.2 Single-stage amplifier architecture . 137 6.3.3 Stability of the Stacked-FET . 139 6.3.4 Thermal analysis . 141 6.3.5 Matching networks . 142 6.3.6 Simulations . 146 6.3.7 Measured results . 147 6.4 HPA 2: 30 W, two-stage amplifier . 150 6.4.1 Two-stage HPA architecture . 150 6.4.2 Stack design including stability constraints . 152 6.4.3 Thermal analysis . 156 6.4.4 Matching networks . 158 6.4.5 Simulations . 163 iii CONTENTS 6.4.6 Measured results . 165 6.5 Conclusion . 169 7 Amplifier yield and screening 171 7.1 Introduction . 171 7.2 Process variations . 172 7.2.1 Process control monitoring . 172 7.2.2 Monte-Carlo analysis on HPA 1 . 173 7.3 Screening . 176 7.3.1 HPA screening procedures . 176 7.4 Pinch-off screening . 178 7.4.1 Procedure and simulations . 178 7.4.2 Measurements on test-structure . 182 7.5 Breakdown screening . 182 7.5.1 Procedure and simulations . 183 7.5.2 Measurements on test-structures . 187 7.6 Conclusion . 189 8 Conclusions and outlook 191 8.1 Thesis overview . 191 8.2 Comparison to previously published results . 193 8.3 Conclusions . 194 8.4 Original contributions . ..
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