WIDE BAND GAP SEMICONDUCTOR TECHNOLOGY (Sic Mesfets and Gan Hemts) and THEIR RESPONSE in DIFFERENT CLASSES of POWER AMPLIFIERS
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Bias Circuits for RF Devices
Bias Circuits for RF Devices Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul A lot of RF schematics mention: “bias circuit not shown”; when actually one of the most critical yet often overlooked aspects in any RF circuit design is the bias network. The bias network determines the amplifier performance over temperature as well as RF drive. The DC bias condition of the RF transistors is usually established independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration. A transistor amplifier must possess a DC biasing circuit for a couple of reasons. • We would require two separate voltage supplies to furnish the desired class of bias for both the emitter-collector and the emitter-base voltages. • This is in fact still done in certain applications, but biasing was invented so that these separate voltages could be obtained from but a single supply. • Transistors are remarkably temperature sensitive, inviting a condition called thermal runaway. Thermal runaway will rapidly destroy a bipolar transistor, as collector current quickly and uncontrollably increases to damaging levels as the temperature rises, unless the amplifier is temperature stabilized to nullify this effect. Amplifier Bias Classes of Operation Special classes of amplifier bias levels are utilized to achieve different objectives, each with its own distinct advantages and disadvantages. The most prevalent classes of bias operation are Class A, AB, B, and C. All of these classes use circuit components to bias the transistor at a different DC operating current, or “ICQ”. When a BJT does not have an A.C. -
A Comparison of E/D-MESFET Gallium Arsenide and CMOS Silicon for VLSI Processor Design Mark K
Purdue University Purdue e-Pubs Department of Electrical and Computer Department of Electrical and Computer Engineering Technical Reports Engineering 12-1-1985 A Comparison of E/D-MESFET Gallium Arsenide and CMOS Silicon for VLSI Processor Design Mark K. Bettinger Purdue University Follow this and additional works at: https://docs.lib.purdue.edu/ecetr Bettinger, Mark K., "A Comparison of E/D-MESFET Gallium Arsenide and CMOS Silicon for VLSI Processor Design" (1985). Department of Electrical and Computer Engineering Technical Reports. Paper 551. https://docs.lib.purdue.edu/ecetr/551 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. A Comparison of E/D-MESFET Gallium Arsenide and CMOS Silicon for VLSI Processor Design Mark K. Bettinger TR-EE 85-18 December 1985 School of Electrical Engineering Purdue University West Lafayette, Indiana 47907 A COMPARISON OF E/D-MESFET GALLIUM ARSENIDE AND CMOS SILICON FOR VLSI PROCESSOR DESIGN Mark K. Bettinger TR-EE 85-18 December 1985 ACKNOWLEDGMENTS I acknowledge the guidance and assistance of my major professor, Veljko Milutinovic. He has provided opportunities to learn that I appreciate. I am also indebted to RCA-ATL for their support and guidance as well as their funding. I would also like to thank those at RCA-ATL who have provided assistance: Tom Geigel, Bill Heagerty, Walt Helbig, Wayne Moyers, Jeff Prid- more, and Rich Zeigert. Little of this work would have been completed without the support of my officemates. I also thank my good friend Lee Bissonette for all of her cheerful assistance. -
The Bipolar Junction Transistor (BJT)
The Bipolar Junction Transistor (BJT) Introduction he transistor, derived from transfer resistor, is a three terminal device whose resistance between two terminals is controlled by the third. The term bipolar reflects the fact that T there are two types of carriers, holes and electrons which form the currents in the transistor. If only one carrier is employed (electron or hole), it is considered a unipolar device like field effect transistor (FET). The transistor is constructed with three doped semiconductor regions separated by two pn junctions. The three regions are called Emitter (E), Base (B), and Collector (C). Physical representations of the two types of BJTs are shown in Figure (1–1). One type consists of two n -regions separated by a p-region (npn), and the other type consists of two p-regions separated by an n- region (pnp). Figure (1-1) Transistor Basic Structure The outer layers have widths much greater than the sandwiched p– or n–type layer. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity of the base (increases the resistance) due to the limited number of “free” carriers. Figure (1-2) shows the schematic symbols for the npn and pnp transistors 1 College of Electronics Engineering - Communication Engineering Dept. Figure (1-2) standard transistor symbol Transistor operation Objective: understanding the basic operation of the transistor and its naming In order for the transistor to operate properly as an amplifier, the two pn junctions must be correctly biased with external voltages. -
WIDE BANDGAP POWER SEMICONDUCTOR DEVICES Teaming List
WIDE BANDGAP POWER SEMICONDUCTOR DEVICES Teaming List Updated: July 8, 2013 This document contains the list of potential teaming partners for the WIDE BANDGAP POWER SEMICONDUCTOR DEVICES, solicited in RFI-0000004 and is published on ARPA-E eXCHANGE (https://arpa-e-foa.energy.gov), ARPA-E’s online application portal. This list will periodically undergo an update as organizations request to be added to this teaming list. If you wish for your organization to be added to this list please refer to https://arpa-e-foa.energy.gov/ for instructions. By enabling and publishing the WIDE BANDGAP POWER SEMICONDUCTOR DEVICES Teaming List, ARPA-E is not endorsing or otherwise evaluating the qualifications of the entities that are self-identifying themselves for placement on this Teaming List. Organization Name Organization Area of Background Website Email Phone Address Type Expertise ABB US Corporate Research Business > 940 Main Campus Center, ABB 1000 [email protected] +1 919 856 Drive, Raleigh NC Inc. Le Tang Employees Grid Power and Automation www.abb.com .com 3878 27606 APEI, Inc. specializes in developing and manufacturing high power density and high efficiency power electronic solutions and products based on wide bandgap (WBG) technologies. APEI, Inc.’s commercial ISO9001 and AS9100 certified Class 1000 manufacturing facility offers custom power substrate manufacturing, power module manufacturing, and microelectronics assembly Technologies manufacturing services. The manufacturing lines have that facilitate been designed to deliver the highest quality product for low-cost, high- those applications that need the best performance and performance, reliability, including a specialization in high temperature and/or plug- electronics manufacturing processes to 400 C. -
FET) Field Effect Transistor Projects
50 (FET) Field Effect Transistor Projects F. G. RAYER, T. ENG. (CEI), ASSOC. IERE 50 (F.E.T.) Field Effect Transistor Projects by F. G. RAYER, T. Eng. (CEI), Assoc. IERE BABANI PRESS The Publishing Division of Babani Trading and Finance Co. Ltd. The Grampians Shepherds Bush Road London W6 7NF England INTRODUCTION Field effect transistors find application in a wide variety of cir- cuits. The projects described here include radio frequency am- plifiers and converters, test equipment and receiver aids, tuners, receivers, mixers and tone controls, as well as various miscella- neous devices which are useful in the home. It will be found that in general the actual FET used is not criti- cal, and many suitable types will perform satisfactorily. The FET is a low noise, high gain device with many uses, and the dual gate FET is of particular utility for mixer and other applications. This book should be found to contain something of particular interest for every class of enthusiast - short wave-listener, radio amateur, experimenter, or audio devotee. FET Operation Figure 1 will help clarify the working of the field effect transis- tor. “A” represents the essential elements of the device, which has Source lead 5, Gate lead G, and Drain connection D. The path for current is from Source to Drain through the semiconduc- tor material, this path being termed the channel. With the N-chan- nel FET, the carriers are electrons. The Source is connected to negative of the supply, and Drain to positive. P-type gates are formed on the N-type channel, providing PN junctions. -
NOVEL MODELLING METHODS for MICROWAVE Gaas MESFET DEVICE ZHONG ZHENG a THESIS SUBMITTED for the DEGREE of DOCTOR of PHILOSOPHY
CORE Metadata, citation and similar papers at core.ac.uk Provided by ScholarBank@NUS NOVEL MODELLING METHODS FOR MICROWAVE GaAs MESFET DEVICE ZHONG ZHENG (M.Eng, University of Science and Technology of China, P.R.C) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2010 i Acknowledgements First of all, I would like to deeply thank my supervisors, Professor Leong Mook Seng and A/Prof. Ooi Ban Leong, who have led me into this interesting world of device modelling, and given me full support for my study. I am here to express my sincere gratitude to them for their patient guidance, invaluable advices and discussions. I believe what I have learnt from them will always lead me ahead. I also want to thank other faculty staffs in NUS Microwave & RF group: Prof Yeo Swee Ping, Prof Li Le-Wei, Dr. Chen Xu Dong, Dr. Guo Yong Xin, Dr. Koen Mouthaan, and Dr. Hui Hon Tat, etc. for their significant guidance and support. I am also very grateful to these supporting staffs in NUS Microwave & RF group: Madam Guo Lin, Mr. Sing Cheng-Hiong and Madam Lee Siew-Choo for their kind assistances in PCB/MMIC fabrication and measurement. My gratitude also goes to all the friends in microwave division, for their kind help and for the wonderful time we shared together. Last but not least, I would like to thank my family, for their endless support and encouragement, which always be the greatest treasure of my life. ii Table of Contents Acknowledgements ……..………………………..……………..…...…………………i Table of Contents ...…………………………...……………………………………….ii Summary ……………………………………...…….…………………………………vi List of Figures……………………………………….……………………………..…viii List of Tables ….……………………………………..………….……………………xiii List of Symbols ……………………………………….……………….….……….….xv Chapter 1 Introduction ........................................................................................ -
Transition of Sic MESFET Technology from Discrete Transistors to High Performance MMIC Technology
Transition of SiC MESFET Technology from Discrete Transistors to High Performance MMIC Technology J.W. Milligan, J. Henning, S.T. Allen, A.Ward, P. Parikh, R.P. Smith, A. Saxler, Y. Wu, and J. Palmour Cree, Inc., 4600 Silicon Drive, Durham, NC 27703, (919) 313-5564, [email protected] Keywords: SiC, MESFET, MMIC, HPSI, HTOL, GaN Abstract Significant progress has been made in the development of SiC MESFET DEVICE PERFORMANCE SiC MESFETs and MMIC power amplifiers manufactured on 3-inch high purity semi-insulating (HPSI) 4H-SiC substrates. SiC MESFETs continue to mature in performance and MESFETs with a MTTF of over 200 hours when operated at a manufacturing process stability. These devices now TJ =295 °C are presented. High power SiC MMIC amplifiers achieve a power density of approximately 4.0 W/mm and are shown with excellent yield and repeatability using a power added efficiencies greater than 50% on a regular released foundry process. GaN HEMT operating life of over basis. As an example, Figure 2 shows a 1.0 mm gate 500 hours at a TJ =160 °C is shown. Finally, GaN HEMTs with 30 W/mm RF output power density are reported. periphery MESFET operating at 50V producing 4.0 watts of output power at 66% drain efficiency (54% PAE) at 3.5 GHz. INTRODUCTION SiC MESFETs offer significant advantages for next CW Load Pull Data at 3.5 GHz generation commercial and military systems. Increased 40 60 CW Power power density and higher operating voltage enable higher 36 PAE 50 performance, lighter weight, and wider bandwidth systems. -
A Novel 4H-Sic MESFET with a Heavily Doped Region, a Lightly Doped Region and an Insulated Region
micromachines Article A Novel 4H-SiC MESFET with a Heavily Doped Region, a Lightly Doped Region and an Insulated Region Hujun Jia *, Mengyu Dong , Xiaowei Wang, Shunwei Zhu and Yintang Yang School of Microelectronics, Xidian University, Xi’an 710071, China; [email protected] (M.D.); [email protected] (X.W.); [email protected] (S.Z.); [email protected] (Y.Y.) * Correspondence: [email protected]; Tel.: +86-029-8820-2562 Abstract: A novel 4H-SiC MESFET was presented, and its direct current (DC), alternating current (AC) characteristics and power added efficiency (PAE) were studied. The novel structure improves the saturation current (Idsat) and transconductance (gm) by adding a heavily doped region, reduces the gate-source capacitance (Cgs) by adding a lightly doped region and improves the breakdown voltage (Vb) by embedding an insulated region (Si3N4). Compared to the double-recessed (DR) structure, the saturation current, the transconductance, the breakdown voltage, the maximum oscillation frequency (fmax), the maximum power added efficiency and the maximum theoretical output power density (Pmax) of the novel structure is increased by 24%, 21%, 9%, 11%, 14% and 34%, respectively. Therefore, the novel structure has excellent performance and has a broader application prospect than the double recessed structure. Keywords: SiC; Metal-Semiconductor Field Effect Transistor (MESFET); heavily doped region; power added efficiency (PAE) Citation: Jia, H.; Dong, M.; Wang, X.; Zhu, S.; Yang, Y. A Novel 4H-SiC MESFET with a Heavily Doped Region, a Lightly Doped Region and 1. Introduction an Insulated Region. Micromachines The third-generation semiconductor is the development trend of the semiconductor. -
Metal Semiconductor FET - MESFET�
SMA5111 - Compound Semiconductors Lecture 9 - Metal-Semiconductor FETs - Outline • Device structure and operation Concept and structure:� General structure� Basis of operation; device types� Terminal characteristics Gradual channel approximation w. o. velocity saturation Velocity saturation issues Characteristics with velocity saturation Small signal equivalent circuits High frequency performance • Fabrication technology Process challenges: (areas where heterostructures can make life easier and better) 1. Semi-insulating substrate; 2. M-S barrier gate; 3. Threshold control; 4. Gate resistance; 5. Source and drain resistances Representative sequences: 1. Mesa-on-Epi; 2. Proton isolation; 3. n+/n epi w. recess; 4. Direct implant into SI-GaAs C. G. Fonstad, 3/03 Lecture 9 - Slide 1� BJT/FET Comparison - cont.� Base/ Emitter/ Collector/ Channel Source Drain 0 wB or L Controlled by vEB in a BJT; by vGS in an FET vCE or vDS C. G. Fonstad, 3/03 0 wB or L Lecture 9 - Slide 2 BJT/FET Comparison - cont.� OK, that's nice, but there is more to the� difference than how the barrier is controlled� BJT FET Charge minority majority carriers in base in channel Flow diffusion drift mechanism in base in channel Barrier direct contact change induced control made to base by gate electrode The nature of the current flow, minority diffusion vs� majority drift, is perhaps the most important difference.� C. G. Fonstad, 3/03 Lecture 9 - Slide 3� FET Mechanisms - MOSFET and JFET/MESFET� MOSFET� Induced n-type channel JFET Doped n-type channel C. G. Fonstad, 3/03� Lecture 9 - Slide 4 Junction Field Effect Transistor (JFET)� Reverse biasing the gate-source junction increases depletion width under gate and constricts the n-type conduction path between the source and drain. -
California State University, Northridge A
CALIFORNIA STATE UNIVERSITY, NORTHRIDGE A COMPREHENSIVE MODEL OF FREQUENCY DISPERSION OF GALLIUM NITRIDE MESFET A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Rumman Raihan August 2018 Copyright by Rumman Raihan 2018 ii The graduate project of Rumman Raihan is approved: …………………………………….. ……………. Dr. Sembiam Rengarajan Date ……………………………………. …………….. Dr. Jack Ou Date ……………………………………… …………… Dr. Somnath Chattopadhyay, Chair Date California State University, Northridge iii ACKNOWLEDGEMENT At the very beginning, I would like to express my best and foremost gratitude towards Dr. Somnath Chattopadhyay for his help and guidance not just in this project, but also throughout my entire Graduate study period. He opened the door of his vast knowledge towards me and I am very much thankful to him for letting me work under his supervision. I also forward my gratitude towards Dr. Sembiam Rengarajan and Dr. Jack Ou to be on the graduate committee and spending their valuable time to guide me throughout the project. I express my love and gratitude to my mother and my family, my uncle Mr. Mohammad Islam and his family for their mental and financial support. iv DEDICATION This work is dedicated to my departed father Mr. K. M. Nur-ul-Alam (may his soul rest in peace) and my loving mother Mrs. Nilufa Akter. v TABLE OF CONTENTS COPYRIGHT PAGE..…………………………………………………………….............ii SIGNATURE PAGE..….…………………………………………………………...........iii ACKNOWLEDGEMENT…………………………………………………......................iv -
THE DESIGN, SIMULATION and FABRICATION of a GALLIUM ARSENIDE MONOLITHIC SAMPLE and HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. Mcgi
THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE MONOLITHIC SAMPLE AND HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. McGill University A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June 1986 © Willem G. Durtler 1986 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of ELECTRICAL ENGINEERING The .University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 1986 06 12 ABSTRACT This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold circuit. The literature relevant to high-speed electronic sampling is reviewed, and the different types of high• speed sampling circuits are discussed. The requirements of a sampling circuit for use in a distributed sampling amplifier are analyzed, and it is found that the most important requirement is a high input impedance. A circuit suitable for monolithic integration is designed and analyzed using the computer program mwSPICE. The different fabrication technologies for gallium arsenide integrated circuits are discussed, with emphasis on the self-aligned gate technologies, which can give reduced parasitic source and drain resistances. -
Metal Semiconductor Field Effect Transistors Mesfet Mesfet
METAL SEMICONDUCTOR FIELD EFFECT TRANSISTORS MESFET MESFET MESFET = Metal Semiconductor Field Effect Transistor = Schottky gate FET . The MESFET consists of a conducting channel positioned between a source and drain contact region. The carrier flow from source to drain is controlled by a Schottky metal gate . The control of the channel is obtained by varying the depletion layer width underneath the metal contact which modulates the thickness of the conducting channel and thereby the current. MESFET MESFET The key advantage of the MESFET is the higher mobility of the carriers in the channel as compared to the MOSFET. The disadvantage of the MESFET structure is the presence of the Schottky metal gate. It limits the forward bias voltage on the gate to the turn-on voltage of the Schottky diode. This turn-on voltage is typically 0.7 V for GaAs Schottky diodes. The threshold voltage therefore must be lower than this turn-on voltage. As a result it is more difficult to fabricate circuits containing a large number of enhancement-mode MESFET. Basic Structure GaAs MESFETs are the most commonly used and important active devices in microwave circuits. In fact, until the late 1980s, almost all microwave integrated circuits used GaAs MESFETs. Although more complicated devices with better performance for some applications have been introduced, the MESFET is still the dominant active device for power amplifiers and switching circuits in the microwave spectrum . Basic Structure Schematic and cross section of a MESFET Basic Structure The base material on which the transistor is fabricated is a GaAs substrate. A buffer layer is epitaxially grown over the GaAs substrate to isolate defects in the substrate from the transistor.