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THE DESIGN, SIMULATION and FABRICATION of a GALLIUM ARSENIDE MONOLITHIC SAMPLE and HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. Mcgi

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THE DESIGN, SIMULATION and FABRICATION of a GALLIUM ARSENIDE MONOLITHIC SAMPLE and HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. Mcgi THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE MONOLITHIC SAMPLE AND HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. McGill University A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June 1986 © Willem G. Durtler 1986 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of ELECTRICAL ENGINEERING The .University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 1986 06 12 ABSTRACT This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold circuit. The literature relevant to high-speed electronic sampling is reviewed, and the different types of high• speed sampling circuits are discussed. The requirements of a sampling circuit for use in a distributed sampling amplifier are analyzed, and it is found that the most important requirement is a high input impedance. A circuit suitable for monolithic integration is designed and analyzed using the computer program mwSPICE. The different fabrication technologies for gallium arsenide integrated circuits are discussed, with emphasis on the self-aligned gate technologies, which can give reduced parasitic source and drain resistances. The processing steps for the refractory metal self-aligned gate technology developed for this thesis at the University of British Columbia are given in detail. DC measurement procedures for MESFETs and Schottky diodes are given and results are presented for self-aligned gate MESFETs fabricated at UBC. These results indicate that the refractory metal self-aligned gate process developed at UBC should be suitable for the fabrication of the monolithic sample-and-hold circuit. TABLE OF CONTENTS ABSTRACT ii LIST OF TABLES v LIST OF FIGURES vi ACKNOWLEDGEMENT ix 1 INTRODUCTION 1 1.1 Overview 1 1.2 Requirement for high-speed monolithic integrated circuits 1 1.3 Elements of monolithic microwave integrated circuits 3 1.4 Semiconductor materials for MMICs 4 1.5 The sampling amplifier concept 7 2 HIGH-SPEED SAMPLING 10 2.1 Sample-and-hold waveforms and definitions 10 2.2 Sample-and-hold design considerations 12 2.3 Basic sample-and-hold circuits 12 2.4 Sampling switches 15 2.5 Survey of literature on sample-and-hold circuits 20 2.5.1 Discrete mechanical sampling heads 21 2.5.2 Discrete solid state samplers 22 2.5.3 Monolithic sample-and-hold circuits 23 2.5.4 Theoretical analysis and modeling of high-speed sample-and-hold circuits 27 3 DESIGN AND SIMULATION 30 3.1 System requirements 30 3.2 Buffer amplifiers 40 3.3 The sampling switch 47 4 PROCESSING TECHNOLOGY FOR GaAs MESFETs AND MMICs 56 4.1 Introduction 56 4.2 Review of GaAs MESFET fabrication technologies 58 4.2.1 Active layer formation 59 4.2.2 Device isolation 62 4.2.3 Gate formation 65 4.2.4 Ohmic contact formation 71 4.2.5 Passive components 74 4.3 UBC refractory metal self-aligned gate MESFET fabrication technology 77 5 MEASUREMENT TECHNIQUES AND RESULTS 89 5.1 Introduction 89 5.2 Diode measurements 90 5.3 Transistor Measurements 94 - iii- 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 107 REFERENCES 111 APPENDIX Al mwSPICE listing for transfer curve analysis 115 A2 mwSPICE listing for buffer amplifier transient response 116 A3 mwSPICE listing for dual-gate switch transient analysis 117 -iv- LIST OF TABLES TABLE DESCRIPTION PAGE 1., 1 Components for monolithic microwave integrated circuits 5 1.. 2 Important properties of silicon and gallium arsenide 6 4,. 1 Detailed self-aligned gate process log 80 5.. 1 Typical self-aligned gate MESFET model parameters 105 -V- LIST OF FIGURES FIGURE TITLE PAGE 1.1 Sampling amplifier block diagram. 8 2.1 Sample-and-hold waveforms and definitions ( after Stafford 11 et al. [13] ). 2.2 Basic sample-and-hold circuits: (a) simplest, (b) output 13 buffered, (c) input and output buffered, (d) integrator. 2.3 Multistage sample-and-hold circuits: (a) feedback, 16 (b) ground referenced. 2.4 Six-diode sampling switch. 17 2.5 FET sampling switch: (a) n-channel MOSFET, (b) n-channel MESFET. 19 2.6 Silicon monolithic sample-and-hold circuit ( after Stafford 25 et al. [13] ) . 2.7 GaAs monolithic sampling switch ( after Saul [17] ). 26 2.8 GaAs monolithic sample-and-hold circuit ( after Harrold 28 et al. [19] ) . 3.1 Block diagram of the sampling amplifier showing the critical 31 propagation times. 3.2 Input delay line low frequency equivalent circuit. 34 3.3 Input dc loss as a function of the number of channels: (a) Rin= 1 kn, (b) Rin= 10 kfl 35 3.4 Input delay line high frequency equivalent circuit. 36 3.5 Input ac loss as a function of channel position: 2 _ (a) Rin= 10 kfi, wCin= 10" , (b) Rin= 10 kQ, wCin= 10 * 38 3.6 Simulated return loss and transmission loss of the loaded 39 input delay line. 3.7 Monolithic FET buffer amplifier ( after Hornbuckle et al. [23] ). 42 3.8 Buffer amplifier simplified low frequency small signal 43 equivalent circuit. 3.9 Simulated buffer amplifier frequency response. 45 -vi- FIGURE TITLE PAGE 3.10 Simulated buffer amplifier transient response. 46 3.11 Single-gate MESFET switch: (a) schematic diagram, (b) ON state 48 equivalent circuit, (c) OFF state equivalent circuit. 3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state 51 equivalent circuit, (c) OFF state equivalent circuit. 3.13 Simulated single-gate GaAs MESFET switch transient response. 54 3.14 Simulated dual-gate GaAs MESFET switch transient response. 55 4.1 Device isolation methods: (a) selective ion-implantation, 63 (b) isolation ion-implantation, (c) mesa etching. 4.2 Buried-channel refractory metal self-aligned-gate process 66 ( after Yokoyama et al. [42] ). 4.3 T-structure self-aligned-gate process 68 ( after Levy et al. [43] ). 4.4 Self-Aligned Implantation of N+-layer Technology ( SAINT ) 70 process ( after Yamasaki et al. [45] ). 4.5 Sidewall-assisted pattern inversion process ( after 72 Hagio et al. [46] ). 4.6 Airbridge fabrication process. 76 4.7 UBC refractory metal self-aligned-gate fabrication process flowchart. 79 4.8 Sample-and-hold mask layout. 86 4.9 Photomicrograph of sample-and-hold chip. 87 4.10 Scanning electron micrograph of dual gate MESFET. 88 5.1 Typical capacitance/voltage doping profile. 92 5.2 Typical diode current/voltage plot. 93 5.3 Symmetric MESFET model equivalent circuit ( after Curtice et al. [50] ). 95 5.4 Small-gate-length MESFET depletion region. 97 5.5 Typical plot of 7lDS versus VGS used to determine threshold voltage VT and gain parameter K. 99 -vii- FIGURE TITLE PAGE 5.6 Measurement setup used to determine Rs and RD. 101 5.7 Typical end-resistance plot giving Rs. 102 5.8 Typical plot of transconductance gm versus VGS. 104 5.9 Self-aligned gate MESFET transfer curves: ( ) measured, ( • • • ) simulated 105 -viii- ACKNOWLEDGEMENT Many people helped in direct or indirect ways in the research and preparation of this thesis. In particular, I would like to thank Dr. L. Young for his encouragement and guidance during all stages of my graduate work. Peter Townsley was largely responsible for the acual device fabrication. I also gratefully acknowledge the contributions of my fellow graduate students, Kim Tan, Dave Hui, Salam Dindo and Wade Tang, as well as Rod Walker for his proofreading. Finally, I would like to thank my colleagues and management at Harris-Farinon Canada, Ltd., of Dorval, Quebec, for their active support and encouragement. - ix- CHAPTER 1 INTRODUCTION 1.1 Overview This thesis describes the design and fabrication of a monolithic, high• speed, sample-and-hold amplifier for use in signal processing applications. The introduction will discuss the requirements for high-speed monolithic circuits, the application of gallium arsenide and the fundamentals of gallium arsenide monolithic microwave integrated circuits ( GaAs MMICs ), and the concept of distributed sample-and-hold amplification. Chapter 2 will discuss the theoretical and practical aspects of high speed sample-and-hold circuits and give an overview of published work in the field. In chapter 3 the design of a sample-and-hold amplifier suit• able for use in a distributed amplifier will be described and simulation results using the computer program mwSPICE will be given. In chapter 4 the development of a self-aligned gate GaAs processing technology at the University of British Columbia will be described. Measurement procedures and experimental results will be given in chapter 5, and finally chapter 6 will present conclusions and suggestions for future work. 1.2 Requirement for high-speed monolithic integrated circuits In the past there has been an evolution to faster and more complex circuits, with circuits of a given complexity becoming ever faster and circuits of a given speed becoming ever more complex. At the same time -1- these circuits are becoming both cheaper and physically smaller in size. These developments are spurred by the requirement for relatively cheap, high volume subsystems in areas such as signal processing, phased array radar and real time graphics. Phased array radar, for example, uses transmit power amplifiers, receive low noise amplifiers, transmit/receive switches and digitally controlled phase shifters, all which must operate at the radar frequency of typically 8 GHz.
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