THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE

MONOLITHIC SAMPLE AND HOLD CIRCUIT

by

WILLEM G. DURTLER

B.Eng. McGill University

A THESIS SUBMITTED IN PARTIAL FULFILMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in

THE FACULTY OF GRADUATE STUDIES

DEPARTMENT OF ELECTRICAL ENGINEERING

We accept this thesis as conforming

to the required standard

THE UNIVERSITY OF BRITISH COLUMBIA

June 1986

© Willem G. Durtler 1986 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.

Department of ELECTRICAL ENGINEERING

The .University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3

1986 06 12 ABSTRACT

This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold circuit. The literature relevant to high-speed electronic sampling is reviewed, and the different types of high• speed sampling circuits are discussed. The requirements of a sampling circuit for use in a distributed sampling amplifier are analyzed, and it is found that the most important requirement is a high input impedance. A circuit suitable for monolithic integration is designed and analyzed using the computer program mwSPICE.

The different fabrication technologies for gallium arsenide integrated circuits are discussed, with emphasis on the self-aligned gate technologies, which can give reduced parasitic source and drain resistances. The processing steps for the refractory metal self-aligned gate technology developed for this thesis at the University of British Columbia are given in detail. DC measurement procedures for MESFETs and Schottky diodes are given and results are presented for self-aligned gate MESFETs fabricated at UBC.

These results indicate that the refractory metal self-aligned gate process developed at UBC should be suitable for the fabrication of the monolithic sample-and-hold circuit. TABLE OF CONTENTS

ABSTRACT ii

LIST OF TABLES v

LIST OF FIGURES vi

ACKNOWLEDGEMENT ix

1 INTRODUCTION 1 1.1 Overview 1 1.2 Requirement for high-speed monolithic integrated circuits 1 1.3 Elements of monolithic microwave integrated circuits 3 1.4 Semiconductor materials for MMICs 4 1.5 The sampling amplifier concept 7

2 HIGH-SPEED SAMPLING 10 2.1 Sample-and-hold waveforms and definitions 10 2.2 Sample-and-hold design considerations 12 2.3 Basic sample-and-hold circuits 12 2.4 Sampling switches 15 2.5 Survey of literature on sample-and-hold circuits 20 2.5.1 Discrete mechanical sampling heads 21 2.5.2 Discrete solid state samplers 22 2.5.3 Monolithic sample-and-hold circuits 23 2.5.4 Theoretical analysis and modeling of high-speed sample-and-hold circuits 27

3 DESIGN AND SIMULATION 30 3.1 System requirements 30 3.2 Buffer amplifiers 40 3.3 The sampling switch 47

4 PROCESSING TECHNOLOGY FOR GaAs MESFETs AND MMICs 56 4.1 Introduction 56 4.2 Review of GaAs MESFET fabrication technologies 58 4.2.1 Active layer formation 59 4.2.2 Device isolation 62 4.2.3 Gate formation 65 4.2.4 Ohmic contact formation 71 4.2.5 Passive components 74 4.3 UBC refractory metal self-aligned gate MESFET fabrication technology 77

5 MEASUREMENT TECHNIQUES AND RESULTS 89 5.1 Introduction 89 5.2 Diode measurements 90 5.3 Transistor Measurements 94

- iii- 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 107

REFERENCES 111

APPENDIX Al mwSPICE listing for transfer curve analysis 115 A2 mwSPICE listing for buffer amplifier transient response 116 A3 mwSPICE listing for dual-gate switch transient analysis 117

-iv- LIST OF TABLES

TABLE DESCRIPTION PAGE

1., 1 Components for monolithic microwave integrated circuits 5

1.. 2 Important properties of silicon and gallium arsenide 6

4,. 1 Detailed self-aligned gate process log 80

5.. 1 Typical self-aligned gate MESFET model parameters 105

-V- LIST OF FIGURES

FIGURE TITLE PAGE

1.1 Sampling amplifier block diagram. 8

2.1 Sample-and-hold waveforms and definitions ( after Stafford 11 et al. [13] ).

2.2 Basic sample-and-hold circuits: (a) simplest, (b) output 13 buffered, (c) input and output buffered, (d) integrator.

2.3 Multistage sample-and-hold circuits: (a) feedback, 16 (b) ground referenced.

2.4 Six-diode sampling switch. 17

2.5 FET sampling switch: (a) n-channel MOSFET, (b) n-channel MESFET. 19

2.6 Silicon monolithic sample-and-hold circuit ( after Stafford 25 et al. [13] ) .

2.7 GaAs monolithic sampling switch ( after Saul [17] ). 26

2.8 GaAs monolithic sample-and-hold circuit ( after Harrold 28 et al. [19] ) .

3.1 Block diagram of the sampling amplifier showing the critical 31 propagation times.

3.2 Input delay line low frequency equivalent circuit. 34

3.3 Input dc loss as a function of the number of channels:

(a) Rin= 1 kn, (b) Rin= 10 kfl 35

3.4 Input delay line high frequency equivalent circuit. 36

3.5 Input ac loss as a function of channel position:

2 _ (a) Rin= 10 kfi, wCin= 10" , (b) Rin= 10 kQ, wCin= 10 * 38 3.6 Simulated return loss and transmission loss of the loaded 39 input delay line.

3.7 Monolithic FET buffer amplifier ( after Hornbuckle et al. [23] ). 42

3.8 Buffer amplifier simplified low frequency small signal 43 equivalent circuit.

3.9 Simulated buffer amplifier frequency response. 45

-vi- FIGURE TITLE PAGE

3.10 Simulated buffer amplifier transient response. 46

3.11 Single-gate MESFET switch: (a) schematic diagram, (b) ON state 48 equivalent circuit, (c) OFF state equivalent circuit.

3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state 51 equivalent circuit, (c) OFF state equivalent circuit.

3.13 Simulated single-gate GaAs MESFET switch transient response. 54

3.14 Simulated dual-gate GaAs MESFET switch transient response. 55

4.1 Device isolation methods: (a) selective ion-implantation, 63 (b) isolation ion-implantation, (c) mesa etching.

4.2 Buried-channel refractory metal self-aligned-gate process 66 ( after Yokoyama et al. [42] ).

4.3 T-structure self-aligned-gate process 68 ( after Levy et al. [43] ).

4.4 Self-Aligned Implantation of N+-layer Technology ( SAINT ) 70 process ( after Yamasaki et al. [45] ).

4.5 Sidewall-assisted pattern inversion process ( after 72 Hagio et al. [46] ).

4.6 Airbridge fabrication process. 76

4.7 UBC refractory metal self-aligned-gate fabrication

process flowchart. 79

4.8 Sample-and-hold mask layout. 86

4.9 Photomicrograph of sample-and-hold chip. 87

4.10 Scanning electron micrograph of dual gate MESFET. 88

5.1 Typical capacitance/voltage doping profile. 92

5.2 Typical diode current/voltage plot. 93

5.3 Symmetric MESFET model equivalent circuit ( after Curtice et al. [50] ). 95 5.4 Small-gate-length MESFET depletion region. 97

5.5 Typical plot of 7lDS versus VGS used to determine threshold

voltage VT and gain parameter K. 99

-vii- FIGURE TITLE PAGE

5.6 Measurement setup used to determine Rs and RD. 101

5.7 Typical end-resistance plot giving Rs. 102

5.8 Typical plot of transconductance gm versus VGS. 104

5.9 Self-aligned gate MESFET transfer curves: ( ) measured, ( • • • ) simulated 105

-viii- ACKNOWLEDGEMENT

Many people helped in direct or indirect ways in the research and preparation of this thesis. In particular, I would like to thank Dr. L.

Young for his encouragement and guidance during all stages of my graduate work. Peter Townsley was largely responsible for the acual device fabrication. I also gratefully acknowledge the contributions of my fellow graduate students, Kim Tan, Dave Hui, Salam Dindo and Wade Tang, as well as

Rod Walker for his proofreading. Finally, I would like to thank my colleagues and management at Harris-Farinon Canada, Ltd., of Dorval, Quebec, for their active support and encouragement.

- ix- CHAPTER 1 INTRODUCTION

1.1 Overview

This thesis describes the design and fabrication of a monolithic, high• speed, sample-and-hold amplifier for use in signal processing applications.

The introduction will discuss the requirements for high-speed monolithic circuits, the application of gallium arsenide and the fundamentals of gallium arsenide monolithic microwave integrated circuits ( GaAs MMICs ), and the concept of distributed sample-and-hold amplification.

Chapter 2 will discuss the theoretical and practical aspects of high speed sample-and-hold circuits and give an overview of published work in the field. In chapter 3 the design of a sample-and-hold amplifier suit• able for use in a distributed amplifier will be described and simulation results using the computer program mwSPICE will be given. In chapter 4 the development of a self-aligned gate GaAs processing technology at the

University of British Columbia will be described. Measurement procedures and experimental results will be given in chapter 5, and finally chapter 6 will present conclusions and suggestions for future work.

1.2 Requirement for high-speed monolithic integrated circuits

In the past there has been an evolution to faster and more complex circuits, with circuits of a given complexity becoming ever faster and circuits of a given speed becoming ever more complex. At the same time

-1- these circuits are becoming both cheaper and physically smaller in size.

These developments are spurred by the requirement for relatively cheap, high volume subsystems in areas such as signal processing, phased array radar and real time graphics. Phased array radar, for example, uses transmit power amplifiers, receive low noise amplifiers, transmit/receive switches and digitally controlled phase shifters, all which must operate at the radar frequency of typically 8 GHz. In presently available systems these functions are implemented using mainly hybrid integrated circuit technology which is bulky and expensive due to the skilled manpower required for assembly and tuning. All these subsystems have been demonstrated using monolithic integrated circuit technology [1,2,3,4], but at present yield seems to be the limiting factor. Once a suitable high yield technology has been developed it is likely that all these functions will be integrated on one chip.

Another high volume application that is being actively investigated is

12 GHz Direct Broadcast Satelite ( DBS ) receivers for the commercial television market. These circuits typically consist of a low noise preamplifier, a local oscillator, a mixer, a bandpass filter and an automatic gain control intermediate frequency amplifier. All these functions have been demonstrated in monolithic form, amd several papers have presented complete receivers on a chip [5,6].

A very important advantage of monolithic microwave circuits over hybrid circuits is that the parasitic reactances associated with component inter• connections can be greatly reduced. This considerably increases the maximum attainable bandwidth which is important for instrumentation and electronic

-2- warfare applications. By incorporating the parasitic capacitances of a number of FETs into a transmision line structure, so-called travelling wave, or distributed, amplifiers can achieve bandwidths of a decade or more up to

20 GHz [7]; this performance is only possible with monolithic circuits.

The small size and minimal parasitics also allow MMICs to be used well into the millimetre-wave ( 30 - 300 GHz ) region [8]. Up to now only wave• guide circuits were usable in this frequency range.

In the digital field there is a large requirement for very high speed logic for such applications as real time signal processing and real time graphics. Other uses for high speed digital ICs are supercomputers and high data-rate telecommunications modems. At present, GaAs-based SSI and MSI circuits are commercially available that operate up to about 4 GHz [9] but their cost is still prohibitively high.

1.3 Elements of monolithic microwave integrated circuits

A monolithic microwave integrated circuit ( MMIC ) can be defined as a circuit used to perform a given function at frequencies greater than about 1

GHz, where the active and usually passive elements are fabricated on a single semiconductor chip. This definition allows for critical passive components, such as resonators, or bulky non-critical components, such as decoupling capacitors, to be off the chip.

Active components, such as metal-semiconductor field effect transistors

( MESFETs ) and Schottky diodes are required to achieve gain, for frequency conversion and other nonlinear functions. Passive devices, such

-3- as capacitors, inductors, resistors and transmission lines are used for bandwidth determination, impedance transformation, biasing and other linear functions. The most important elements, their common uses and, where applicable, their fabrication technologies are listed in table 1.1.

One problem with MMICs that contain many passive elements is that the chip size can become quite large, a cm2 or more is not uncommon. This increases the cost and can decrease yield due to breakage, substrate flaws etc. Another potential disadvantage of MMICs is that present techniques to tune a circuit after fabrication are rudimentary compared with conventional hybrid circuits. Therefore a very careful initial design is required using the best possible component models and a design philosophy based on minimum sensitivity to component and processing varations. Computer-aided analysis and design are absolutely essential for most MMIC designs.

1.4 Semiconductor materials for MMICs

At present both silicon and gallium arsenide are being used for the production of MMICs. Si has the advantages of having lower cost and a well developed and simpler production technology while GaAs has inherently higher speed. The main characteristics of the two are listed in table 1.2. InP also has potential as a suitable semiconductor but has not yet been developed to the extent of Si and GaAS.

The low field electron mobility of GaAs is much higher than that of Si which is the reason for its higher speed potential. However, its hole

-4- COMPONENT FABRICATION TECHNOLOGY APPROXIMATE VALUE RANGE

Capacitors interdigitated < 1 pF

metal-insulator-metal 1 - 100 pF

Inductors loop < 10 nH

shorted high-impedance line < 10 nH

multiturn ( with airbridges ) 10 - 100 nH

Resistors thinfilm sputtered 10 - 10 kO

semiconductor 10 fl - 1 kil

Transmission lines microstrip 20 - 130 O

coplanar waveguide 40 - 200 O

MESFETs and epitaxial

Schottky diodes ion-implanted

Table 1.1. Components for monolithic microwave integrated circuit fabrication.

-5- PROPERTY Si GaAs

Intrinsic resistivity, fi-cm 2.3X105 108

Dielectric constant 11.9 13.1

Electron drift mobility, cm2/V-s 1500 8500

Hole drift mobility, cm2/V-s 450 400

Bandgap, eV 1.12, indirect 1.42, direct

Crystal structure diamond zincblende

Lattice constant, A 5.431 5.653

Density, g/cm3 2.33 5.32

Linear coefficient of

thermal expansion, K"1 2.6X10"6 6.86X10"6

Thermal conductivity, W/K-cm 1.5 0.46

Melting point, °C 1415 1238

All values specified at 300 K.

Table 1.2. Important properties of silicon and gallium arsenide.

-6- mobility is lower than that of Si and hence n-channel FETs are used almost exclusively. GaAs does not have a native oxide with appropriate properties

for use with MOS, and other insulators such as Si3NA and Si02 have thus far given rise to very high interface trap densities, so Schottky barriers rather than MIS structures are used for the FET gates which limits the usable forward gate voltage to about 0.6 V.

The high resistivity of GaAs even after processing is one of the main advantages because it provides inherent isolation between devices and also allows the fabrication of relatively low loss transmission lines on chip. At

2 GHz its dielectric loss is about 0.008 dB per cm compared to 0.4 dB for Si and 0.001 dB for alumina, a common hybrid MIC substrate [10].

The direct bandgap of GaAs allows it to be used to make solid state lasers and since it is transparent to infrared light it is an ideal material for making integrated opto-electronic devices such as monolithic fibre-optic repeaters, although InP may be an even better choice for this application [11].

Although much work remains to be done to develop a suitable fabri• cation technology, it appears that GaAs will be the semiconductor of choice for most MMIC designs.

1.5 The sampling amplifier concept

The work done for this thesis was directed at studying the feasibility of producing a monolithic version of the sampling amplifier developed at the

Defense Research Establishment Ottawa ( DREO ) [12]. A block diagram of the

-7- Figure 1.1 Sampling amplifier block diagram.

-8- sampling amplifier is given in figure 1.1 The input travels along the input delay line (A) and is finally dissipated in the input load resistor (B).

The N input switches (C) are periodically closed to sample the signal along the input line and the sampled voltage is stored on capacitors (D). Signal processing, such as in this case amplification, occurs in the video amplifiers (E), after which the output switches (F) feed the processed signal to the output delay line (G). Half the signal travels in the opposite direction as the input signal and is absorbed by the output load resistor (H), the other half is low pass filtered to remove the switching noise and is available at the output.

The bandwidth of the sampling amplifier is determined mainly by the width of the sampling pulse which should be made as narrow as possible. The bandwidth required of the video amplifiers is slightly greater than half of the input bandwidth divided by the number of channels. The optimum time delay between adjacent switches is determined by the maximum input freqency, the number of channels and the time delay of the switch control signal between adjacent switches, which will be non-zero in practice.

The advantages of the sampling amplifier are that low bandwidth ampli• fiers can be used to amplify wideband signals and that the design is inherently redundant so that the failure of one sub-amplifier will not cause the failure of the complete sampling amplifier.

-9- CHAPTER 2 HIGH SPEED SAMPLING

2.1 Sample-and-hold waveforms and definitions

An ideal sample-and-hold circuit is a circuit that, in the sample mode, tracks the input signal and whose output, on receipt of a hold command, takes on the value of the input signal at the instant the command is received and holds this value until the next command is given [13].

In practice certain signal distortions and time delays occur that will limit the performance of a sample-and-hold circuit. Figure 2.1 shows the input, output and control waveforms with the typically occurring non- idealities. After the hold command is given a finite time is required for the switch to open; this is termed delay time. Pedestal is the term given to the change in output voltage when the sampling switch is opened and Is due to the capacitive divider effect of the hold capacitor and the sampling switch parasitic capacitances. Settling time is the time required for any transients to die down when the switch is opened. In the hold mode, the hold capacitor will slowly charge or discharge, depending on signal polarity. The corresponding change in output voltage is termed droop rate.

When the sample command is given the time required for the switch to close, the hold capacitor to charge to the input level and the output signal to settle down is termed acquisition time.

-10- INPUT

SETTLING OUTPUT - TIME — UJ CO

o > _J PEDESTAL

F.

r DROOP

DELAY TIME ACQUISITION TIME

SAMPLE HOLD SAMPLE

TIME

Figure 2.1 Sample-and-hold waveforms and definitions ( after Stafford et al. [13] ).

-11- 2.2 Sample-and-hold design considerations

For a given application there are two sets of constraints that must be taken into account. The first is determined by the external system require• ments and consists of such factors as bandwidth, input and output impedance, gain, power handling capability and power consumption, linearity and sampling accuracy. On the other hand, the physical circuit implementation determines the circuit complexity and cost and the tradeoffs that will be required in the system requirements.

Specific design goals were not given for the distributed amplifier work done at the University of British Columbia. It was to run as fast as possible, run at a fairly low signal level and be suitable for monolithic integration. Since a large number of switches are connected in parallel along the delay lines the input impedance of each must be high to avoid a significant voltage drop along the line. In order to keep yield as high as possible the circuit complexity should, at least initially, be kept low.

2.3 Basic sample-and-hold circuits

In principle, all sample-and-hold circuits consist of a signal switch and a hold capacitor. Other elements, such as buffer circuits, switch drive circuits and feedback circuits can be added to better meet system requirements. The simplest type of sample-and-hold is simply a switch and capacitor, figure 2.2a. The disadvantages of this circuit are that all the

-12- IN OUT

-13- hold capacitor charging current must be supplied by the sampled source, which means that the acquisition time will be dependent on the source impedance. Conversely, the droop rate will be dependent on the input impedance of subsequent circuitry, and, if this impedance is inductive, there can be significant ringing of the sampled signal, which will increase the settling time.

The sample-and-hold performance can be improved by following the hold capacitor with a buffer amplifier as shown in figure 2.2b. This results in a consistent, high impedance load and thus a low droop rate. The major disadvantage of this circuit is increased'complexity, and the buffer must be properly designed to avoid having it limit speed performance, cause distortion or give a dc offset. The input impedance of this circuit is still not well defined and is time varying, which can cause problems in high frequency systems.

The next logical improvement is to also put a buffer amplifier at the input to isolate it from the source as shown in figure 2.2c. For the case of a number of switches in parallel a high input impedance is necessary as was discussed in section 2.2. The input buffer should also be designed to have a high slew rate to reduce acquisition time. As in the case of the previous circuit, the major disadvantages are increased complexity and the possibility of distortion and dc offset.

Another type of sample-and-hold circuit is shown in figure 2.2d. Here the output buffer amplifier is configured as an integrator, with the hold capacitor in the feedback loop. The main advantage of this circuit is that the switch is essentially always operating at ground potential, thus easing

-14- the drive requirements and allowing a larger input voltage swing. It has limited high frequency use, however, due to the difficulty of obtaining microwave "op-amp" type amplifiers.

In certain applications, such as sampling oscilloscopes, it is required to have very short acquisition times but at relatively low sampling rates.

In such cases the more complex multistage sample-and-hold circuits of the type shown in figure 2.3 are often used. In the circuit of figure 2.3a,

capacitor Cx is initially charged up to a small fraction, typically 5%, of

its steady state value before switch S1 is opened again. Switch S2 charges

the much larger capacitor C2 over a longer period of time and the amplifier gain A and the feedback factor are chosen to charge both capacitors to the

original input value. In the circuit of figure 2.3b, C1 is similarly charged to a fraction of its steady state value and the gain A is chosen to

charge the larger capacitor C2 to the full steady state value. Once this is

achieved S2 opens and S3 is closed to discharge C1 back to ground potential.

2.4 Sampling switches

For the switching element itself there are two popular configurations.

The first is the diode ring shown in figure 2.4. In the OFF state ( switch

open ) , the control voltage Vc must be less than the peak signal voltage Vs

in order to keep diodes D5_6 forward biased and reverse biased.

Conversely, in the ON state Vc must be greater than Vs. The bias voltage Vb is dependent on the bias resistor value and diode series resistance as well as on the maximum input signal swing [12].

-15- (a)

Figure 2.3 Multistage sample-and-hold circuits: (a) feedback, (b) ground referenced.

-16- + CONTROL

+ BIAS

BIAS D5

01 1 03

OUT Vs . IN

02 D4

R BIAS D6

- BIAS

- CONTROL

Figure 2.4 Six-diode sampling switch.

-17- The main advantage of the diode ring switch is that, due to the balanced control drive requirement, the complementary sampling pulses tend to cancel at the input and output ports if well-matched diodes are used. It can also handle large input signal levels if the bias and control voltages and bias resistors are chosen properly, and can have a high OFF/ON impedance ratio.

Its disadvantages are a significant dc power consumption and the requirement for a high speed complementary switch current drive, especially if a large number of switches are to be used in parallel.

The other popular type of switch uses a field effect transistor as a voltage controlled resistor, figure 2.5. For lower speed applications, up to a few tens of MHz, a silicon MOSFET is most useful since its gate cannot be forward biased into conduction as is potentially the case with a JFET or

MESFET. Higher speed applications, however, require the fast switching speed of a GaAS MESFET.

The advantages of a FET switch are that its state is controlled by a single-ended voltage signal, thus easing the drive requirements compared to a diode switch, and the negligible dc power consumption. However, since the switch resistance is dependent on the gate to channel voltage, and the channel voltage is signal level dependent, a limitation is placed on the maximum useful signal level that can be handled. In order to minimize these effects the switch control bias and pulse height must be chosen such that the control gate does not become forward biased into conduction at the lowest signal voltage and that the channel resistance does not become too large at the highest signal level since this would cause the acquisition time to be strongly signal level dependent. In practice this limits the

-18- (a) I

CONTROL

OUT

(b) CONTROL

Figure 2.5 FET sampling switch: (a) n-channel MOSFET, (b) n-channel MESFET.

-19- signal voltage swing to about 1 volt peak-to-peak.

Another major advantage of the FET switch is its simplicity. It is not required to have matched devices and the physical layout is less critical than in the case of the diode switch.

The disadvantage of the FET switch is that the single-ended drive does not give any sample pulse feedthrough cancellation. This feedthrough is essentially caused by the gate-source capacitance forming a capacitive divider with the hold capacitor and is thus dependent on the ratio of the values of these capacitances. It is more or less independent of signal level and will not be an important factor in many applications. The other disadvantage of the MESFET switch is the low allowable input voltage swing as discussed previously.

2.5 Survey of literature on sample-and-hold circuits

To determine the state of the art of sample-and-hold circuits both a computer aided search and a manual search were performed using subject and citation indexes. Surprisingly little has been published in the scientific literature. The most important papers of what has been published will be discussed in four categories: (a) discrete mechanical sampling heads,

(b) discrete solid state sampling circuits, (c) monolithic sampling circuits and (d) theoretical analysis and modeling of high speed sampling circuits.

-20- 2.5.1 Discrete mechanical sampling heads

The highest speed electronic switches are found in this category. The sampling heads are generally used in sampling oscilloscopes and since they have been developed by private laboratories for use in commercially available test equipment little has been published on the actual design procedure. The first recent paper of interest is by Grove [14] of Hewlett-

Packard. In it he discussed the design and modelling of a two diode sampler located in the centre of a dielectric-filled biconical transmission line.

Using a simplified linear ( small signal ) model he obtained an expression for the sampler bandwidth, which is determined by the diode characteristics, the sampling pulse width and the transmission line characteristics for both the signal and the sampling pulse. The design gave a bandwidth of greater than 15 GHz and still forms the basis of present day sampling heads and has not been significantly improved upon.

In a more recent paper Riad [15] gave a more rigorous analysis of the HP-

1430A sampling head, which has a nominal bandwidth of 12.4 GHz and a nominal pulse risetime of 28 ps. The sampling head itself is similar in construction to the one discussed in [14], with a biconical tapered line and two sampling diodes. The input and output impedance matching structures are more - sophisticated, and feedback is used to bias the diodes to the previous sampled level as was discussed in section 2.3. By doing this the sampling network measures only the difference between consecutive samples, thus improving the dynamic range. The sample pulse itself is obtained by

-21- reflecting a fast risetime voltage step off a short circuit wall in the cavity. When the leading edge of the step is reflected off the short circuit it is inverted and, upon reaching the diodes, cancels the incoming wave leaving only a narrow pulse whose width is determined by the round trip distance between the diodes and the short circuit.

After describing the sampler and its operation Riad goes on to develop a model of it which includes the input and output matching networks, the diode layout, construction and bias, and the feedback network.

Mechanical sampling heads using discrete diodes are the fastest electronic samplers currently available, the fastest having bandwidths of about 18 GHz. Their disadvantage is their high cost ( for machining and assembling their components ) and their relatively large size.

2.5.2 Discrete solid state samplers

In contrast to the mechanical samplers discussed in the previous section, solid state samplers do not normally have matching networks for the input signal. Typically, a complete sampler will use input and output buffer amplifiers to isolate the switch from the external circuitry. The input impedance of the amplifiers is usually high while the output impedance is low.

The switch can consist of either a diode bridge or a FET of some sort.

In recent work the FET switch has been preferred because of its ease of fabrication and much simpler drive requirements.

A representative paper describing the state of the art of such discrete

-22- sampling circuits is that by Givens [16]. He uses high slew rate monolithic buffer amplifiers and discrete DMOS FET switches for his circuit, which is primarily intended for analog-to-digital converter systems. As such, speed is not as important as accuracy. His design achieves a bandwidth of about

50 MHz for a 2 V peak-to-peak input, but with high linearity, low droop rate and low pedestal, which he terms hold-step error. The low pedestal is achieved by using a charge compensation circuit to supply the same amount of charge to the hold capacitor as was transferred to the switch.

The rest of the paper describes the tradeoffs involved in sample-and-hold design and some of the techniques used to measure their characteristics.

The advantage of discrete solid state samplers is their low cost and small size compared to mechanical ones. The disadvantage is that the inevitable circuit parasitics will tend to limit the maximum speed to a few

GHz, although circuits of this bandwidth have not yet been reported in the literature.

2.5.3 Monolithic sample-and-hold circuits

For large volume applications, such as the sampling amplifier envisioned in this project, monolithic circuits can be expected to give substantially reduced cost as well as increased uniformity and potentially higher performance. For high speed applications, GaAs is the semiconductor of choice due to its higher electron mobility relative to silicon. Processing technology is much less developed for GaAs, however, and much work needs to be done before the full potential of GaAs sample-and-hold circuits can be

-23- realized.

The earliest paper describing a monolithic sample-and-hold was by

Stafford et al. [13] in 1974. They used silicon technology and a fairly complex integrator/feedback system to obtain the medium speed, medium performance sample-and-hold circuit shown in figure 2.6. Although they do not give the speed performance, their quoted settling time was 1 jus, giving a maximum sampling rate of about 250 kHz.

The first paper describing a monolithic sample-and-hold switch is by Saul

[17] in 1980. He used a quad ring of MESFETs as a switch, but used an external hold capacitor and no buffer amplifiers, figure 2.7. Using MESFETs with a 4 fj.m gate length and a 13 pF hold capacitor Saul was able to obtain a maximum sampling rate of 150 MHz. The major limiting factor was the parasitic inductance associated with the external capacitor. It is therefore reasonable to expect that, using a submicron gate length switch and a 1 or 2 pF monolithic hold capacitor, a sampling rate of at least an order of magnitude higher can be obtained.

In his switch design Saul uses a quad ring of MESFETs, presumably based on the standard diode ring. However, since the MESFETs are not comple• mentary, the main reason for using a ring ( which is to reduce sample pulse feedthrough by using a balanced drive ) is lost. What remains is a complex structure having the same characteristics as a single MESFET of the same geometry.

A more recent paper describing a GaAs monolithic sample-and-hold circuit was published by Barta et al. in 1983 [18]. They use a triple-gate MESFET switch with an on-chip metal-insulator-metal ( MIM ) capacitor followed by a

-24- SUB HOLD

- IN SWITCH

+ IN OUT

CLAMPS CHARGE CANCEL ft DEVICE

A V

SWITCHING CONTROL CIRCUIT

Figure 2.6 Silicon monolithic sample-and-hold circuit ( after Stafford et al. [13] ).

-25- + BIAS

OUT

CONTROL

- BIAS

Figure 2.7 GaAs monolithic sampling switch ( after Saul [17] ).

-26- feedback buffer amplifier to minimize loading effects on the performance of the sampler itself. The use of a triple-gate switch, with the sample pulses applied to the centre gate and the outer gates grounded, was found to significantly reduce sample pulse feedthrough to the input and output. They reported an overall 3dB bandwidth of 1.1 GHz with a maximum sampling rate of

500 MHz.

A more complex switch has been reported by Harrold et al. [19] for use in a switched capacitor bandpass filter IC. Their circuit, shown in figure

2.8, uses drive circuitry which allows the gate of the switching FET to track the input signal, thus alleviating the input voltage swing limitation.

They reported a maximum switching speed of about 1 GHz.

2.5.4 Theoretical analysis and modeling of high speed sample-and-hold

circuits

A number of papers already discussed in this section contain an analysis or model of the sampling process. Grove [14] gives a simplified linear analysis of samplers in general. Riad [15] gives a thorough model of the

HP-1430A sampling head which inludes a nonlinear model for the switching diodes. His main objective was to obtain the sampling head step response.

Other papers have dealt more with the theoretical aspects of sampling.

Blum [20] investigates the effects of aperture time using Fourier analysis.

Wollman [21] does a simplified analysis of the effects of nonlinear switch resistance, showing that this will give rise to intermodulation distortion.

Finally, Sonders [22] defines the parameters involved in the dynamic

-27- + BIAS

IN

HOLD OUT

- BIAS

CONTROL

Figure 2.8 GaAs monolithic sample-and-hold circuit ( after Harrold et al. [19] ).

-28- performance of high speed sample-and-hold circuits and gives a transformer bridge technique for the measurement of those parameters.

In conclusion, the literature published to date provides some idea of the the promise of GaAs high speed sampling circuits, although this promise has not yet been realized. The work being done at the University was designed to continue the development of high-speed monolithic sample-and-hold circuits, both in terms of processing and circuit complexity and in terms of speed.

-29- CHAPTER 3 DESIGN AND SIMULATION

3.1 System requirements

In order to specify the performance requirements of the sampling amplifier subsystems, the system requirements of the sampling amplifier itself must first be defined. A detailed block diagram of the sampling amplifier is shown in figure 3.1. The analysis will be divided into three sections: the overall system, the input network and the output network.

The external parameters of interest for the overall system are bandwidth, gain,input impedance and output impedance. Secondary characteristics are power handling capabilities, noise and distortion characteristics. These parameters are determined by several factors such as sampling rate S and sample pulse width W, spacing between adjacent switches, input and output impedances of the switches and gain and bandwidth of the video amplifiers.

Typically, in designing such a system one would first determine the

primary parameters: bandwidth B, gain A and system impedance Z0. The maximum allowable sampling pulse width is determined by the bandwidth requirement,

Wmax. * V2B (3.1)

The sampling rate and the number of channels N required for complete reconstruction of the sampled signal are related by

-30- Figure 3.1 Block diagram of the sampling amplifier showing the critical propagation times.

-31- N = B/S (3.2)

The time delay between adjacent channels Ts is also dependant on the bandwidth. It is given by

Ts = 1/2B (3.3)

In practical systems there will also be a delay in the sampling pulse

between adjacent channels Tp which results in an effective signal delay of

Tse =TS ± Tp (3.4)

depending on whether the sampling pulse is travelling in the same direction

(-) as or opposite to (+) the input signal. Thus, the bandwidth is given by

B = V2Tse (3.5)

The video amplifier bandwidth requirement is

Bvideo > S/2 (3.6)

It would appear that, for a given input signal bandwidth, one could decrease the video bandwidth requirement by increasing the number of channels and decreasing the sampling rate. In practice the number of channels is limited by the loading of the input and output networks on their

-32- respective delay lines. This loading consists of three components, a dc loading due to the resistive component of the input and output impedances, an ac loading which includes the input and output reactances and a periodic loading due to the distributed nature of the input and output lines. In the following discussion the loading effects on the input line will be analyzed; similar effects also hold for the output line.

The low frequency equivalent circuit of the input line is shown in

figure 3.2, where Rin is the input resistance of the sampling circuit, and

Req = Rin/N (3.7)

The loss for this circuit is given by

Lindc = 201og( 1 + Z0N/2Rin ) dB (3.8)

This is plotted in figure 3.3 as a function of N for Z0 = 50 0 and

Rin = 1 kO and 10 kQ.

The ac loading effect is similar to the dc situation, but now both the travelling wave nature of the input signal and the input capacitance must be taken into account. The equivalent circuit for the ac case is shown in figure 3.4. In this case the voltage of the input signal decreases ( i.e. the loss increases ) as the signal travels along the transmission line.

Assuming that the transmission line itself has negligible loss the loss at the Nth sampling circuit is given by

-33- RIN Who •AA/vV 1 (l)

-A/VW 1 (2)

1 (3)

(4)

(N-1)

1 (N)

Figure 3.2 Input delay line low frequency equivalent circuit.

-34- 20 10 20 50 100 200 500 1000

NUMBER OF CHANNELS

Figure 3.3 Input dc loss as a function of the number of channels:

(a) Rin= 1 kfl, (b) Rln- 10 kfl.

-35- R IN u 0 HVWVi -WW- I 1 (i) 'IN

rAWn (2) -K-

rAAAAn (3) -K-

T

rAA/vVi 1 (N)

Figure 3.4 Input delay line high frequency equivalent circuit.

-36- Lin..e

where Yin = 1/Rin + jwCin. This is plotted in figure 3.5 for Rin = 10 kQ and uC = IO-4.

The third form of loading is due to the periodic nature of the sampling circuit. Internal reflections caused by the discontinuities of the sampling circuits can interfere destructively to give nulls in the transfer charac• teristics. This will be most severe when the electrical length between adjacent channels approaches 90°. The effect of periodic loading on the transfer characteristics may not be as noticeable for submultiples of 90° but will still appear in the input and output return loss, defined as

Return Loss = 201og| Si± | dB (3.10)

where Sli is the input (i=l) or output (i=2) reflection coefficient.

Periodic loading was simulated using the microwave analysis program

Touchstone. A chain of 20 sampling circuits connected by lossless 50 O transmission line segments was assumed; the sampling circuits were modelled as a parallel combination of a 10 kfi resistor and a 1 pF capacitor, and the transmission line segments were chosen to have an electrical length of 45° at 2 GHz. The calculated input return loss and transmission loss are shown in figure 3.6, the periodic ripple in the return loss and the null in the transmission at 4 GHz can be clearly seen.

In order to minimize loading effects it is clear that the input impedance of the input sampling circuits and the output impedance of the output

-37- Figure 3.5 Input ac loss as a function of channel position.

(a) Rin= 10 kfl, o>Cin= 10-2, (b) Rin= 10 kfl.W Cin=10-*

-38- DB[S11] . DB[S2i] LINE LINE 0.0000

1 /S11 LOSS, / Return loss dB \

15.00 \ A A A A \ Transinissio n loss

0.0000 3.000 FREQ-GHZ 6.000

Figure 3.6 Simulated return loss and transmission loss of the loaded input delay line.

-39- sampling circuits must be maximized, and that the signal transmission delay

Ts must be kept less than 90° at the maximum input freqency.

The situation at the output is similar to that discussed for the input.

It is, however, much more difficult to implement wideband, high output impedance amplifiers than high input impedance amplifiers. The situation is less critical at the output than at the input since it is not necessary to feed a large number of channels from one source. The loss mechanisms are similar for the input and the output, but to some extent the effects will cancel since the channel that has the highest loss at the input will have the lowest loss at the output and vice versa.

If the sampling pulse width is less than the total time required for the sampling pulse to travel to the adjacent channel, the adjacent switch to open and the output signal to travel back to the first switch, then the output signal will see the other switches only in their high impedance

state. Since this is precisely the condition specified in equations 3.1 and

3.5, no output buffer amplifiers are required.

3.2 Buffer amplifiers

Buffer amplifiers at the sample-and-hold inputs have two functions.

They can be designed to have a high input impedance to reduce the loading problems discussed in the previous section, and they can be designed to have a low output impedance to decrease the time required to charge the hold capacitor. In addition, they will also isolate the signal line from the sample pulse line.

-40- The buffer amplifier configuration of figure 3.7 was chosen because of

its high input impedance and because the feedback of Q2 eases the production uniformity requirements. Amplifiers of this type have been described in

[23] and have shown gains of 10 dB with a 5 GHz bandwidth.

A simplified low frequency small signal equivalent circuit of the buffer amplifier is shown in figure 3.8. The FETs are assumed to be ideal and have

identical transconductance gsa, zero bias current I0 and gate capacitance C0

per unit gate width, and WA and IL are the gate width and total current of

Qi. At low frequencies, 13 = ^ + I2 or

W3I0 - Wx( I0 + gmVin ) + W2( I0 + ^ ) (3.11)

Rearranged, this gives

V0ut = (( W3 - W2 - Wx )/W2 }I0/gm - ( Wx/W2 )Vin (3.12)

If Wx+W2 = W3 there will be no dc offset and the amplifier will have a gain of -Wj/Wg independant of transistor transconductance.

The maximum output current is determined by Q4 and Q5; if these are chosen to have equal width the amplifier will have a symmetrical current

drive capability of W4I0. W4 cannot be increased indefinitely, however, because the corresponding increase in gate capacitance will limit the high frequency response.

The diodes are required to keep the gate of Q4 reverse biased when the output voltage is negative. Since the transistors are assumed to be

-41- VDD

Q3 W=100 jjm r-1 Q4 I W=100jJm

SZ 02

Q2 Ql "—i W=49 jJ IN OUT W=51JJm h

Q5 W=100 jJm

V ss

Figure 3.7 Monolithic FET buffer amplifier ( after Hornbuckle et al. [23] ).

-42- OUT

Figure 3.8 Buffer amplifier simplified low frequency small signal equivalent circuit.

-43- identical, the voltage at the gate of Q4 must be equal to VDD/2. The number

and area of the diodes are chosen such that the voltage at the source of Q4

is not greater than about 0.5V referred to the gate at the minimum output voltage. This gives

M( Vd + W4I0RS ) + | Voutjmin | * VDD/2 (3.13)

where M is the number of diodes, Vd is the diode voltage drop and Rs is the

diode series resistance.

To obtain a more exact idea of the transient and high frequency response

characteristics of such a buffer amplifier the computer program Microwave-

SPICE was used to simulate the amplifier. The FET and diode model parameters are derived in chapter 5, and the SPICE program listings are

given in appendix A. Two analyses were performed, one to determine the

amplifier frequency response and one to determine the transient response

when driving a capacitive load. The frequency response curve for a lightly

loaded GaAs FET amplifier ( Rload = 1 kfl ) is shown in figure 3.9. At low

frequencies the amplifier has a loss of about 0.1 dB, at higher frequencies

there is about 3 dB peaking; this is caused by the effective decrease in

negative feedback due to the phase shift in Q4 and the diodes. The 3 dB

bandwidth of the amplifier is almost 10 GHz.

The simulated transient response is shown together with the input signal

in figure 3.10; the load in this case is a 1 pF capacitor. It can be seen

that the amplifier is inverting with roughly unity gain; the difference

between the positive and negative gain is caused by the extra resistance

-44- -45- VOUT VIN HEAL REAL

0.0000 5.0E-09 TIME l.OE-OB

Figure 3.10 Simulated buffer amplifier transient response.

-46- of the diodes in the sourcing half cycle (positive output voltage). The ringing and overshoot are due to the limited bandwidth of the amplifier. The same amplifier with the load increased to 10 pF, and all the input times also increased ten times, showed almost no ringing.

3.3 The sampling switch

The advantages of a FET switch over a diode switch were given in section

2.4. In this section the switching characteristics of single and dual gate

FET switches will be discussed.

The single gate switch is shown schematically, with its equivalent circuit, in figure 3.11. For a symmetrically designed FET the source and drain terminals are interchangeable; the terms "source" and "drain" are used for reference only, with the switch input considered to be the source. For the small signal levels used here the FET will always be operating in the linear regime so that the use of a resistance to model the source-drain conduction mechanism is appropriate.

The most important switch characteristic in the ON state is the switch resistance, which should be minimized to minimize aquisition time.

Referring to figure 3.11, it can be seen that the switch ON resistance is given by

Ron = Rs + Rch + RD (3-14)

For self-aligned gate FETs, Rs and RD consist of the ohmic contact resistance, the resistance of the n+ layer between the ohmic contact and the

-47- Figure 3.11 Single-gate MESFET switch: (a) schematic diagram, (b) ON state equivalent circuit, (c) OFF state equivalent circuit.

-48- channel, and a short section of channel that is not modulated by the gate.

The channel resistance is dependant on the gate-to-channel voltage, where for small drain and source voltages the channel voltage will be the average of the drain and source voltages. For a uniform doping profile and assuming

that Vs and VD are small and VG=0, the channel resistance can be approximated by [24]

1

Rch - (L/W) { 1 - 7( Vbi/Vp ) }-i (3.15)

qND/ia

where Vbi is the built-in voltage of the Schottky barrier, Vp is the pinch- off voltage of the FET, given by

2 Vp = qNDa /2e (3.16)

and a is the channel thickness. In order to reduce Rch one can change the

geometry of the FET, increase the doping concentration or increase the channel thickness. The latter two also increase the pinch-off voltage which, aside from lowering the channel resistance, also makes the resistance

less sensitive to variations in channel voltage.

In the OFF state the most important characteristic of the switch is the

value of the gate capacitances CGS and CGD, which must be minimized.

Assuming again that Vs and VD are small, the two capacitances will be

approximately equal and will be given by

CGS * CGD « «WL/2a (3.17)

-49- Equation 3.17 also assumes that Vp » Vbi- kT/q and that, in the OFF state,

the gate voltage VG equals the threshold voltage Vt.

This depletion capacitance model assumes a one-dimensional electric field distribution under the gate. In reality, with the short gate lengths used here, there will be an additional fringing capacitance to the sides of the depletion region which can be quite significant. This will be especially important with self-aligned gate devices due to the proximity of the n+- regions to the gate. Since this lateral depletion width cannot vary much with gate bias due to the high doping levels of the n+-region, the total gate capacitance will be larger than calculated by equation 3.17 and be less sensitive to gate bias than one would expect using the standard one- dimensional depletion capacitance formulas.

It is the gate capacitance that produces a sample-and-hold pedestal by forming a capacitance divider with the hold capacitor; it can be reduced by decreasing the width or, to a lesser extent, the length of the gate or by increasing the channel thickness.

The use of additional gates to isolate the control signal from the input and output lines was first proposed by Barta et al. [18]. They used a triple gate FET with the control signal applied to the centre gate and the two outside gates grounded to give isolation to both the input and the output.

In the present case a buffer amplifier is assumed to provide isolation to the input line so that a dual gate FET can be used. The configuration of a dual gate FET used as a switch is shown in figure 3.12. The switch ON resistance is given in this case by

-50- IN OUT

CONTROL (a)

CONTROL IN I i—OUT

DEPLETION ol ° DEPLETION o

° REGION o k o REGION FL R R CH GG CH -vwv- WW S.I. GaAs

(b)

CONTROL

IN OUT

S.I. GaAs (c) Figure 3.12 Dual-gate MESFET switch: (a) schematic diagram, (b) ON state equivalent circuit, (c) OFF state equivalent circuit.

-51- Ron - RS + 2Rch + RD + ^GG (3.18)

where RQQ is the unmodulated resistance between the gates. Assuming equal spacings between the source and drain and the gates, RQQ will be less than

RS and RD because it does not include a contact resistance component.

In the OFF state the source and drain capacitances of the first FET will be the same as for a single gate FET. The second FET will also have capacitances associated with it which will be larger than the OFF capaci• tances of the first FET since the gate voltage is less, and will be essentially constant assuming again that the source and drain voltages remain essentially at ground potential.

If a single and dual gate switch of the same gate geometries are compared one sees that the ON resistance of the dual gate switch is about double that of the single gate switch. The pedestal is reduced slightly for the dual gate switch since the total hold capacitance now includes the gate capacitances of the second FET, while the OFF capacitance of the first FET remains the same as for the single gate case. In practical applications this effect is negligible since the hold capacitor is usually chosen to be much larger than the gate capacitances. The extra channel resistance of the second FET does help smooth the effects of pedestal but does not significantly reduce them, while significantly increasing hold capacitor charging time.

The single and dual gate FET switches were simululated using the quadratic GaAs MESFET model on Microwave SPICE, the input listings are given in appendix A. For comparison purposes the single and dual gate FETs were

-52- both taken to have the same gate width of lOO/^m; the hold capacitor was chosen to be 1 pF in both cases. The sample pulse width was taken to be 100 ps with a repetition rate of 100 MHz. The transient response of the single gate switch is shown in figure 3.13 and of the dual gate switch in figure

3.14. It can be seen that the pedestal shows up as a slight negative offset

in the sampled signal which is nearly independant of signal level, and which is very similar in magnitude in both cases. The number of cycles required to reach a steady state hold voltage is greater for the dual gate switch.

The dual gate switch also has a high droop rate for large negative signals which is due to conduction of the gate diode of the second FET.

In both cases the aquisition time for positive signals is greater than

for negative signals due to the variation of RDS with gate voltage. To minimize this effect, the switch FET pinchoff voltage should be made as large as is compatible with other external and internal circuit parameters. 1.000

volts

0.0000

-1.000

0.0000 B.0E-08 TIME 2.0E-07

Figure 3.13 Simulated single-gate GaAs MESFET switch transient response.

-54- 1.000

volts

0.0000

-1.000

0.0000 B.0E-0B TIME, S 2.0E-07

Figure 3.14 Simulated dual-gate GaAs MESFET switch transient response.

-55- CHAPTER 4 PROCESSING TECHNOLOGY FOR GaAs MESFETS and MMICs

4.1 Introduction

An important aspect of MMIC fabrication is the choice of a suitable fabrication technology. In a general MMIC technology the following steps are used:

-active layer formation

-device isolation

-gate formation and first level metalization

-ohmic contact formation

-passive component formation

-passivation and protection

-backside via hole processing.

The order may vary depending on the particular technology being used and some circuits may require additional steps while others may omit some. For each step there are several possible technologies available; the choice will depend on the final use of the MMIC, the equipment available and cost considerations. The different processing steps will be discussed in the following sections.

The expected reduction in cost is one of the main reasons behind the large amount of industrial research into GaAs MMICs, and the choice of technology directly effects the cost in several ways. The capital cost of the equipment, the throughput and the achievable level of automation directly determine the cost per wafer, and the uniformity of the process

-56- across the wafer, and from wafer to wafer, will in part determine the yield, a higher yield of course giving a lower cost per chip.

To some extent the final use of the MMIC will also determine the

processing technology. For example, if a circuit is to be used in a low

signal level environment it should be optimized for noise performance. Low

noise FETs typically are biased fairly close to pinch-off and have a

relatively thin, lightly doped channel [25] . In addition, gate parasitic

resistance must be minimized while parasitic source and drain resistances

are not as important since the channel is almost pinched off. Thus,

important characteristics of a low noise technology are its ability to

uniformly and reproducibly produce a thin, lightly doped channel and to

achieve a low gate resistance.

On the other hand, power amplifiers require a relatively thick, highly

doped channel to give a large pinch-off voltage, allowing a large input

voltage swing, and to allow a high current density in the channel. Gate

resistance is no longer critical but the source and drain resistances should

be minimized to reduce power dissipation and thus improve efficiency and

reliability.

The most critical component in an MMIC is the MESFET. This is because it

involves the most processing steps and because the gate length is usually

the smallest, and thus most difficult to reproduce, dimension on the chip.

Section 4.2 gives a review of GaAS MESFET and MMIC fabrication technologies,

while section 4.3 describes in detail the self-aligned gate technology

developed at the University of British Columbia for this project.

-57- 4.2 Review of GaAs MESFET fabrication technologies

The starting point for all GaAs MESFET fabrication technologies is high

resistivity semi-insulating ( S.I. ) GaAs. The earliest commercially

available GaAs was grown along the <111> axis using the horizontal Bridgman

( HB ) technique, but HB wafers are irregularly shaped which reduces yield

and inhibits automated production. The more recent liquid encapsulated

Czochralski ( LEC ) technique allows circular wafers to be grown along the

<100> axis. HB and early LEC wafers required chromium in the gallium

arsenide to give the high resistivity characteristics. Chromium pins the

bulk Fermi level approximately midway between the conduction and valence

bands, thus giving the high resistivity characteristics [26]. Recently,

improvements in crystal growth technology have allowed undoped LEC GaAs to

be made which exhibits high resistivity without the addition of Cr. It is

thought that in this case the Fermi level is pinned between the conduction

and valence bands by a trapping level due to a crystal defect in which As

As atoms are located on Ga sites in the crystal lattice, the Ga antisite

defect [26].

Regular LEC-grown wafers show a fairly high number of dislocations,

typically 104 - 105 cm"2. Recently, so-called dislocation free wafers have

been produced by doping the GaAs with about 1% In which can reduce the

dislocation density to less than 10 cm"2. This apparently increases the

fragility of the wafers, however, thus potentially reducing yield, and it is

not yet clear to what extent dislocations affect device performance.

-58- 4.2.1 Active layer formation

Once a wafer type has been selected, MESFETs and MMICs can be fabricated.

The first step, which is common to all processes, is the formation of an n- doped channel layer on the S.I. GaAs substrate. The most common n-type dopant is Si, although Se, S and Te are also used. The two methods used to form the n-layer are epitaxy and ion-implantation.

In the case of epitaxy, crystalline GaAs of the desired doping level is grown on the starting wafer. Usually a buffer layer of high purity GaAs is deposited first, this is especially important in the case of Cr-doped substrates since Cr has the tendency to migrate into the channel, thus changing the device characteristics over time. Once the buffer layer is grown, the active layer is deposited to the desired thickness.

There are three types of epitaxy that are normally used: liquid phase

( LPE ), vapour phase ( VPE ) and molecular beam ( MBE ). In LPE, the starting wafer is placed in a hot solution containing Ga, As and the dopant.

The solution is then cooled and the doped GaAs crystalizes out on to the wafer [27]. In VPE, gases containing compounds of Ga and As are passed over the heated wafer where they react and deposit on to the wafer. In metal- organic chemical vapour deposition ( MOCVD ), organic compounds of Ga and As are used which allow lower temperature formation of the epitaxial layer

[28]. In MBE, which is the latest technology, elemental Ga, As and donor ions are deposited on the wafer directly in a high vacuum environment. Very thin layers, in the order of a few atomic layers, can be deposited, and each layer can be doped individually, allowing such devices as Modulation Doped

-59- FETs ( MODFETs ) to be fabricated [29].

In ion-implanted formation of the active layer, ions of the dopant species are accelerated in vacuum and implanted into the GaAs substrate.

The doping profile that results may be calculated using a model due to

Lindhard, Scharff and Schiott [30] based on the assumption that the target material is amorphous. When crystalline materials, such as GaAs, are used the wafer is tilted and rotated to present a "random equivalent" profile to the ion beam [31]. The doping profile that is obtained roughly fits a truncated gaussian curve, and with typical accelerating voltages of 50 to

200 kV the doping peak occurs at between 200 and 1500 A for Si into GaAs.

If the random equivalent condition is not met the implanted ions can channel through the crystal lattice resulting in a deeper implant which tends to be quite nonuniform. This would produce a large variation of threshold voltage of the MESFETs.

In addition to the depth profile obtained with ion-implantation there occurs a certain amount of lateral movement known as straggle. In the case of selective implantation ( see section 4.2.3 ) this will result in a non- abrupt transition between the implanted and non-implanted regions.

Although the doping profile for a single implant is roughly gaussian in shape it is, in theory, possible to approximate many useful doping profiles by using multiple implants of different doses and energies. One can also use photoresist or other suitable materials to block the implant from certain areas of the wafer. It is thus, for example, possible to fabricate both low noise and high power FETs on the same chip by using two implant masks.

-60- When the GaAs is implanted the crystal lattice is severely damaged. In order to repair the damage and also to activate the implant by allowing the implanted ions to locate themselves on Ga sites, the wafer must be heat treated, or annealed. Presently the most common method to do this is to heat the implanted wafer in a furnace to about 800 to 850 °C for approximately 20 minutes.

A major problem with heat treating GaAs is that the As starts to vaporize at temperatures above about 500 °C. This outgassing changes the stoichiometry of the crystal near the surface and can severely degrade active layer performance. In order to avoid this problem several solutions can be used. The simplest is to encapsulate the wafer with a temperature-

stable dielectric to contain the As during annealing; both Si3N4 and Si02 are commonly used. However, since the thermal coefficients of expansion of these materials are not matched to that of GaAs, stresses occur during annealing which reduce the overall activation and which also result in differences in performance for otherwise identical FETs aligned along different crystalographic axes [32].

In the past years several capless furnace anneal systems have been developed that use an overpressure of As gas near the wafer to prevent outgassing. The As gas is usually obtained by placing powdered InAs, which gives a higher partial pressure than GaAs, in a special boat which also contains the wafer [33].

Another method of capless annealing uses two GaAs wafers in face-to-face contact [34]. In theory no other As sources are required but significant outgassing can still occur near the edges of the wafers, thus reducing

-61- yield. Use of proximate contact annealing in conjunction with As over• pressure has also been reported [35].

Another recent development that has seen much interest in the last few years is the so-called rapid thermal anneal system [36,37,38]. Here the wafer is rapidly heated using infrared light, such as that produced by high- intensity tungsten lamps, to temperatures slightly higher than those used for furnace anneals but for durations of a few seconds rather than the 20 minutes or so normally used with furnace anneals. In principle this rapid annealing should allow capless anneals to be performed without As over• pressure because the short times involved do not allow significant out- diffusion. By the same token chemical reactions with other materials is minimized, as is the redistribution of the implanted ions due to diffusion.

4.2.2 Device isolation

In addition to the active layer formation by one of the methods described in the previous section an isolation step must be used so that those parts of the chip that are not required to be electrically active become, or remain, semi-insulating. This is required both to eliminate interactions between transistors and to build high quality passive components. There are three ways to achieve isolation: selective ion-implantation into S.I. GaAs, isolation implantation and mesa etching, see figure 4.1.

With selective implantation an implant mask is used to protect those areas of the wafer that are to remain semi-insulating from the ion beam during implant. After the implant the mask is stripped off leaving the

-62- DOPANT IONS \ \ \ \ \ \ \

ii IIJI IIJI II.II nj i I*J

(a)

ISOLATION IONS

^ ^ ^ ^ ^ ^ ^

ITTt.ll is.»i n.ir • • «i.r* n.iirj7 v %•%•••« \X* X * X v * x * y X * X \ > x x x J VxXKXXX 1

(b)

1 i II.II *.*••* i^»y<|^n,» *»W V'J Y«« •< *• • V ** • V *• * V s • V *• • *•* •* • V •* V \* ••_•* • •

(0

_ X X X X x* x x XXX x" * X"x» n-DOPED S.I. GaAs PHOTORESIST 6a As GaAS

Figure 4.1 Device isolation methods: (a) selective ion-implantation, (b) isolation ion-implantation, (c) mesa etching.

-63- desired pattern [39].

An isolation implant must be performed after the wafer has been annealed.

An implant mask is again used but in this case it covers the desired active regions. A high dose, high energy implant is then performed to damage the crystal lattice elsewhere, thus providing the semi-insulating property [40].

Typical isolation implant species are protons, boron and oxygen. Isolation implants can be used with both selective and channel implants but are not normally used with epitaxial wafers because of the high accelerating voltages required to penetrate the few microns of the epitaxial layer.

In the case of a mesa etch the active layer is etched away from that part of the chip that is to become semi-insulating. Special etchants are used to obtain sloping sidewalls which allow continuous metalization between the mesa and the etched sections [41].

The advantage of selective implantation and isolation implantation is that they are completely planar which simplifies interconnect metalization.

Selective implantation is the simpler of the two but there is some evidence that an isolation implant gives better isolation and reduces backgating

[40], which is the interaction of the gate of one transistor on the IDS characteristics of other nearby devices. Backgating is not so much of a problem for MMICs as it is for digital ICs with their much higher packing density. The advantage of mesa etching is that it can be used with epitaxial wafers and that it provides very good isolation.

-64- 4.2.3 Gate formation

The active layer formation steps are common to all FET processes. The next steps can occur in two different orders, depending on the type of technology being used. In the epitaxial processes, ohmic contacts are formed first and the gate deposited later. In the so-called self-aligned processes, which all use ion-implantation for the active layer formation, the gate, or sometimes dummy gate, is deposited first and acts as an implant mask for a second, high dose, implant which is used to reduce the source and drain parasitic resistances. Since the emphasis for the present work has been on self-aligned gate technologies, gate formation for both types of processes will be discussed first.

In principle, it should be possible to use a high temperature stable gate material as an implant mask for the n+-implant. The gate must be able to withstand the high temperatures of the annealing cycle without significant degradation or interaction with the GaAs channel. If an implant energy of about 100 keV is used for the n+-implant, the gate will be in very close proximity to the n+ regions. This will result in a very low breakdown voltage as well as a very high gate fringing capacitance. Yokoyama et al.

[42] proposed using a high-energy n+ implant to move the doping peak deeper into the substrate and thus further away from the gate; a flow chart of their process is shown in figure 4.2. Although this does improve the capacitance and breakdown characteristics it also increases the series resistance because the doping near the surface is low. The lateral straggle

-65- \ \ \ \ \ \ CHANNEL IMPLANT SEMI-INSULATING GaAs

ANNEAL

PHOTORESIST UWIIWIIlJUl REFRACTORY 6ATE METAL DEPOSITION

• M.11 ii.ii

* ••••• • • 4»r«

GATE DEFINITION ETCH n-DOPED 6aAs ttlHtt n+ OHMIC IMPLANT M GATE METALIZATION ANNEAL

v ++ +++

n* -DOPED im. OHMIC CONTACT 68A8 P59 DEPOSITION ++ Mi ALLOYING

OHMIC CONTACT METALIZATION

Figure 4.2 Buried-channel refractory metal self-aligned-gate process ( after Yokoyama et al. [42] ).

-66- is also increased which limits how short the gate can be made before the

source and drain n+ regions short out the channel.

Levy et al. [43] found a simple solution to this problem; a flowchart of

their process is shown in figure 4.3. After the channel implant has been

done the whole wafer is covered with gate metal. A second layer of material

is deposited on top of this and patterned with the gate mask. The bottom

( gate ) metal is then etched away using a plasma technique, the top metal having been chosen to have a slow reaction rate with the plasma species used

to etch the gate metal. The wafer is over-etched to slightly undercut the

masking layer. When the wafer is now implanted again for the ohmic contacts

this undercut provides the necessary separation between the n+-regions and

the gate. After implantation the top metal is removed, usually using wet

etching techniques, and the wafer is annealed.

Levy used TiW, which is rapidly etched by fluorine-based plasmas, as the

gate metal and Al or Ni as the implant mask. This is because pure W has

poor adhesion to GaAs, and subsequent workers have also used WSi^ [44],

amongst others. The presence of Ti, while greatly improving adhesion, is

thought by some to degrade device performance by reacting with the GaAs

during annealing. The refractory metal silicides do not suffer from this

problem, but both adhesion and Schottky gate characterisics are very

dependent on chemical composition, and they also have a slightly higher

resistivity than the metallic compounds.

The choice of masking layer depends on the required stopping power and

the desired ease of production, potential materials being, amongst

others, Al, Ni, Cr and photoresist. Photoresist is the easiest to use

-67- V Y V Y V V V

CHANNEL IMPLANT SEMI-INSULATING GaAs

ANNEAL

PHOTORESIST

REFRACTORY BATE METAL DEPOSITION

GATE IMPLANT MASK GATE IMPLANT DEFINITION MASK

GATE DEFINITION ETCH (WITH UNDERCUT)

¥ V Y Y V Y V n-DOPED + n OHMIC IMPLANT GaAs

STRIP GATE IMPLANT MASK

T.W GATE ANNEAL METALIZATION

+ + *+ + + + +++.

|T -DOPED y s\ w GaAs + + OHMIC CONTACT l + J DEPOSITION

ALLOYING OHMIC CONTACT METALIZATION

Figure 4.3 T-structure self-aligned-gate process ( after Levy et al. [43] ).

-68- but, being the least dense, has the lowest implant stopping power. Ni and Cr have much higher stopping powers but are more difficult to deposit and remove. Al is easily evaporated and is easily etched in hydrochloric acid, and has acceptable stopping powers for most applications.

A completely different approach to self-aligned gate MESFET fabrication was taken by Yamasaki et al. [45]. Their technology, called the Self-Aligned Implantation of N+-Layer Technology ( SAINT ), is shown in figure 4.4. After selective implantation of the channel n region, the

wafer is covered with a multilayer resist consisting of PECVD Si3N4

(1500 A), bottom photoresist (8000 A), sputtered Si02 (3000 A) and top photoresist. The top photoresist is patterned for the n+ regions and is

used as a mask for the fluorine-based reactive ion etch of the Si02, after which the bottom photoresist is over-etched using an oxygen-based reactive

ion etch to obtain an undercut profile. The remaining photoresist and Si02 are used as the n+ inplant, after which the wafer is covered with RF

magnetron-sputtered Si02. The Si02 sidewalls are thin compared to the thickness of the flat areas and are easily etched away using buffered HF, followed by the removal of the remaining photoresist. After annealing,

ohmic windows are etched through the Si02 and Si3N4 and ohmic contacts are

deposited and alloyed. The last step is to etch the Si3NA under the gate

using the Si02 as an etchmask, and pattern and deposit the gate metal. The gate length is determined by the length of the bottom photoresist after the undercut etch, while the separation between the gate and the n+ regions is determined by the amount of undercut.

Another type of self-aligned technology was reported by Hagio et al.

-69- V V 11 SEMI-INSULATING CHANNEL IMPLANT GaAs

DEPOSIT SILICON NITRIDE

DEPOSIT BOTTOM PHOTORESIST PHOTORESIST

—IT !«-•• IIJIIIJIIIJI HillJ" SPUTTER SILICON 0I0XIDE

V »J%,.»^«.,.'^V-J».V-.»«.<£/ PATTERN TOP PHOTORESIST FOR n+ IMPLANT FIRST LAYER SILICON DIOXIDE

REACTIVE ION ETCH SILICON DIOXIDE WITH UNDERCUT OF BOTTOM PHOTORESIST V V V V V V V SECOND LAYER nT IMPLANT SILICON DIOXIDE

• • • ^ • • • «. V*.. •••• n-DOPED

SPUTTER SECOND LAYER GaAs SILICON DIOXIDE

+ + ++ ETCH SECONO LAYER SILICON

1 + + |yiVJ+g''A + + + DIOXIDE SIDEWALLS n -DOPED + + GaAs REMOVE REMAINING PHOTORESIST

ANNEAL SILICON + + NITRIDE + + OPEN WINDOWS FOR OHMICS

DEPOSIT OHMIC CONTACTS

ALLOY OHMIC CONTACT METALIZATION

ETCH GATE WINDOW THROUGH SILICON NITRIDE y % • + ++ + DEPOSIT GATE METAL GATE METAL

Figure 4.4 Self-Aligned Implantation of N+-layer Technology ( SAINT ) process ( after Yamasaki et al. [45] ).

-70- [46], a flowchart of their process is shown in figure 4.5. After channel

implantation a dummy Si02 gate is formed and then covered with plasma-

enhanced chemical vapour deposited Si3N4. The plasma deposition causes the nitride to cover the sides of the gates as well as the wafer surface. When the wafer is then implanted, the n+ regions are separated from the dummy gate by the thickness of the nitride layer. A number of selective plasma etch steps are then done to expose the GaAs where the dummy gates were located. A non-critical photolithography step allows the gate metal to be deposited after which the the remaining masking layers are removed. As in the SAINT process, the main advantage of this process is that the gate need not withstand the high annealing temperatures so that a lower resistivity gate metal can be used. An advantage of this technology over the SAINT process is that the separation between the ohmic regions and the gate is controlled by a deposition rather than by an undercut etch, deposition being potentially more uniform across the wafer.

4.2.4 Ohmic contact formation

The source and drain contacts of an FET should be non-rectifying and have a sufficiently low resistance. The non-rectifying characteristic

is obtained by having a very high ( >1019 cm"2 ) donor concentration near

the metal-semiconductor interface, allowing the electrons to tunnel

through the very narrow depletion region [47].

Ohmic contact resistance consists of two parts: the contact resistance of the interface and the sheet resistance of the semiconductor

-71- \ \ \ \ \ \ \

CHANNEL IMPLANT SEMI-INSULATING GaAs

n *i.>i n.rr rt'rr n,ir iicvv-jr SILICON DIOXIDE K» •» • v s • v • v *• • v-v s •! DUMMY GATE FORMATION PHOTORESIST

SILICON PECVD SILICON NITRIDE DEPOSITION AND PATTERNING DIOXIDE

nr IMPLANTATION

ANNEALING n-DOPED GaAs NITRIDE ETCH ++ + + + + OHMIC CONTACT METALIZATION n -DOPED RESIST COATING GaAs

RESIST PLASMA ETCH

SILICON NITRIDE DUMMY GATE REMOVAL

OHMIC CONTACT METALIZATION

GATE METAL EVAPORATION AND LIFT OFF GATE METAL

Figure 4.5 Sidewall-assisted pattern inversion process ( after Hagio et al. [46] ).

-72- between the ohmic area and the channel. Contact resistance is reduced by increasing the carrier concentration at the surface, while sheet resistance is reduced by increasing the carrier concentration or by effectively increasing the thickness of the doped layer.

Ohmic contact sheet resistance reduction is used with both epitaxial and ion-implanted FETs. Epitaxial FETs use the gate recess technique to etch the channel to the desired total doping level. During epitaxial growth the epi layer is made thick enough to provide the desired low sheet resistance. Since the channel is etched anyways it is also possible to grow a thin n+-layer on top of the channel layer to further decrease sheet resistance.

Most ion-implanted FETs use a second, high dose implant to decrease the sheet resistance of the ohmic contact areas. This can be accomplished either by using a separate implant mask or by using one of the self-aligned techniques described in the previous section.

The other component of ohmic resistance is the contact resistance of the interface between the ohmic metal and the semiconductor. The technique used almost universally with GaAs is to include a certain amount of n-type dopant in the ohmic contact metal. After evaporation and lift-off the ohmic contacts must be alloyed to allow the dopant to diffuse into the surface of the GaAs. Since the diffusion depth is small a very high surface doping concentration can be obtained.

The most commonly used procedure is to evaporate a eutectic mixture of

AuGe ( 88-12% by weight ) which is alloyed at 400 - 500 °C for about 2 minutes. Ni is often evaporated on top of the AuGe; it apparently acts

-73- as a wetting agent during alloying and results in improved ohmic character• istics as well as giving a harder and more durable surface. After alloying another, thicker layer of Au is often deposited to facilitate wirebonding.

During the alloying cycle the ohmic metal melts and forms small bumps on the surface of the contact ( see figure 4.10, page 88 ). In general, the larger these bumps are the poorer the ohmic characteristics will be.

Kuzuhara et al. [48] reported an alternative technique which does not require an alloying temperature above the AuGe eutectic point and which thus results in a smooth surface morphology. The high surface donor concentration was obtained by ion-implanting Si at a dose and energy of

>7xl013 cm"2 and 150 keV respectively. The implant is activated by rapid

thermal annealing at 1120 °C for 5 seconds using a SiOxNy encapsulant, after which AuGe-Ni contacts are evaporated and lifted off and the wafer is briefly heated to 300 °C to activate the contact.

4.2.5 Passive components

In addition to MESFETs, most MMICs will also require passive components.

The different types of passive components were briefly discussed in section

1.3; this section will discuss the processing steps required to fabricate them.

Many passive components can be made using essentially the same processing steps as used for MESFET fabrication, although often apparently redundant

steps are added so as to not compromise FET yield or characteristics. There are two additional "components" that are often used which require additional

-74- processing steps; these are airbridges and backside via holes. Airbridges are used where low capacitance crossovers are required, such as spiral inductors and large gatelength power FETs. The fabrication process is shown in figure 4.6. A first thick layer of photoresist is patterned to open holes where the airbridge will contact the first layer metal. A thin layer of metal is then sputter deposited and a second photoresist layer is used to define the airbridges. The exposed sputtered metal is electro-plated with gold to about 1 fim thickness after which the top photoresist is removed.

The electro-plated gold is then used as an etch mask to remove the undesired

sputtered metal, after which the first layer of photoresist is removed,

leaving the final bridge.

Via holes are used when low inductance microwave grounds are required in microstrip based designs. After all the topside processing is done the wafer is thinned from the backside to the final thickness, usually between

100 and 200 /jm, and the backside is patterned and etched. Infrared mask

aligners are usually used to align the back to the front. Great care must be taken after thinning because the thin wafers are very fragile.

With the processing steps discussed so far, all MMIC passive and active

components can be fabricated. For most devices a choice of possible

technologies exists with the final decision being based on circuit requirements such as tolerance and reliability, and production constraints

such as available equipment and cost. Resistors can be made either by

sputter depositing a thin film resistive material or by using n-doped GaAs.

In the latter case a separate recess etch ( for epitaxial wafers ) or

implant ( for ion-implanted wafers ) is often used to allow independent

-75- Illlllllll LUTJ llllllllllllilll STARTING WAFER WITH FIRST LEVEL METALIZATION

PATTERN SUPPORT PHOTORESIST

DEPOSIT THIN CONDUCTIVE LAYER

PATTERN BRIDGE PHOTORESIST

ELECTROPLATE Au BRIDGE CONDUCTOR

REMOVE PHOTORESIST

ETCH THIN CONDUCTIVE LAYER

fflTTJJJ I 1 V////A FIRST LEVEL PHOTORESIST THIN CONDUCTIVE GOLD GaAs METALIZATION WAFER LAYER AIRBRIDGE

Figure 4.6 Airbridge fabrication process.

-76- optimization of FET channel parameters and resistor characteristics. The sputtered resistor requires slightly more processing but can be more accurate and uniform and have a lower temperature coefficient of resistance than the semiconductor resistor, which takes up less space.

Capacitors can be made either with a planar interdigitated structure or using a metal-insulator-metal ( MIM ) sandwich structure. The interdigital capacitor is more repeatable ( but much harder to model ), easier to make and has a higher yield than the MIM capacitor but is limited in value to

about 1 pF. For larger values an MIM capacitor is required; sputtered Si02

or Ta205 or plasma-deposited Si3N4 are the usual dielectrics and an airbridge is often used to connect the top plate to the rest of the circuit to reduce the chance of a short circuit at the edge of the capacitor.

Inductors are either simulated using a short length of high impedance line or made as a loop inductor. Multiturn inductors require an airbridge

to access the centre of the inductor, or a via hole can be used in the case

of shunt elements. Coupled inductors have also been demonstrated using

these techniques.

4.3 Refractory metal self-aligned gate MESFET fabrication technology

The refractory metal self-aligned gate MESFET fabrication technology developed at the University of British Columbia is closely based on that by

Levy and Lee [43] and Sadler [35]. The complete process of MESFET

fabrication requires five masks, while a sixth mask is required for the MIM capacitor of the sample-and-hold. The UBC process differs significantly in

-77- the wafer cleaning procedures, the photolithography steps and the annealing conditions. There are several other minor modifications such as the use of a plasma etch rather than a reactive ion etch ( RIE ) to undercut the gate mask and the choice of implant dose and energy to obtain depletion mode rather than enhancement mode FETs.

A flowchart of the MMIC process is shown in figure 4.7; a detailed step by step description follows in table 4.1. The development of this processing technology is to a large extent an evolutionary process of trial

and error; when a particular run does not yield expected results it is often

difficult to isolate the step that caused the problem. Although the process

described here gives reasonable devices it is by no means fully mature. The main steps that could use improvement are discussed below, as are those that

are not self-explanatory.

Steps 1-2 Wafer cleaning

The wafers are received at UBC with both sides polished. The polishing

is done using a combination of chemical and abrasive means. The

resulting surface damage, and also possible surface contamination, can

cause inconsistent and poor results. Therefore, the surface layers are

removed by etching prior to subsequent processing. Step 1 is used to

thoroughly degrease and clean the wafer, immediately thereafter step 2 is

used to etch about 2 pirn from the surface in a slow and uniform manner.

The same etching solution is also used for the registration mark etch,

allowing the etch rate and hence the surface etch depth to be determined

from the registration mark depth and etch time.

-78- V V Y Y V V V CHANNEL IMPLANT SEMI-INSULATING GaAs

PHOTORESIST

REFRACTORY GATE METAL DEPOSITION

GATE IMPLANT MASK GATE IMPLANT DEFINITION MASK

GATE DEFINITION ETCH (WITH UNDERCUT) rrrTTrnTira y slv •» • Z*

Y Y Y Y Y Y Y vViViii' n-DOPED n n +OHMIC IMPLANT GaAs rTTTnTTJTTTj

STRIP GATE IMPLANT MASK

TiW GATE ANNEAL METALIZATION

• :+++.

rfFfrs rr -DOPED 6aAs • •••» V + + + ++ OHMIC CONTACT DEPOSITION

ALLOYING

OHMIC CONTACT METALIZATION

ure 4.7 UBC refractory metal self-aligned-gate MESFET fabrication process flowchart.

-79- TABLE 4.1 DETAILED SELF-ALIGNED GATE PROCESS LOG

STEP PROCESS DESCRIPTION

1 Wafer cleaning * 1% Alconox solution (NaH2P04) , 4 min

* DI rinse, 1 min, N2 blow dry * boiling acetone, 5 min * boiling isopropanol, 5 min

2 Surface etch (=2 /zm) * 2H202: 5NH40H: 240H20, 27°, 10 min * DI rinse, 30 sec * boiling isopropanol, 5 min

3 Photoresist deposition * spin-on S1400-30, 4000 rpm, 20 sec * softbake 95°, 25 min, cooldown

4 Registration mark * 320 ran, 20 mWcnf2, 30 sec exposure and develop * spray develop, 30 sec ( 37 sec if chlorobenzene treatment used ) * DI rinse, 15 sec

5 Registration etch * 2H202: 5NHA0H: 240H20, 27°, 30 sec * DI rinse, 15 sec

6 Strip photoresist * boiling acetone, 5 min

* boiling isopropanol, 5 min 7 Photoresist deposition * as in step 3 8 Channel exposure * as in step 4 9 Light cleaning etch

* 1H202: 1NH40H: 240H20, 27°, 3 sec * DI rinse, 15 sec

* 10% NHA0H, 1 min ( Ga203 removal )

* BHF, 1 min ( As205 removal ) * DI rinse, 10 min

* N2 blow dry 10 Channel implant * 29Si, energy=100 keV, dose=2.5xlO-12cnT2 * wafer orientation: 7° tilt, 22° rotation

11 Photoresist strip * boiling acetone, 10 min * "microstrip", 90°, 5 min * DI rinse, hot, 15 sec * boiling acetone, 5 min * boiling isopropanol, 5 min

* N2 blow dry

12 Light cleaning etch * as in step 9

-80- 13 Gate metal deposition * rf sputter deposition, Ar atmosphere, TiW, 2000 A 100 W, 33 mTorr, 22 min

14 Gate metal patterning * S1400-30, 4000 rpm, 20 sec and exposure * softbake 95°, 25 min, cooldown * immerse in chlorobenzene, 2.5 min * expose as in step 4

15 Gate implant mask * evaporate 4400 A Al ( or 3500 A Cr ) deposition

16 Liftoff * boiling acetone, gentle agitation

17 Gate undercut etch * CF4/02 plasma, 100 W, 500 mTorr 120°

CF4 = 200 seem, 02 •= 8 seem, 2 min

18 n+ patterning * as in steps 3-4 and exposure

19 Light cleaning etch * as in step 9

20 N+ implant * 28Si, 100 keV, lxl013cnf2

* wafer orientation as in step 10 21 Photoresist strip * as in step 11 22 Al removal * warm cone. HC1, 1 min 23 Light cleaning etch * as in step 9

24 Si3N4 encapsulent * NH3 plasma preclean, 5 min deposition * plasma deposition, 500 A, 300°, 100 W 1500 mTorr, He = 500 seem,

SiH4 = 550 seem, NH3 =37.6 seem

25 Implant anneal * Minibrute furnace, 825°, 25 min

1 -0/min N2 atmoshere

26 Si3N4 removal * 40% HF, 3 min, buffered HF, 1.5 min * DI rinse, 10 min

27 Si3N4 passivation and * as in step 24 capacitor dielectric deposition

28 Ohmic contact * as in step 14 patterning and exposure

29 Light cleaning etch * as in step 9

-81- 30 Ohmic deposition * evaporate AuGe (88-12%), 2000 A, Ni, 200 A

31 Liftoff * as in step 16

32 Alloy * Minibrute furnace, 425°, 2 min,

1 i/min N2 atmosphere

33 Ohmic gold and * as in step 14 capacitor top plate patterning and exposure

34 Au deposition * evaporate 2000 A Au

35 Liftoff * as in step 16

-82- Step 6 Photoresist strip

A number of different techniques are used depending on the difficulty of

removal. In most cases boiling acetone is sufficient, but after implants

the resist is damaged and requires the use of 02 plasma or "microstrip"

remover. There is no apparent damage to the GaAs by any of these

methods.

Step 9 Light cleaning etch

It was found that the device characteristics are strongly affected by any

surface contamination. The cleaning process used here removes about 50 A

from the surface which does not significantly alter the doping profile

even after repeated application and is organic contaminant free. It is

used before each implant and each metal or nitride deposition.

Step 13 Gate metal deposition

This step was previously proceded by an in situ Ar sputter etch of the

GaAs before deposition. The resulting poor activation is thought to be

due to the surface stoichiometry change caused by the lighter Ga atoms

being more easily sputtered than As.

Step 14 Gate metal patterning and exposure

A chlorobenzene soak is used here before developing to remove the

solvents from the top layer of photoresist. The resulting harder top

layer develops more slowly than the rest of the photoresist so that an

overhanging resist profile is obtained. During subsequent metal evapo•

ration this overhang ensures a discontinuity between the desired and

undesired metalization areas which eases liftoff.

Step 16 Liftoff

-83- If necessary, a brief immersion in an ultrasonic bath can aid liftoff,

but if overdone this can also remove the Al implant metal from the

desired areas.

Step 25 Anneal

Originally two anneals were done, one after each implant, but better

activation was achieved with only one anneal after the isolation implant.

The annealing temperature is relatively low compared to conventional

furnace anneals to minimize interactions between the TiW and the GaAs. A

fair bit of experimentation was done using rapid thermal annealing, and

although the best runs gave better activations than the best furnace

anneals, the results were not reproducible from run to run. This might

be attributable to the use of wafers from different suppliers and

different boules, and since rapid thermal annealing seems to be

potentially superior it warrants further investigation.

Step 27 Si3N4 passivation and capacitor dielectric deposition

A separate nitride layer is used rather than the annealing cap to

minimize the probability of pinhole shorts.

Step 32 Ohmic contact alloying

Some work was done to investigate the use of the rapid thermal anneal

technique to alloy the ohmic contacts. As in the case of the channel

anneal this is promising but needs more investigation.

The sample-and-hold mask set layout is shown in figure 4.8. To reduce cost, three mask layers were put on each mask so that only one out of three rows on the wafer contains useful devices. The bottom row of figure 4.8

-84- contains the input buffer amplifier, a dual gate switch, an MIM capacitor and the output buffer amplifier. On the top row there are discrete single

and dual gate transistors, a diode and a capacitor for testing purposes. A photomicrograph of the chip is shown in figure 4.9, an SEM closeup of a dual gate FET after removal of the nitride is shown in figure 4.10. The gate

lengths are about 0.5 Lim with about 4 Lira spacing between the gates. The nonuniform texture of the ohmic contacts is also visible.

-85- Ed co Eb < Eb E- Ed 03 Et] Eb t—I E- Eb < ECOd a. _2 as E- 0* o«* Ed oa X o E- »—i o C3 O w i—i E- o < s: a, i—i «C

D

a Ed E- Ed 4 Eb a O O Ed CQ i-t Ed E- Eb _] Ed E- i-t O EL, a, a. Z CO .-. » Z X CO X

Figure 4.8 Sample-and-hold mask layout.

-86- Figure 4.9 Photomicrograph of sample-and-hold chip.

-87- I 1 5 ym

Figure 4.10 Scanning electron micrograph of dual gate MESFET.

-88- CHAPTER 5 MEASUREMENT TECHNIQUES AND RESULTS

5.1 Introduction

The measurement of device parameters and performance is a vital and non-

trivial part of the development of a processing technology [49]. In this

chapter the measurement techniques used to evaluate device performance will be discussed and results presented.

The measurements used can be divided into two categories, low frequency

or static measurements which give information about the the individual

device model parameters, and microwave measurements which give information

about the high frequency characteristics of the device as a whole. If

measurements and modeling are carried out correctly there should be good

correspondence between the low frequency and the high frequency results.

The emphasis in this thesis is on low frequency measurements. The reasons

for this can be summarized as follows

-availability of test equipment

-ease of wafer scale testing

-ease of isolating device parameters

-can be done at different points in the fabrication process.

Two catagories of low frequency measurements can be distinguished. Capa•

citance versus voltage ( CV ) measurements can be made of reverse biased

Schottky barrier diodes to obtain doping profiles. Current versus voltage

( IV ) measurements can be made of diodes to obtain reverse saturation

current, ideality factor and barrier height, and of transistors to obtain

-89- saturated current, threshold voltage, transconductance and source and drain resistance. In the following sections the techniques used to make these measurements will be presented.

5.2 Diode measurements

The most important application of diode measurements is to determine the quality of the channel anneal step. This is particularly important in a refractory metal-based self-aligned gate technology since the gate is present during the anneal and can potentially react with the GaAs.

CV measurements using a HP4061A LCR meter controlled by a HP9816 computer are performed on large area diodes to determine the doping profile of the

active layer. The doping profile ND(W) is obtained by measuring the capacitance at different bias levels and applying the following formulas.

The capacitance per unit area is

C(V) = e/W(V) (5.1)

where W(V) is the depletion width at bias voltage V, and

2 _1 ND(W) = ( -2/q€ ){ d(l/C )/dV } (5.2)

This method of obtaining the doping profile is limited to a small forward bias on the diode. If the bias is increased too much the resulting current makes accurate determination of the capacitance impossible. Accurate

-90- determination of the doping profile near the surface is thus not possible with this technique. A typical doping profile is shown in figure 5.1. with the "best fit" LSS profile calculated using a program written by David Hui.

Diode IV measurements are made using the HP4145A semiconductor parameter analyzer. The parameters of interest are the ideality factor n, the reverse

saturation current I0, the Schottky barrier height h and the diode series

resistance Rs. The basic diode equation, neglecting Rs, is

I(V) = I0[ exp( qV/nkT ) - 1 ] (5.3)

For V > ~ 3nkT/q the factor 1 can be neglected, and taking the natural logarithm of both sides and differentiating with respect to V gives

d ln(I)/dV = qV/nkT + ln(I0) (5.4)

Plotting ln(I) versus V yields a straight line for a limited range of V, the

slope of which is proportional to 1/n and the y-intercept of which is I0,

which can be used to obtain h from

2 h = ( kT/q )ln( A**T S/I0 ) (5.5)

where where A** = 8.4 Acm"2K"2 is the effective Richardson constant for GaAs

and S is the area of the diode [35].

A typical diode IV plot obtained with the HP4145A is shown in figure 5.2.

The analyzer is programmed to calculate n directly to facilitate measuring a

-91- Figure 5.1 Typical capacitance/voltage doping profile.

-92- LNI IF ) CURSOR ( 3400V . •296E-03 6.356mA ) (mA) MARKER (• 2300V . •491E-03 •5.940nA )

119.71 10.00 E-03

j

48.47 1.000 /div /div

-604.4 .0000 -.5000 2.000 2500/div ( V) 1/GRAD j Xintercept| Yinterceptj LINEl! 911EHD3_j 1_. 10_E+00i 666E-03 [ -606E-03 LINE2J 1"1" " ""-] LNI ( ) 26E-3*LN (ABE (I) )

Figure 5.2 Typical diode current/voltage plot.

-93- large number of devices. Typically, n ~ 1.1 for refractory metal self- aligned gate devices.

As the voltage is increased the linear dependance of ln(I) on V breaks

down due to the presence of the parasitic series resistance Rs. As the voltage is increased the voltage drop across the resistance dominates the drop across the diode so that a plot of I versus V gives another straight

line with slope 1/RS.

5.3 Transistor measurements

Accurate measurement of transistor parameters is important to study the

effects of changes in processing steps and to allow realistic modelling of

larger scale circuits to be performed.

The MESFET model used in the simulations in this thesis is a symmetric

square law model, with the gate-source and gate-drain junction effects given by a Schottky diode model [50], the general equivalent circuit is shown in

figure 5.3. The diode parameters I0, n and b can be obtained in the manner

discussed in section 5.2

Because of the small gate area of microwave transistors it is not

possible to directly obtain accurate gate capacitance measurements. Gate

capacitances can be measured on so-called fat FETs which can have gate

lengths and widths of 100 firn or more. The zero bias gate capacitance is measured with the source and drain tied together and yields a depletion

capacitance per unit area. Since with a self-aligned gate process the

transistor is physically the same on both the source and the drain side, the

-94- Figure 5.3 Symmetric MESFET model equivalent circuit ( after Curtice et al. [50] ).

-95- zero bias gate-source and gate-drain capacitances should also be the same and can be obtained from the fat FET values by multiplying by the gate area.

As mentioned in section 3.3, for small gate length transistors there will also be a significant fringing capacitance from the edges of the gate; this is shown schematically in figure 5.4, assuming a uniform doping profile and ignoring the proximity of the source and drain n+ regions [51]. The depletion region is divided into two regions. Region I is the one- dimensional region under the gate, the standard depletion capacitance formulas are assumed to hold here. Region II consists of two quarter- circular regions on either side of the gate, with radius W, where W is the depletion width of region I. Then,

W = J{ ( 2e/qND )( Vbi - V - kT/q ) } cm (5.5)

2 Q = qNDLW + 4qND7rW C (5.6)

2 ^TOTAL " I 5Q/aV | - e( L/W + Tr ) Fern" (5.7)

Eqation 5.7 gives the total gate capacitance per unit gate width, and, since the transistor is assumed to be symmetric, the drain and source components

will both be given by CT0TAL/2. The zero bias source and drain capacitances required by the model are then given by

2 1

CGSO = CGD0 = 7( qNDeL /8Vbi ) + Tre/2 Fern" (5.8)

-96- GATE per cm of gate width. The first term can be obtained from diode or fat FET data so that no detailed knowledge of the doping profile is required.

The FET channel current in the saturation regime can be modelled by

IDS " K( VGS " VT )2( 1 + AVDS )( TANH «VDS ) (5-9)

where VT is the threshold voltage, and K, A and a depend on the device

geometry and semiconductor parameters [47,50]. A typical plot of ,/lDS

versus VGS is shown in figure 5.5. It fits the linear approximation quite

well. VT is defined as the x-axis intercept of the quadratic region

asymptote and K is given by the square of its slope. The variation of IDS in the linear regime is controlled by the hyperbolic tangent parameter a.

It can be determined from the slope of IDS for small VDS as

AV AIDS/ DS a = (5.10) 2 K-VT

VGS= 0, VDS« VDS_sat

The channel length modulation parameter A is often used in computer

simulation programs to account for the small slope of IDS versus VDS in the saturation regime; it can be evaluated from

AIDS/AVDS A = (5.10)

2 K-VT

vGS= o, vDS> VDS t

The measurement of source and drain resistances is more complicated

-98- if A) CURSOR (-2.4200V 16.6E-03. MARKER (-3.0000V 2.80E-03,

124.0 E-03

12.39 /div

1580 -3.440 4300 VG .4,300/di v ( V) GRAD 1/GRAD Xintercept Yintercept LINE1 32.1E-03 31.1E+00 -2.94E+00 94.3E-03 LINE2 SQBT (/A) - /IS

Figure 5.5 Typical plot of Jlos versus VGS used to determine threshold

voltage VT and gain parameter K

-99- because of the difficulty of isolating the parasitic resistances, which are not modulated by the applied gate voltage, and the channel resistance, which is. The method used in this thesis was proposed by Lee et al. [52] and is shown schematically in figure 5.6. In this setup the gate is slightly forward biased with respect to the source so that a small gate current flows. At the same time, a constant current source is used to obtain a small drain current while the drain-source voltage is monitored as the gate current is perturbed slightly. As the drain current increases the drain side of the gate becomes increasingly reverse biased and the gate current gets concentrated in the source side of the channel. The differential end

resistance Rend is defined as

avDS Rend (5.12) aiGS

Ipg—const

and in [52] it is shown that, for a limited range of IDS, this becomes

R R end = s + nkT/qIDS (5.13)

Thus, by plotting AVDS/AIGS versus 1/IDS and finding the y-axis intercept of

the linear portion with slope nkT/q one can determine Rs. By reversing the

source and drain terminals one can obtain RD. A typical plot is shown in

figure 5.7.

-100- -101- REND (ft ) CURSOR ( 454E+00 . 30.0E+00. MARKER [ 454E+0Id . 30.0E+00. ) /

50.00 -\ /r E+00 / f / / / • 5.000 /div / / *

•

.0000 .0000 1.500 IDINV .1 500/div ( ) E+03 GRAD 1/GRAD Xintercept Yintercept LINE1 52.6E-03 19.0E.00 -117E+00 6.18E+00 LINE2 REND (O ) - AVDS/AIG IDINV ( ) - 1/ID

Figure 5.7 Typical end-resistance plot giving Rs.

-102- Another parameter which is commonly used is the transconductance defined as

aiDS (5.14)

Vpg=const

It is usually expressed in millisiemens per millimeter of gate width. It is

a small signal parameter, however, and depends strongly on operating point;

it is most often measured at VGS = 0 or VGS = +0.8 V. A typical plot of

versus VGS is shown in figure 5.8.

For comparison purposes the K-factor defined earlier is a more universal

figure of merit since it is not operating point dependant.

The model parameters for a typical recent FET are given in table 5.1.

These parameters are used in the SPICE simulations of chapter 3. To show

the validity of at least the static part of the model, the simulated and

measured transfer curves of this FET are shown together in figure 5.9.

-103- (mS) CURSOR ( .OOOOV 5.98E+00. MARKER ( ,6000V 7.17E+00 -1 1 r i ^ \ _ .Ii . I i cn E+00 i i ! j ! .... (

6976 i ( /div ! ! I r 1 ! i

---f-—

0000 -3.440 0 .4300 VG 4300/div ( V)

SQRT if A) - /IS GM (mS) - 1000KAID/AVG

Figure 5.8 Typical plot of transconductance g,,, as a function of gate bias.

-104- PARAMETER SPICE DESIGNATION VALUE

Threshold voltage, VT VTO -1.80 V

Hyperbolic tangent parameter, a ALPHA 0.86

Transconductance parameter, /9 BETA 2.68X10"3 A/V2

Channel length modulation parameter, A LAMBDA 2xl0"5

Source resistance, Rg RS 6.17 n

Drain resistance, RD RD 20.7 n

Gate resistance, RQ RG 3 kfi

Zero-bias gate-source capacitance, CGS0 CGSO 0.28 pF

Zero-bias gate-drain capacitance, CGD0 CGDO 0.28 pF

Gate diode ideality factor, n N 2.2

Gate built-in potential, ^b VBI 0.8 V

Drain-source capacitance, CDS CDS 0.07 pF

Table 5.1. Self-aligned gate MESFET model parameters used in SPICE

simulations.

-105- EEsof - mwSPICE r- 5/9/BB - 16: IB: 14 - DTA SAGFET . IDS REAL 0.0150

— • 1'

• • < m •

0.0050 • • • • <

• • • • !L » • •« 1 * • _. ,. ..a— •

0.0000 1.500 VDS 3.000

Figure 5.9 UBC self-aligned gate MESFET transfer curves: ( ) measured, ( • • • ) simulated.

-106- CHAPTER 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK

The work done in this thesis can be divided into two sections. The first

deals with high speed sampling and its application to the sampling amplifier

concept developed at the Defense Research Establishment Ottawa ( DREO ). A

literature survey was done to determine the state of the art for high speed

sampling circuits. It was found that the highest speed electronic sampling

is achieved using solid state mechanical sampling heads used in sampling

oscilloscopes, with bandwidths of about 18 GHz. The highest speed monolithic circuits are made with gallium arsenide and have bandwidths of

about 2 GHz. Some of the different types of sample-and-hold circuits were

discussed, ranging in complexity from a single switch and storage capacitor

to multistage feedback circuits.

The important parameters of the two most common types of switch were also

investigated. It was found that the six diode ring switch can handle the

largest voltage swing but requires a balanced current switch drive, which

can be difficult to obtain if a number of switches are to be used in parallel at a high sampling rate. The FET switch uses a single-ended voltage drive and is therefore more suited for applications, such as the

sampling amplifier, requiring a large number of switches in parallel. High

speed switching will require the use of GaAs MESFETs so that the maximum

allowable voltage swing will be limited to about 0.5 V by the conduction of

the forward biased gate diode. The use of a dual-gate MESFET to reduce

sample pulse feedthrough, as was reported in [18], was investigated and

found to have minimal effect in most practical applications.

-107- The effects of sampling circuit parameters on the performance of the sampling amplifier were investigated in chapter 3. It was found that the main factor determining the number of channels that can be used without introducing excessive loss is the input impedance of the sampling circuits.

In order to minimize this loss, high input-impedance buffer amplifiers are required to isolate the switches from the delay line. The performance of one such amplifier was analyzed using a simplified low frequency model as well as simulated using the computer program Microwave-SPICE. The performance of this amplifier should be adequate up to at least 10 GHz.

The other main area of investigation in this thesis is the technologies used in the manufacture of gallium arsenide monolithic integrated circuits.

The main components used in MMICs were discussed, and the most important processing technologies reported in the literature were discussed In some detail. Much work is being done to develop self-aligned gate technologies, which have the advantages of maintaining a planar structure and being potentially simpler to manufacture, as well as having improved speed performance due to the reduction of parasitic source and drain resistances by reducing the spacing between the gate and the ohmic n+ regions. The development of a refractory metal T-gate self-aligned gate process technology at the University of British Columbia was presented; in this process the distance between the gate and the ohmic regions is determined by the amount of undercut of the gate implant mask. The gate material itself is present during the anneal, and much effort was required to determine the best annealing conditions in order to obtain adequate activation without excessive interaction between the titanium-tungsten gate material and the

-108- gallium arsenide.

Chapter 5 deals with the measurements used to characterize the performance of the Schottky diodes and MESFETs made at UBC. The emphasis is

on dc measurements since it is easier to isolate the various parameters, and

the measurements themselves are easier to perform. The measurement methods used to obtain the various model parameters used for computer simulation were given and results given for some recently fabricated FETs. The

simulation results showed good agreement with the measured values. A test

j ig was made to allow measurement of the microwave parameters of one of the better FETs at Harris/Farinon in Montreal, but the FET was damaged in

transit to Montreal so that no measurements were possible.

The fabrication steps used to make discrete devices are readily extended

to allow fabrication of a complete monolithic sample-and-hold circuit,

including input and output buffer amplifiers, a MESFET sampling switch and a

hold capacitor. In the initial mask design, the sum of the widths of the

input and feedback transistors was not chosen to be equal to the width of

the current source transistor. This resulted in a significant dc offset

which caused the output stages to be turned off under normal operation, no

measurements of amplifier performance were therefore possible.

Most of the future work will be required in the processing area. The

main areas of interest are the use of rapid thermal annealing to anneal the

channel and n+ implants without using a dielectric annealing cap and with

minimum interaction between the gate and the gallium arsenide as well as to

alloy the ohmic contacts. The physical effects of the interaction between

the gate material and the substrate during anneal could also warrant

-109- investigation.

The use of the self-aligned gate processing technology to fabricate a complete sample-and-hold circuit should be attempted. For the sampling amplifier, a high sampling rate is not required so one of the multistage

sampling circuits discussed in chapter 2 could be used. The buffer

amplifier topology discussed in chapter 3 should be suitable if the gate

dimensions are appropriately chosen; the dimensions given in figure 3.7

suggested. Given suitable drive circuitry, maximum sampling rates of at

least 1 GHz should be attainable, with sampling times of less than 100 ns

-110- REFERENCES

R.E. Lehmann and D.D. Heston, " X-band monolithic series feedback LNA," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1985.

C. Andricos, I.J. Bahl and E.L. Griffin," C-band 6-bit monolithic phase shifter," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1895.

S.D. Bingham, S.D. McCarter and A.M. Pavio, " A miniaturized 6.5-16 GHz monolithic power amplifier module," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1895.

Y. Ayasli, R.A. Pucel, J.L. Vorhaus and W. Fabian, "A monolithic X-band single-pole, double-throw bidirectional GaAs FET switch," 1980 IEEE GaAs IC symposium digest.

S. Hori, K. Kamei, K. Shibata, M. Tatematsu, K. Mishima and S. Okiano, " GaAs monolithic MIC's for direct broadcast satellite receivers," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-31 , No. 12, Dec. 1983.

P. Harrop, P. Lesarte and A. Collet, " GaAs integrated all-FET-front- end at 12 GHz, " 1980 IEEE GaAs IC symposium digest.

Y. Ayasli, L.D. Reynolds, R.L. Mozzi and L.K. Hanes, " 2-20 GHz GaAs travelling wave power amplifier," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-32, No.3, March 1984.

P. Bauhahn, T. Contolatis, J. Abrokwah, C. Chao and C. Seashore, " 94 GHz planar GaAs monolithic balanced mixer," 1984 IEEE microwave and millimeter-wave symposium digest.

G.A. Breed, GaAs digital ICs promise exciting RF applications, RF Design, April 1986.

] K.C. Gupta, R. Garg and I.J. Bahl, " Microstrip lines and slotlines," Artech House, 1979.

] S.R. Forrest, " Monolithic optoelectronic integration: a new component technology for lightwave communications," IEEE Trans. Elecron Devices, Vol. ED-32, No.12, Dec. 1985.

] L.J. Conway and S.L. Bouchard, " The sampling amplifier (U)," DREO report No. 863, June, 1982.

-Ill- [13] K.R. Stafford, P.R. Gray and R.A. Blanchard, " A complete monolithic sample/hold amplifier," SC-9, No.6, June 1974.

[14] W.M. Grove, " Sampling for oscilloscopes and other RF systems: DC through X-band," IEEE Trans. Microwave Theory and Techniques, Vol. MTT- 14, No.12, Dec. 1966.

[15] S.M. Riad, " Modelling of the HP-1430A feedthrough wideband (28 ps) sampling head," IEEE Trans. Instrumentation and Measurement, Vol. IM- 31, No.2, June 1982.

[16] S.D. Givens, " Bipolar and DMOS technologies team up to produce a fast sample and hold amplifier," IEEE Midcon/80 Conference Record.

[17] P.H. Saul, " A GaAs MESFET sample and hold switch," IEEE J. Solid State Circuits, Vol. SC-15, No.3, June 1980.

[18] G.S. Barta and A.J. Rode, " GaAs sample and hold IC using a 3-gate MESFET switch," 1982 IEEE GaAs IC Symposium Digest.

[19] S.J. Harrold, I.A.W. Jance and J. Mun, " A GaAs switched capacitor filter," 1985 IEEE GaAs IC Symposium Digest.

[20] A.S. Blum, " Frequency response of finite aperture sample-and-hold systems, IEEE Trans. Nuclear Science, Vol. NS-30, No.l. Feb. 1983.

[21] H. Wollman, " High speed ADC systems for waveform analysis," IEEE Trans. Instrumentation and Measurement, Vol. IM-33, No.3, Sept. 1984.

[22] T.M. Sonders, " A bridge control for the dynamic characterization of sample/hold amplifiers," IEEE Trans. Instrumentation and Measurement, Vol. IM-27, No.4, Dec. 1978.

[23] D.P. Hornbuckle and R.L. Van Tuyl, " Monolithic GaAs direct-coupled amplifiers," IEEE Trans. Elecron Devices, Vol. ED-28, No.2, Feb. 1981.

[24] A. Gopinath and J.B. Rankin, " GaAs FET RF switches," IEEE Trans. Elecron Devices, Vol. ED-32, No.7, July 1985.

[25] J.V. DiLorenzo and D.Khandelwal, eds., " GaAs FET principles and techniques," Artech House, 1982.

[26] C. Kocot and C.A. Stolte, " Backgating in GaAs MESFET's," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.7, July 1982.

[27] A. Markoc and L.F. Eastman, " The growth of uniform submicron GaAs layers by liquid phase epitaxy," J. Electrochem. Soc., Vol. 123, p906, 1976.

-112- [28] H.M. Manasevit and W.I. Simpson, " The use of metal-organics in the preparation of semiconductor materials: I. Epitaxial gallium-V compounds," J. Electrochem. Soc, Vol. 116, pl725, 1969.

[29] P.C. Chao, S.C. Palmateer, P.M. Smith, U.K. Mishra, K.H.G. Duh, and J.C.M. Hwang, " Millimeter-wave low noise high electron mobility transistors," EDL-6, No.10, Oct.1985.

[30] for example, see S.K. Ghandi, " VLSI fabrication principles," John Wiley and Sons, 1983.

[31] J. Kasahara, H. Sakurai, T. Suzuki, M. Arai and N. Watanabe, " The effect of channeling on the LSI-grade uniformity of GaAs FETs by ion- implantation," 1985 IEEE GaAs IC symposium digest.

[32] CP. Lee, R. Zucca and B.M. Welch, " Orientation effect on planar GaAs Schottky barrier field effect transistors," Appl. Phys. Lett., Vol.37, No.3, 1980.

[33] K.P. Pande, O.A. Aina, A.A. Lakhani, V.K.R. Nair and J.M. O'Connor, " A simplified capless annealing of GaAs for MESFET applications," IEEE Trans. Elecron Devices, Vol. ED-31, No.4, Apr. 1984.

[34] B. Molnar, " Close-contact annealing of ion implanted GaAs and InP," Appl. Phys. Lett., Vol.36, No.11, 1 June 1980.

[35] R.A. Sadler, " Fabrication and performance of submicron GaAs MESFET digital circuits by self-aligned ion implantation," Ph.D. Dissertation, Cornell University, Jan. 1984.

[36] H. Kanber, R.J. Cipolli, W.B. Henderson and J.M. Whelan, " A comparison of rapid thermal anealing and controlled atmosphere annealing of Si- implanted GaAs, J. Appl. Phys., Vol.57, No.10, 15 May 1985.

[37] K.S. Seo, S. Dahr and P.K. Battacharya, " High quality Si-implanted GaAs activated by a two-step rapid thermal anneal technique," Appl. Phys. Lett., Vol.47, No.5, 1 Sept. 1985.

[38] T. Ohnishi, Y.Yamaguchi, T. Inada, N. Yokoyama and N. Nishi, "

+ Application of the lamp annealing method to the n -layer of WSix-gate self-aligned GaAs MESFETs, EDL-5, No.10, Oct. 1984.

[39] M.H. Badawi, D.R. Dundobbin and J. Mun, " Selective implantation of GaAs for MESFET applications," Electronics Lett. Vol.10, No.15,

[40] D.C. D'Avanzo, " Proton isolation for GaAs MESFET's," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.7, July 1982.

-113- [41] for example, see R.E. Williams, " GaAs processing techniques," Artech House, 1984.

[42] N. Yokoyama, T. Mimura, M. Fukata and H. Ishikawa, " A new self-aligned source/drain technology for ultrahighspeed GaAs MESFET VLSI," ISSCC Tech. Digest, Feb. 1981.

[43] H.M. Levy and R.L. Lee, " Self-aligned submicron gate digital GaAs integrated circuits," EDL-4, No.4, Apr. 1983.

[44] T. Ohnishi, N. Yokoyama, H. Onodera, S. Suzuki and A. Shibatomi,

" Characterization of WSix/GaAs Schottky contacts," Appl. Phys. Lett., Vol.43, No.6, 15 Sept 1983.

[45] K. Yamasaki, K. Asai, T.Mizitani and K.Kurumada, " Self-Align Implantation for N+-layer Technology (SAINT) for high-speed GaAs ICs, Electronics Letters, Vol.18, No.3, 1982.

[46] M. Hagio, S. Katsu, T.Tagaki, M. Kazumura G. Kano, I. Teramoto and H. Mizuno, " A new self-align technology for low noise GaAs MESFET's - Sidewall-assisted pattern inversion technology-," 1984 IEDM Symposium Digest.

[47] for example, see S.M. Sze, " Physics of semiconductor devices," 2nd Edition, Wiley-Interscience, 1981.

[48] M. Kuzuhara, T. Nozaki and H. Kohzu, " Non-alloyed ohmic contacts to Si-implanted GaAs activated using SiO^-capped infrared rapid thermal annealing," J. Appl. Phys., Vol.58, No.3, 1 Aug. 1985.

[49] H. Fukui, " Determination of basic device parameters of a GaAs MESFET," Bell System Tech. J., Vol.58, No.3, Mar. 1979.

[50] W.R. Curtice and M. Ettenburg, " A nonlinear GaAs FET model for use in the design of output circuits for power amplifiers," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-33, No.12, Dec. 1985.

[51] T. Takada, K. Yokoyama, M. Ida and T. Sudo, " A MESFET variable- capacitance model for GaAS integrated circuit simulation," IEEE Trans. Microwave Theory and Techniques, Vol. MTT-30, No.5, May 1982.

[52] K. Lee, M.S. Shur, A.J. Valois, G.Y. Robinson, X.C. Zhu and A. Van Der Ziel, " A new technique for the characterization of "End" resistance in Modulation-doped FETs," IEEE Trans. Elecron Devices, Vol. ED-31, No.10, Oct. 1984.

-114- ! name: 468S128E (2,4) ! date: 86 05 07 ! purpose: COMPARE SIMULATED AND MEASURED TRANSFER CURVES ! FOR UBC SELF-ALIGNED GATE GaAs MESFET.

CKT S2PA_A1 12 0 [MODEL=gasmdl area=l] DEF2P 1 2 SAGFET

MODEL gasmdl GAS M0DEL=1 VTO=-1.80 ALPHA=.86 BETA=2.68E-3 LAMBDA=2e-5 + RS=6.17 RD=20.7 CGS0=.28p CGD0=.28p CDS=.07p VBI=0.8 N=2.1 RG=3K

SOURCE SAGFET IVS_Vds 2 3 DC=3.0 SAGFET IVS_Vmon 0 3 DC=0 SAGFET IVS_Vgs 10 DC =-.4

CONTROL SAGFET DC Vds 0 3.2 Vgs -2 0.5 .5

SPICEOUT SAGFET DC V(all) I(all) END

Appendix Al. mwSPICE listing for transfer curve analysis.

-115- !buffer amp simulation using GaAsFET model !output transient analysis dim cap pf res oh ckt S2PA Al 1 2 0 [model=gl area= =5.1] S2PA_A2 7 2 0 [model=gl area= =4.9] S2PA_A3 2 3 4 [model=gl area= =10] S2PA A4 2 3 2 [model=gl area= =10] S2PA_A5 6 7 6 [model=gl area= =10] S1PA Dl 4 5 [model=dl] S1PA_D2 5 7 [model=dl] DEF2P 1 7 AMP MODEL Dl D CJO=10p IS=1E-15 N=l.l RS=100 VJ=.8 Gl GAS VT0=-1.8 BETA=2.68E-4 LAMBDA=2E-5 RD=62 RS=62 CGS0=3.If TAU=10p RG=3k ALPHA=.86 VBI=.8 CGD0=3.If CDS=.75f SOURCE AMP IVS_Vdd 3 0 DC=4 AMP IVS_Vss 6 0 DC=-2 AMP IVS_Vin 0 tran=pwl(0 0 .2n 0 .4n .5 4.4n .5 4.8n -.5 8.8n -.5 9n 0) AMP CAP_Cload 7 8 c=l AMP RES Rload 8 0 r=50 CONTROL AMP tran .In lOn AMP options list node SPICEOUT AMP tran v(l) v(7) i(cap_cload)

Appendix A2. mwSPICE listing for the buffer amplifier transient response.

-116- ! simulation of a GaAsFET switch dim cap pf res oh CKT S2PA_A1 13 2 [MODEL=gl area=10] S2PA_A2 0 4 3 [model=gl area=10] CAP_Chold 4 0 c=l DEF2P 1 4 SWITCH MODEL gl gas VTO=-1.80 LAMBDA=2E-5 BETA=2.68E-4 alpha=.86 + RS=62 RD=62 CGS0=3.If cgdo=3.If VBI=0.8 CDS=.75f SOURCE SWITCH RES_Rin 10 2 r=10 SWITCH IVS_Vin 10 0 tran pwl(0 0 40n 0 41n .5 lOOn .5 102n -.5 150n -.5 151n 0) SWITCH IVS_Vcntrl 1 0 tran pulse(-3 0 .In .In .In .In lOn) CONTROL SWITCH tran lOOp 200n uic SWITCH ic v(4)=-0 SWITCH OPTIONS NODE ACCT SPICEOUT SWITCH tran v(4) v(10)

Appendix A3. mwSPICE listing for dual-gate switch transient analysis.

-117-