DOCSLIB.ORG

Amplifier Design in ADS

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Amplifier Design in ADS Characterization of High Power Devices A Short Course Covering Component-Level Modeling and Measurement, Circuit Design and Analysis and System Modeling Your Calibration, Measurement & Modeling Solutions Partner! Characterization of High Power Devices Abstract - Device characterization is an essential process in many aspects of research, development and testing of RF and microwave devices. In this course, we will explore various interconnected topics of device characterization that form the amplifier design flow. Topics include pulsed IV and S- parameters for compact model extraction, load pull for model validation and measurement, amplifier design and IC stability analysis, X-parameter modeling and system-level simulations. Instructors from Maury Microwave, Agilent Technologies and AMCAD Engineering will provide instruction and demonstrations. Your Calibration, Measurement & Modeling Solutions Partner! Characterization of High Power Devices Load Pull S-Parameters IV Curves Compact Models Amplifier Design Circuit Simulation Harmonic Balance Amplifier Stability X-Parameters What do they mean? Are they somehow related? Your Calibration, Measurement & Modeling Solutions Partner! System Design from Compact Models Component level Circuit level System level VNA based FET Compact Pulsed IV and RF Compact FET IC Design & load pull model Validation IC X-Parameter Simulation at measurements model extraction Stability analysis & Refinement model system level TOOLS PIV TUNERS ADS ADS ADS ADS PNA-X IVCAD PNA-X IVCAD (PNA-X) IVCAD ICCAP IVCAD STAN Your Calibration, Measurement & Modeling Solutions Partner! System Design from X-Parameters Component level Circuit level System level IC Design & IC X-Parameter Simulation at Stability analysis X-Parameters model system level load pull TOOLS TUNERS ADS ADS ADS PNA-X NVNA IVCAD (PNA-X) IVCAD STAN Your Calibration, Measurement & Modeling Solutions Partner! System Design from Measurements Component level Circuit level System level VNA based IC Design & load pull IC X-Parameter Simulation at Stability analysis model system level TOOLS TUNERS ADS ADS ADS PNA-X (or PSG/PSA) IVCAD (PNA-X) IVCAD STAN Your Calibration, Measurement & Modeling Solutions Partner! Design flow entry points Component level Circuit level System level VNA based FET Compact Pulsed IV and RF Compact FET IC Design & load pull model Validation IC X-Parameter Simulation at measurements model extraction Stability analysis & Refinement model system level VNA based IC Design & load pull IC X-Parameter Simulation at Stability analysis model system level Your Calibration, Measurement & Modeling Solutions Partner! – Instructor Introduction – Pulsed IV/RF and Compact Modeling – Load Pull – Amplifier Design in ADS – Stability Analysis – X-Parameters – System-level Simulations Your Calibration, Measurement & Modeling Solutions Partner! Instructor – Gary Simpson Gary Simpson received his Bachelor degree from DeVry Institute of Technology in 1972, and his Masters degree from Arizona State University in 1978. He has been involved with microwave measurements since 1973, starting with device characterization through manual load pull on microwave power transistors at his first job at Motorola. He has been with Maury Microwave since 1982, where he began developing components and fixtures for microwave measurements, including network analyzer calibration standards and techniques. Gary is a pioneer in device characterization systems; in 1987 he developed one of the earliest automated slide-screw tuners for advanced load pull measurements. Since then, he has been responsible for much of the on-going development of device characterization techniques, methodologies and systems. He is currently Chief Technical Officer at Maury Microwave Corp. Your Calibration, Measurement & Modeling Solutions Partner! Instructor – Tony Gasseling Tony Gasseling received his PhD from University of Limoges in 2003. The topic of his PhD was “A new characterization technique of "Four hot S parameters" for the study of nonlinear parametric behaviors of microwave components”. Throughout his education, Tony focused on advanced device characterization techniques with emphasis on transistor modeling. In 2004, with the support of the European Social Fund, he launched AMCAD Engineering, a spin-off of the XLIM Laboratory (Limoges-FRANCE). Today, AMCAD Engineering employs 10 PhDs to support a strong innovation in the field of testing solutions for RF and microwave circuits. Your Calibration, Measurement & Modeling Solutions Partner! Instructor – Stephane Dellier Stéphane Dellier received his MSc degree and PhD degree in electrical engineering from XLIM laboratory, University of Limoges, France, respectively in 2001 and 2005. His PhD research is focused on microwave circuits design. In 2004 he co-founded AMCAD Engineering, company providing new RF and microwave solutions to semiconductor professionals. He is currently project leader at AMCAD Engineering focused on the development of IVCAD software platform for characterization and modeling of RF devices. Your Calibration, Measurement & Modeling Solutions Partner! Instructor – David Ballo David Ballo is a Senior Application Engineer with 33 years of experience at Agilent Technologies’ Component Test Division in Santa Rosa, California. After graduating from the University of Washington in Seattle, he spent ten years in R&D designing analog and RF circuits for signal analyzers. Since then, he has worked on developing and presenting seminars and papers, and writing application notes and technical articles on a wide variety of network- and spectrum-analyzer measurement topics. Your Calibration, Measurement & Modeling Solutions Partner! Instructor – Al Lorona Al Lorona is an Application Engineer who helps customers use SystemVue and other Agilent Technologies EDA products more effectively and creatively. With 24 years of experience at Hewlett-Packard and Agilent he is a seasoned presenter, teacher and sales team member. Al is based in southern California. Your Calibration, Measurement & Modeling Solutions Partner! – Instructor Introduction – Pulsed IV/RF and Compact Modeling – Load Pull – Amplifier Design in ADS – Stability Analysis – X-Parameters – System-level Simulations Your Calibration, Measurement & Modeling Solutions Partner! Large-Signal Transistor Models Convergence Operating range Physic model Compact Extrapolation Physical insight model Accuracy Behavioral model Easy modeling Usability for Circuit design process Your Calibration, Measurement & Modeling Solutions Partner! Commercial compact FET models • Mostly used models for GaN HEMTs Number of Electro-thermal Trapping Original Device FET models parameters effect Effects Context Curtice3 [1] 59 No No GaAs FET CFET [2] 53 Yes No HEMT EEHEMT1 [3] 71 No No HEMT Angelov [4] 80 Yes No HEMT/MESFET AMCAD HEMT1 [5] 65 Yes Yes GaN HEMT Your Calibration, Measurement & Modeling Solutions Partner! Compact FET model extraction flow 1.6 1.18 1.4 Rd 1.16 y = 0.0049x + 0.6889 1.14 1.2 y = -0.0008x + 1.1543 1.12 1 Rs 1.1 Idss Rs, Rd Rs, 1.08 0.8 y = 0.0029x + 0.6375 1.06 0.6 1.04 0.4 1.02 0 50 100 150 200 0 50 100 150 200 T°C T°C Non-linear Thermal Trapping Small-Signal IV Model capacitances model effects Ri Dgs=f(Vgs) Dgs=f(Vgs,T) Cds Dgd=f(Vgd,T) Rg τ Dgd=f(Vgd) Lg Gm Ids=f(Vgs,Vds) Ids=f(Vgs,Vds,T) Cpg Gd Ls Cgs Cgs=f(Vgs) Ids=f(Vgs_trap,Vds,T) Cpd Cgd Cgd=f(Vgd) Ld Rgd Rs Rs=f(T) Rd Rd=f(T) Various effects are successively added Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements Short pulse : Quasi-isothermal conditions Low duty cycle : Constant mean temperature Quiescent bias point : Thermal conditions fixed Several quiescent bias point Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements • Pulsed IV measurements must be accurate from low to high voltage/current values • Accurate IV data = . Reliable current source . Transconductance . Leakage current . Ideality factor schottky diode IVCAD Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements How to get accurate pulsed IV measurements ? PIV system Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements How to get accurate pulsed IV measurements ? Gate 15 bits + sign Drain 16 bits +20V 250V 15 bits + sign 16 bits 25V -20V Pulse shape monitoring 20ns time resolution Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements How to get accurate pulsed IV measurements ? 1A 33µA 4mA AM212 1A Gate access 100mA 3,3µA 400µA 100mA 10mA 330nA 40µA 10mA 1mA 33nA 4µA 1mA 0mA -20V -2V 0V 650µV 65µV Measurement Resolution 20mV 2mV Voltage Absolute Accuracy 20V 2V Voltage Range Your Calibration, Measurement & Modeling Solutions Partner! Pulsed IV measurements How to get accurate pulsed IV measurements ? 10A AM221 200µA 20mA Drain access 1A 22µA 2mA 0A Measurement Resolution 0,53mV 4,9mV Voltage Absolute Accuracy 50mV 500mV Voltage Range 0V 25V 250V Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter measurements Pulsed S parameter measurements Bias Bias Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter measurements The first & most important point : • Pulsed S parameter measurements must not be noisy • Small S2P measurement variation = strong influence over the linear model extraction : optimization algorithm Requirements : IVCAD Dynamic range in pulsed mode > 90dB for Duty Cycle ~ 5% Your Calibration, Measurement & Modeling Solutions Partner! Pulsed S-parameter
Load more

Recommended publications
  • Bias Circuits for RF Devices
    Bias Circuits for RF Devices Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul A lot of RF schematics mention: “bias circuit not shown”; when actually one of the most critical yet often overlooked aspects in any RF circuit design is the bias network. The bias network determines the amplifier performance over temperature as well as RF drive. The DC bias condition of the RF transistors is usually established independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration. A transistor amplifier must possess a DC biasing circuit for a couple of reasons. • We would require two separate voltage supplies to furnish the desired class of bias for both the emitter-collector and the emitter-base voltages. • This is in fact still done in certain applications, but biasing was invented so that these separate voltages could be obtained from but a single supply. • Transistors are remarkably temperature sensitive, inviting a condition called thermal runaway. Thermal runaway will rapidly destroy a bipolar transistor, as collector current quickly and uncontrollably increases to damaging levels as the temperature rises, unless the amplifier is temperature stabilized to nullify this effect. Amplifier Bias Classes of Operation Special classes of amplifier bias levels are utilized to achieve different objectives, each with its own distinct advantages and disadvantages. The most prevalent classes of bias operation are Class A, AB, B, and C. All of these classes use circuit components to bias the transistor at a different DC operating current, or “ICQ”. When a BJT does not have an A.C.
    [Show full text]
  • The Bipolar Junction Transistor (BJT)
    The Bipolar Junction Transistor (BJT) Introduction he transistor, derived from transfer resistor, is a three terminal device whose resistance between two terminals is controlled by the third. The term bipolar reflects the fact that T there are two types of carriers, holes and electrons which form the currents in the transistor. If only one carrier is employed (electron or hole), it is considered a unipolar device like field effect transistor (FET). The transistor is constructed with three doped semiconductor regions separated by two pn junctions. The three regions are called Emitter (E), Base (B), and Collector (C). Physical representations of the two types of BJTs are shown in Figure (1–1). One type consists of two n -regions separated by a p-region (npn), and the other type consists of two p-regions separated by an n- region (pnp). Figure (1-1) Transistor Basic Structure The outer layers have widths much greater than the sandwiched p– or n–type layer. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity of the base (increases the resistance) due to the limited number of “free” carriers. Figure (1-2) shows the schematic symbols for the npn and pnp transistors 1 College of Electronics Engineering - Communication Engineering Dept. Figure (1-2) standard transistor symbol Transistor operation Objective: understanding the basic operation of the transistor and its naming In order for the transistor to operate properly as an amplifier, the two pn junctions must be correctly biased with external voltages.
    [Show full text]
  • FET) Field Effect Transistor Projects
    50 (FET) Field Effect Transistor Projects F. G. RAYER, T. ENG. (CEI), ASSOC. IERE 50 (F.E.T.) Field Effect Transistor Projects by F. G. RAYER, T. Eng. (CEI), Assoc. IERE BABANI PRESS The Publishing Division of Babani Trading and Finance Co. Ltd. The Grampians Shepherds Bush Road London W6 7NF England INTRODUCTION Field effect transistors find application in a wide variety of cir- cuits. The projects described here include radio frequency am- plifiers and converters, test equipment and receiver aids, tuners, receivers, mixers and tone controls, as well as various miscella- neous devices which are useful in the home. It will be found that in general the actual FET used is not criti- cal, and many suitable types will perform satisfactorily. The FET is a low noise, high gain device with many uses, and the dual gate FET is of particular utility for mixer and other applications. This book should be found to contain something of particular interest for every class of enthusiast - short wave-listener, radio amateur, experimenter, or audio devotee. FET Operation Figure 1 will help clarify the working of the field effect transis- tor. “A” represents the essential elements of the device, which has Source lead 5, Gate lead G, and Drain connection D. The path for current is from Source to Drain through the semiconduc- tor material, this path being termed the channel. With the N-chan- nel FET, the carriers are electrons. The Source is connected to negative of the supply, and Drain to positive. P-type gates are formed on the N-type channel, providing PN junctions.
    [Show full text]
  • THE DESIGN, SIMULATION and FABRICATION of a GALLIUM ARSENIDE MONOLITHIC SAMPLE and HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. Mcgi
    THE DESIGN, SIMULATION AND FABRICATION OF A GALLIUM ARSENIDE MONOLITHIC SAMPLE AND HOLD CIRCUIT by WILLEM G. DURTLER B.Eng. McGill University A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June 1986 © Willem G. Durtler 1986 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of ELECTRICAL ENGINEERING The .University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 1986 06 12 ABSTRACT This thesis describes work done towards the development of a gallium arsenide monolithic sample-and-hold circuit. The literature relevant to high-speed electronic sampling is reviewed, and the different types of high• speed sampling circuits are discussed. The requirements of a sampling circuit for use in a distributed sampling amplifier are analyzed, and it is found that the most important requirement is a high input impedance. A circuit suitable for monolithic integration is designed and analyzed using the computer program mwSPICE. The different fabrication technologies for gallium arsenide integrated circuits are discussed, with emphasis on the self-aligned gate technologies, which can give reduced parasitic source and drain resistances.
    [Show full text]
  • Low Cost Field Effect Transistor Measurements and Applications
    Calhoun: The NPS Institutional Archive Theses and Dissertations Thesis Collection 1967-09 Low cost field effect transistor measurements and applications Holt, Ben Ford Monterey, California. U.S. Naval Postgraduate School http://hdl.handle.net/10945/12569 N PS ARCHIVE 1967 HHSSBBG™ HOLT, B. mammHI "•KMin «H WW RUSH 3W COST FIELD EFFECT TRANSISTOR :••';•'.••;. '•..','. •'•;• ."'•• • v ; i ' * • ' HOLT, JfL .'-.•' 5 Met V p- 3 LOW COST FIELD EFFECT TRANSISTOR MEASUREMENTS AND APPLICATIONS by Ben Ford Holt, Jr. Lieutenant, United States Navy B.S., Naval Academy, 1959 Submitted in partial fulfillment of the requirements for the degree of MA.STER OF SCIENCE IN ENGINEERING ELECTRONICS from the NAVAL POSTGRADUATE SCHOOL September, 1967 KcTT DU \, C>, ABSTRACT The field effect transistor (FET) has emerged as an important active device. Low cost FETs (about one dollar) are now available which should substantially enlarge the FET market. Measurements on and applications of various low cost FETs are discussed pointing out advantages and disadvantages of particular devices and circuits. Basic FET operation and terminology is discussed including the specification sheet, DC biasing, small signal representation^ and measurements of device parameters. Mixer, tuned amplifier, oscillator, and detector circuits were constructed and tested. Low noise character- istics are examined and a brief treatment of other applications is given. LIBRAKY NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIF. 93940 TABLE OF CONTENTS Section Page 1. Introduction 11 2. Basic FET Operation and Terminology 12 3. The Specification Sheet 16 4. Direct Current Biasing 19 5. Small Signal Representation 24 6. Basic Measurements 27 7. The FET Mixer 34 8. Design of a 5 MHz Tuned Amplifier 42 9.
    [Show full text]
  • An L-Band Stacked SOI CMOS Amplifier
    ISSN: 1226-7244 (Print) ISSN: 2288-243X (Online) j.inst.Korean.electr.electron.eng.Vol.20,No.3,279∼284,September 2016 논문번호 16-03-10 http://dx.doi.org/10.7471/ikeee.2016.20.3.279 71 An L-band Stacked SOI CMOS Amplifier ★ Young-Gi Kim* , Jae-Yeon Hwang* Abstract This paper presents a two stage L-band power amplifier realized with a 0.32 μm Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a 0.32 μm Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply.
    [Show full text]
  • Project 15 MOSFET Amplifiers with Current Source Biasing
    Electronics Laboratory Project 15 - MOSFET Amps with CS (FET) - 1 Project 15 MOSFET Amplifiers with Current Source Biasing Objective: This project will focus on the use of FET current mirrors to provide the DC biasing for Common Source and Common Drain amplifiers, two of the primary FET amplifier stages. The design of each amplifier type (CS and CD) to achieve a specific design goal using current biasing will be examined. The frequency response and feedback adjustments will also be investigated. Components: 2N7000 FET Introduction: One of the primary differences between discrete and integrated amplifier design, as mentioned in Project 11, is the use of biasing resistors. The savings in “semiconductor real estate” is even more dramatic when the resistor area is compared to that of the active FETs. The ability to easily change the W/L ratios for the FETs used in the current source (see project 13 for additional discussion) provides great flexibility in selecting the size of the required power supply(ies) as well as in the value of the load currents. As in most semiconductor device fabrication, “exact” parameter values are difficult and expensive to obtain while matched device parameters are basically a “side effect” of the overall process. This “side effect” makes FET based current sources well suited for integrated circuits since the FETs are used for the entire source. This project will examine the use of an FET current mirror, as discussed in Project 13, to provide the DC bias for a Common Source and a Common Drain amplifier. The actual AC amplifier analysis and design is the same for both discrete and integrated circuits once the related changes due to the new biasing network have been incorporated.
    [Show full text]
  • WIDE BAND GAP SEMICONDUCTOR TECHNOLOGY (Sic Mesfets and Gan Hemts) and THEIR RESPONSE in DIFFERENT CLASSES of POWER AMPLIFIERS
    Linköping Studies in Science and Technology Thesis No. 1374 Wide Bandgap Semiconductor (SiC & GaN) Power Amplifiers in Different Classes S h e r A z a m LIU-TEK-LIC-2008:32 Material Science Division Department of Physics, Chemistry and Biology Linköpings universitet, SE-581 83 Linköping, Sweden Linköping 2008 LIU-TEK-LIC-2008:32 ISBN: 978-91-7393-855-6 ISSN: 0280-7971 http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11786 Printed by Liutryck, Linköping, Sweden To my Parents, family and all those who pray for the successful completion of this research work ACKNOWLEDGMENTS All praise is due to our God (ALLAH) who enabled me to do this research work. I’m deeply indebted to my supervisor, Docent Qamar ul Wahab, for his guidance and encouragement during this research work. He introduced me to the most experienced and pronounced researchers of professional world, like my co-supervisor Professor Christer Sevensson, department of electrical engineering (ISY) and Mr. Rolf Jonsson, sensor group (previous Microwave Technology group) at Swedish Defence Research Agency (FOI). I am thankful to them for useful recommendations, excellent guidance and giving me fantastic feedback. I would say I was lucky to meet people like them, who advice and assistance me during my work. I acknowledge FOI for technical and financial support in this work. I also acknowledge Mr. Stig Leijon at FOI, for manufacturing amplifiers and help with the development of the measurement fixtures. Of course I cannot forget my colleagues at Material Science Division and Eva Wibom for the help in administrative work.
    [Show full text]
  • Stacked-FET Based Gaas Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends
    Stacked-FET based GaAs Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends Gijsbert van der Bent PROMOTIECOMMISSIE: Voorzitter/secretaris prof. dr. J.N. Kok Universiteit Twente Promotor prof. dr. ir. F.E. van Vliet Universiteit Twente Referent dr. ir. W.J.A de Heij Thales Netherlands Leden prof. dr. ir. B. Nauta Universiteit Twente prof. dr. A.A. Stoorvogel Universiteit Twente prof. S. Mahon Macquarie University prof. dr. D.M.W. Leenaerts Technische Universiteit Eindhoven The work presented in this thesis has been supported by the Dutch Radar Centre of Expertise (D-RACE), a strategic alliance of Thales Netherlands and TNO. Cover: Ilse Modder, www.ilsemodder.nl Printed by Gildeprint Drukkerijen. ISBN: 978-90-365-4766-6 DOI: 10.3990/1.9789036547666 Copyright © 2019 by Gijsbert van der Bent All rights reserved. No parts of this thesis may be reproduced, stored in a retrieval system or transmitted in any form or by any means without permission of the author. Alle rechten voorbehouden. Niets uit deze uitgave mag worden vermenigvuldigd, in enige vorm of op enige wijze, zonder voorafgaande schriftelijke toestemming van de auteur. Stacked-FET based GaAs Monolithic Microwave High-Power Amplifiers for Active Electronically Scanned Array Radar Front-Ends PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. T.T.M. Palstra, volgens besluit van het College voor Promoties in het openbaar te verdedigen op vrijdag 3 mei 2019 om 16:45 uur door Gijsbert van der Bent geboren op 11 februari 1975 te Leiden Dit proefschrift is goedgekeurd door: De promotor: prof.
    [Show full text]
  • Designing with Field-Effect Transistors
    DESIGNING WITH FIELD-EFFECT TRANSISTORS DESIGNING WITH FIELD-EFFECT TRA~SISTORS SILICONIX INC. Editor in Chief Arthur D. Evans McGRAW-HILL BOOK COMPANY New York St. Louis San Francisco Auckland Bogota Hamburg Johannesburg London Madrid Mexico Montreal New Delhi Panama Paris Sao Paulo Singapore Sydney Tokyo Toronto Library of Congress Cataloging in Publication Data Siliconix Incorporated. Designing with field-effect transistors. Includes index. 1. Field-effect transistors. 2. Transistor cir­ cuits. 3. Electronic circuit design. I. Evans, Arthur D. II. Title. TK7871.95.S54 1981 621.3815'284 80-15690 ISBN 0-07-057449-9 Copyright ® 1981 by McGraw-Hill, Inc. All rights reserved. Printed in the United States of America. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. 567890 KPKP 89876543 The editors for this book were Tyler G. Hicks and Geraldine Fahey, the designer was Elliot Epstein, and the production supervisor was Sally Fliess. It was set in Baskerville by The Kingsport Press. Printed and bound by The Kingsport Press. CONTENTS Preface lX 1 FIELD-EFFECf TRANSISTOR THEORY 1 2 PARAMETERS AND SPECIFICATIONS 25 3 LOW-FREQUENCY CIRCUITS 61 4 HIGH-FREQUENCY CIRCUITS 137 5 ANALOG SWITCHES 193 6 VOLTAGE-CONTROLLED RESISTORS AND FET CURRENT SOURCES 233 7 POWERFETs 255 8 FETs IN INTEGRATED CIRCUITS 281 INDEX 289 v I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I CONTRIBUTORS Written by the Applications Engineering Staff of Siliconix Incorporated Editor in Chief ARTHUR D.
    [Show full text]
  • Theory and Applications of Field-Effect Transistors
    "HEORY AND APPLICATIONS ^^ FIELD-L""7~^CT TPJ\NSlf""70"\r by /&? COE WILLAP.D TOLIVER 3. S., Prairie View as: College, 1952 A MASTER'S REPORT sv-bnitted in partial fulfillment of requirements for the FAST"?. 0? SCIENCE Department of Electrical Engineering KANSAS STATS UNIVE"^T '" Manhattan, Kansas 19S7 Approved by: ] 2 i Major Professor / LU Hi " CONTENTS Page INTRODUCTION 1 CONSTRUCTION OF FIELD-EFFECT TRANSISTORS 4 THE FIELD-EFFECT TRANSISTOR 7 FIELD-EFFECT TRANSISTOR THEORY 10 The Conductive Channel 11 Depletion Layer Potential 13 Channel Current 17 Characteristics of Field-effect Transistors 21 Mutual Transconductance 22 Determining the Field-effect Transistor Pinch-off Voltage 26 Temperature Dependence of I 2 8 BIASING FIELD-EFFECT TRANSISTORS 30 SELECTING THE 3S~T FIELD-EFFECT TRANSISTOR 36 tCUIT DESIGN 3 8 SMALL-SIGNAL LOW FREQUENCY-PROPERTIES 41 SMALL-SIGNAL EQUIVALENT CIRCUIT 45 FIELD EFFECT TRANSISTOR AMPLIFIERS 49 Basic FET Amplifier Configurations 49 Voltage Amplifier Circuit 50 The Source-follov;er Circuit 51 FET Cascade with 3ipolar Transistor 53 THE POWER FIELD-EFFECT TRANSISTOR 59 CONCLUSIONS 61 Ill Page REFERENCES 64 ACKNOWLEDGEMENT 66 LIST OF PRINCIPAL SYMBOLS 67 . INTRODUCTION In 1952, shortly after the invention of the junction transistor, Shockley (18) described theoretically a new active device based on the modulation of a majority-carrier current. The principle of operation of this device, which he termed a unipolar field-effect transistor, is radically different from that of the junction transistor in that the majority - rather than minority-carrier current is modulated by altering the width of a conducting channel through the narrowing or widen- ing of a p-n junction depletion layer.
    [Show full text]
  • Chapter 8:Field Effect Transistors (FET's)
    Chapter 8:Field Effect Transistors (FET’s) The FET The idea for a field-effect transistor (FET) was first proposed by Julius Lilienthal, a physicist and inventor. In 1930 he was granted a U.S. patent for the device. His ideas were later refined and developed into the FET. Materials were not available at the time to build his device. A practical FET was not constructed until the 1950’s. Today FETs are the most widely used components in integrated circuits. 1 8-1: The Junction Field Effect Transistor (JFET) Basic Structure The JFET ( junction field-effect transistor) is a type of FET that operates with a reverse-biased pn junction to control current in a channel. JFETs has two categories, n channel or p channel. For n-channel JFET shown; the drain (D) is at the upper end, and the source (D) is at the lower end. Two p-type regions are diffused in the n-type material to form a channel, and both p-type regions are connected to the gate (G) lead. for p-channel, the gate is connected to n-type regions forming basic structure of the two the channel into the p-type material types of JFET. 8-1: The Junction Field Effect Transistor (JFET) Basic Operation Biasing of JFET is shown in the figure VDD provide drain-to-source voltage Æ current flow from drain to source VGG sets the reverse bias between the gate and the source Æ sets the depletion region along the pn junction Æ restricting channel width Æ increase channel resistance 2 8-1: The Junction Field Effect Transistor (JFET) Basic Operation Depletion region By varying the gate voltage (VGG) Æincreasing –ve voltage between G and S Æ varying the channel width Æ controlling the amount of drain current (ID); As VGG increase Æ depletion region increase Æ channel decrease Æ higher resistance Æ lower current The schematic symbols for both n-channel and p-channel JFETs are shown in the adjacent figure; the arrow on the gate points “in” for n channel and “out” for p channel.
    [Show full text]