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Photonic Crystal Microcavities in a Microelectronics 45 Nm SOI CMOS Technology Christopher V

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Photonic Crystal Microcavities in a Microelectronics 45 Nm SOI CMOS Technology Christopher V This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LPT.2015.2389840, IEEE Photonics Technology Letters IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. X, NO. Y, OCTOBER Z, 2014 1 Photonic Crystal Microcavities in a Microelectronics 45 nm SOI CMOS Technology Christopher V. Poulton, Xiaoge Zeng, Mark T. Wade, Jeffrey M. Shainline, Jason S. Orcutt and Milosˇ A. Popovic´ Abstract—We demonstrate the first monolithically integrated art microelectronics, may impact the commercial viability of linear photonic crystal microcavities in an advanced silicon- electronic-photonic systems in a number of applications. on-insulator (SOI) complementary metal-oxide-semiconductor We demonstrate efficient linear photonic crystal cavities in (CMOS) microelectronics process (IBM 45 nm 12SOI) with no in- foundry process modifications and a single post-processing step. a state-of-the-art microelectronics CMOS process – a silicon- The cavities were integrated into a standard microelectronics on-insulator (SOI) CMOS transistor process – implemented design flow meeting process design rules, and fabricated alongside in the transistor device body layer. We demonstrate 1520 nm transistors native to the process. We demonstrate both 1520 nm design devices with a loaded quality factor of 2,150 (92 and 1180 nm wavelength cavity designs using different cavity GHz bandwidth), and extract an intrinsic quality factor on the implementations due to design rule constraints. For the 1520 nm and 1180 nm designs, loaded quality factors of 2,000 and 4,000 are order of 100,000. Cavities with a 1180 nm resonant design measured, and intrinsic quality factors of 100,000 and 60,000 are wavelength with an extracted intrinsic quality factor on the extracted. We also demonstrate an evanescent coupling geometry order 60,000 are also presented. All cavities are excited via that decouples the cavity and waveguide-coupling design. evanescent coupling [8], enabling decoupled design of the Index Terms—Photonic crystals, electronic-photonic integra- microcavity and waveguide coupling [Fig. 1(a)]. tion, zero-change microelectronics CMOS. II. ADVANCED CMOS DESIGN CONSIDERATIONS I. INTRODUCTION We employ the IBM 45 nm 12SOI process [9] to fabricate NERGY efficiency and bandwidth density requirements the devices. Recent work has demonstrated linear PhC cavities E in future CPU-to-memory interconnects have motivated in a bulk silicon (polycrystalline transistor-gate device layer) research into monolithic integration of photonics with micro- process [10], which is also promising for CMOS integration. electronics [1]. Recent design techniques have enabled pho- An advantage of an SOI CMOS process, in comparison to tonic devices to be manufactured within standard process de- bulk CMOS, is the low optical loss of the crystalline silicon sign kit (PDK) guidelines in advanced complementary metal- transistor body layer when used as the waveguiding layer. oxide-semiconductor (CMOS) processes and to be fabricated The cross-section of the cavity within the 12SOI process is without requiring any in-foundry process modifications [2]– illustrated in Fig. 1(b) (exact layer thicknesses available in [4]. Thus, photonics is enabled in native microelectronics fab- IBM 12SOI Process Design Kit under NDA [9]), showing the rication processes, enabling photonics technology to leverage body silicon layer waveguide, and a nitride stressor layer above the advances in CMOS technology fabrication at essentially it (present in advanced-node processes to increase mobility no cost. Nanostructured devices such as photonic crystals in the metal-oxide-semiconductor field-effect transistor (MOS- (PhCs) require high resolution and low proximity effects, FET) channel region). The buried oxide is not thick enough which turned previous research in favor of electron beam to enable optical isolation between the waveguides and the lithography [5] over photolithography, but this approach is not silicon substrate. Thus, a post-processing XeF2 silicon etch viable for high-volume production. Modern microelectronics step is required to remove the silicon substrate. The substrate CMOS processes, such as the 45 nm process used in this work, removal can be performed locally [11] or globally [2], and support the resolution and process control to define PhCs and it was previously shown that the substrate removal does not provide a scalable solution for mass manufacturing. However, degrade transistor performance [3]. The experiments in this they are entirely optimized for electronic circuits with no pro- work utilized global substrate removal. A micrograph image vision for photonics. PhC microcavities are potential building of a PhC after substrate removal is shown in Fig. 2(c). blocks for efficient filtering, tuning, modulation, all-optical The primary challenges in design are the sub-90 nm thick- switching and nonlinear applications [6], [7]. Therefore, their ness of the body silicon layer that limits confinement, and direct integration into advanced CMOS, alongside state-of-the- process design rules including minimum feature size, enclosed area and notch width rules. Because of the thin body silicon Manuscript revised January 6, 2015. layer, the cavity waveguide width is large relative to that of C.V. Poulton, X. Zeng, J.M. Shainline, M.T. Wade and M.A. Popovic´ typical silicon designs [5] in order to maximize confinement are with the Department of Electrical, Computer and Energy Engineer- [Fig. 1(c)], and the cavity is also longer to support a high ing, University of Colorado, Boulder, CO 80309, USA (e-mail: cvpoul- [email protected]; [email protected]; [email protected]; intrinsic quality factor. Although the polysilicon gate layer [email protected]; [email protected]). could be utilized on top of the crystalline silicon body layer J.S. Orcutt is with the Research Laboratory of Electronics, Mas- to increase confinement [4], it is omitted here because its sachusetts Institute of Technology, Cambridge, MA 02139, USA (email: [email protected]). substantial optical loss would degrade the intrinsic quality Copyright (c) 2014 IEEE factor. In order to pass to the fabrication stage within a 1041-1135 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LPT.2015.2389840, IEEE Photonics Technology Letters IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. X, NO. Y, OCTOBER Z, 2014 2 (a) Cavity B B’ (b) (a) Simulated Resonance Wavelength 1600 +10nm B’ SiO2 (PSG) 1580 B Nominal Si3N4 1560 -10nm 1540 Input D Output coupler coupler c-Si 1520 Wavelength [nm] 1500 1 2 3 4 5 Air SiO 2 (b) Simulated Intrinsic Q 500nm 106 i +10nm (c) D’ 105 Nominal λ = 1520nm 400nm -10nm 430nm 600nm 1µm 104 3 Quality Factor 10 1 2 3 4 5 258nm 320nm (c) Mode Number (d) 1mm Mode 1 D’ drop port 20µm drop port D 5µm D’ Mode 3 input through port D 5µm Fig. 2. (a) Simulated resonance wavelengths of the 1520 nm cavity for the (e) nominal design and ±10 nm hole size design variants; (b) simulated intrinsic λ = 1180nm 400nm loss Qi’s; (c) optical micrographs of the 3×3 mm chip and of a fabricated 350nm 380nm 500nm device including grating coupler ports, waveguides and a cavity. optical potential [12]. In contrast to analytic approximations 198nm 136nm typically used, we employed a synthesis procedure that relies (f) Mode 1 on a parameter map obtained from rigorous three-dimensional (3-D) numerical band-structure calculations. High-Frequency 5µm Structure Solver (HFSS) [13] was used for photonics simu- Mode 3 lations. First, it was used in eigensolver configuration with periodic longitudinal boundary conditions to compute the 5µm photonic band structure. This provided the mirror strength of the cavity unit cells at a target resonance wavelength as a Fig. 1. (a) Device geometry showing the photonic crystal cavity and evanes- function of a unit cell geometry parameter, such as the size cently coupled input and output waveguides; (b) waveguide cross-section in of the square holes or rectangular blocks. A cavity design the IBM 45 nm 12SOI CMOS process showing the fundamental transverse- electric (TE) mode (transverse-magnetic (TM) modes not supported); (c) (with a non-uniform cell distribution) was synthesized from the 1520 nm device design with (d) first and third longitudinal modes; (e) 1180 nm parameter maps. HFSS was used to find the fundamental and device design (unit cell difference due to design rules) with (e) first and (f) higher-order modes of the full cavity to verify the synthesis third longitudinal modes. procedure, and to analyze effects of fabrication variations. The synthesized 1520 nm design cavity has a single transverse standard microelectronics process, these structures must pass mode and multiple longitudinal modes [Fig. 1(d)], and the automatic design rule checks (DRC) provided for the process. simulated free spectral range (FSR) is 1.71 THz. Fig. 2(a) Unit cells with discretized circular holes are prone to violation shows the simulated resonant wavelength for each mode and of notch design rules. As a result, the 1520 nm resonant Fig. 2(b) shows the simulated intrinsic quality factors, Qi. cavities presented here use square holes in silicon as the unit The fundamental mode of the nominal design has a simulated cells to simplify layout and DRC conformance. The 12SOI Qi of 184,000 at 1521 nm. Qi decreases exponentially with process has a relatively large minimum enclosed area rule that mode number because the cavity length is fixed, the higher- places a strong constraint on the cavity design. Therefore, in order longitudinal modes occupy a larger portion of the cavity, cavities designed for 1180 nm wavelength, an alternative unit which results in scattering due to the finite extent of the cavity.
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