DOCSLIB.ORG

Transforming Education for a World of Opportunity Competitions For

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Transforming Education for a World of Opportunity Competitions For University of Michigan AIChE February 2, 2012 This Week’s Speakers: Intel Energy-Efficient Computing Intel helps drive best sustainable business practices for energy-conscious manufacturing Technology innovation and sustainable business practices help us create products Transforming Education for a World of that are more energy efficient and have a Opportunity smaller ecological footprint than previous generations, while maintaining the highest With over 200 programs in more than 70 countries, Intel works with and supports standards for our microprocessors. governments, NGO’s and communities to achieve Energy-efficient performance educational reform that enables children to excel in the global economy. Our processors are designed to help support the effort to minimize the world’s concerns Competitions for Inspiring Innovators and with the environmental impact of Entrepreneurs Information and Communication Today's students are innovators of tomorrow. Technology (ICT). We’re helping businesses Find out how we enable the next generation of assess how IT can reduce CO2 emissions scientists, engineers, and entrepreneurs through across the global economy. competitions. EDUCATION Technology for Advancing Education We're using technology to enhance learning Intel is helping to transform the lives of environments. See how Intel helps improve millions through education. For over a education worldwide with advanced technology, decade, we've been working with countries, Internet access, and digital content. communities, and schools worldwide to bring the resources and solutions needed Programs for Improving Teaching and for advancing education. We collaborate Learning with governments, policy-makers, and local Intel works directly with students, teachers, and vendors to turn their vision into reality. universities to enable tomorrow’s innovators. Technology that brings quality education to Learn about our worldwide education programs. more people, while sustaining local communities and economies—that's our unwavering commitment. We’re on the web! Announcements http://www.engin.umich.edu/societies/aiche/AIChE/Home.html AIChE Duess To join AIChE this semester: Semester without luncheons - $10 ($15 if not a national member) One semester with luncheon - $25 ($30 if not a national member) Join the National AIChE Why register to be a National AIChE Scan the above image with your i-thing/device member? It’s easy, free, and they send to view our Facebook page for event updates and reminders!!! How easy is that?! you a pen in the mail. Here are the quick and easy steps: AICHE Happy Hour rd 1) Go to www.aiche.org/scaleup When : Friday February 3 4:00-6:00pm Where: Good Time Charlie’s 2) Click Apply Online 3) Enter your info Grab some free appetizers and meet with other 4) Click Join! AICHE members and mentors! You don’t need to If you joined last year, don’t forget to be 21 to attend! renew your membership this year! Novellus Info Session th Mentorship program: Sophomores who When: Monday February 6 6:00-7:00pm do not already have an AIChE mentor may Where: 1013 Dow Find what Novellus has to offer! request one at [email protected]. We will soon be planning a number of great Join The AICHE IM Broomball Team mentorship events, just in time for career When: Thursdays at 11:20 Where: Yost Ice Arena fair. You MUST register to be on the AIChE team by NOON on game day (T hursday, if you want to play the first game) on the Athleague website. You If you have any suggestions for only need to register once. food, email Christine at [email protected]! Bridging the Memory Gap If you know what mercury delay lines are you either have diligently studied computer history or have a good “memory." Mercury delay lines were used in early digital computers as memory to store program and data. It is slow. The processor must sit idle and wait for the instruction or data to come around to be used. Thus from the very beginning of the digital computer era, there existed a discrepancy between the logic speed and the memory response time. This discrepancy is called the memory gap. Technologists and researchers have spent much effort to find better memory technologies that can match up to the speed of the logic processor. After mercury delay line memory, a few technologies were invented and used such as CRT (Williams Tubes) memory and core memory . They were faster than mercury delay lines but were still slow in comparison with logic. By the late sixties and early seventies semiconductor memories were beginning to appear. Dynamic Random Access Memory (DRAM) was invented in 1967 and represented grea t progress in density and access time. Even though it did not result in memory performance catching up fully with processor performance, it came pretty close. There was hope that from then on memories and processors would benefit from the same semiconducto r technology advancement and would scale together in performance. Unfortunately this did not happen as planned. This was because of significant divergences between the semiconductor technology used for DRAM memories and the technology used for digital logic circuits. Since the eighties, the performance gap between memory and processor has started to widen again. While the microprocessor performance increased at the rate of roughly 50% per year, the speed of DRAM memory improved at a rate of only 7% per year. Processor architecture began to advance on several fronts to compensate for the growing gap. Advances on one front attempted to reduce the memory access latency via caching. Caching is a very effective scheme to bring down the average memory access latency because memory access patterns exhibit spatial and temporal localities. Most of the time, an access to data or instruction hits the cache and results in a very short delay only. Advances in architecture also worked to better tolerate memory latency through methods like out of order execution. Out of order execution allows other instructions that are not blocked by the memory access to continue to execute, thus allowing the processor to bypass any data resolution delays. Unfortunately these architectural techniques require the implementation of more complex logic circuitry, causing power consumption to increase, and this has led us to a point where the return on investment of these complex techniques is diminishing. Moreover, memory has been aiming at density reduction only. There have been few corresponding architectural techniques to improve performance on the memory side. Besides performance, power consumption is becoming a very important criterion for system design. High power consumption complicate d the thermal solution and increases the operation cost of a computer system. We must include the operational cost into the total cost of the computer and not just the system hardware cost. Today, it is estimated that memory accounts for 20 to 40 percent of a computer system’s total power. The proportion is increasing as the density and performance requirements of DRAM increase. One example is the over-fetching incurred due to the way current DRAM die is organized. It activates thousands of bits with each request, but only returns a small number of data bits to the processor. This is rather inefficient. Another example of the DRAM energy inefficiency comes from the fact that DRAM dies are put together on a DIMM and multiple DIMMs may share a channel to communicate with the processor. A single request must activate multiple dies and drive more than one load. Moreover, DRAM also needs to be refreshed periodically to ensure that data is retained in the memory deviecs. The DRAM consumes power even though there is no actual data activity. This is bad for laptop, tablet and handheld platforms because users want instant on from standby and for standby to last for multiple days between charges. We are starting a memory research project with the Industrial Technology Research Institute (ITRI) of Taiwan to address the performance gap and to reduce the power consumption of memory. Novel techniques are being investigated to extend DRAM refresh time to reduce standby power. We are also looking into using an extra (vertical) dimension to help reduce the physical distance between data transfers to save even more energy. Allowing DRAM dies to stack on each other opens up many new opportunities for architectural improvement. We will build models and utilize simulation to explore the design space holistically to find the highest performance, lowest power solution possible. A prototype is planned as well to demonstrate our research results. Making the Memory more power efficient and faster is a challenging task. This challenge has existed since the dawn of digital computer, and it is growing. If we don’t do anything it will severely impede the further advancement of computing systems. It is exciting to work on a difficult and important problem! Source: Shih-Lien Lu, Intel Labs Sr. Principal Engineer, Monday, December 5th, 2011: http://techresearch.intel.com/newsdetail.aspx?Id=34 ChemE of the Week Avi Wolf What are you hobbies/ favorite sport? Fill in the bubbles with the numbers 1-5 so I love playing tennis, but my favorite sport to watch is football with the NY Giants. I may even head to Indianapolis for the super bowl just for that every row, column, and strand has the the atmosphere... let me know if you're going so we can car pool! numbers 1-5. What is your favorite engineering class? Dare I say ChE 487, Senior Design? It's not just a rite of passage which we all must endure, but it's one that we only share with each other. I find others just don't fathom or understand our experiences there. What is your favorite non-engineer class? I know you all are thinking I'm going to say Orgo I, but I've had better: a class in Leadership in the ROTC program.
Load more

Recommended publications
  • DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA
    Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_
    [Show full text]
  • Metal Ultrasonic Delay Lines
    Research Paper 2453 rOOmOI of R~eo"h of The NO tiO ~;;:if ~;=asoni;l~~i~;~~~:: Russell W . Mebs, John H. Darr, and John D. Grimsley A study was made of the applicability of a number of metals and a lloys for therm all y stable ultrasonic delay lin es. A preliminary iavestigation was made of different types of pressure holders and ad­ hesi ves for use in crystal t ransducer attachments and of the iafluence of specimen length on attenuation for valious m etals and alloy. The effect of cold-work, annealing, and specimen cross section on attenuation was a lso determined for a representati ve isoelastic alloy. Measurements of temperature variation of signal attenuation, distort ion, a nd delay t im e on a number of assembled delay lines indicated t hat an isoelastic a lloy employing over cured epoxy-resin crystal attachments gave best over-all t ransmission characteristics. No correlation was obtainable between strength and SOLl nd-transmission characteristics with varioLls cemented joints. 1. Introduction variations in pulse attenuation and distortion with acceleration or change of temperature. The ultrasonic delay line has come into wide use Only a general survey will be given of the basic in recent years with the development of radar, com­ theory of ultrasonic transmission as related to delay ~uters , and other electronic devices [1 , 2, 3, 4V It lines of 50 tLsec or less. More comprehensive 's a means for delaying a signal for a predetermined treatments have been given elsewhere [2, 4, and 5]. ~hort period to be accurately reproduced for use at _tn appropriate later instant.
    [Show full text]
  • History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch Cards - Herman Hollerith (Of IBM Forerunner) Invented "IBM" Punch Cards to Be Used for the 1890 Census
    Computer Memory History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch cards - Herman Hollerith (of IBM forerunner) invented "IBM" punch cards to be used for the 1890 census. 1932 - Drum memory 1947 - Delay line memory 1949 - Magnetic CORE memory 1950 - Magnetic TAPE memory 1955 - Magnetic DISK memory - IBM RAMAC was first one 1957 - Plated wire memory 1962 - Thin film memory 1968 (ca) - Paper tape - Had beginnings dating back to 1846, but became widely used with teletype machines such as the Teletype Model 33 ASR, which were adopted early on by minicomputers as a primitive terminal. 1970 - Bubble memory 1970 - DRAM - Invented by Intel, first device was the 1101, organized as 256x1, followed by the 4x larger (1024x1) 1103(A) -- regarded as the world's first commercial DRAM (intro in October 1970). 1971 - Bipolar SRAM - Fairchild 256x1 (note IBM made a 16-bit SRAM in late 1960s. AMD made a second source of a 64x1 SRAM by Fairchild in 1971.) 1971 - EPROM - Invented by Dov Frohman of Intel as the i1702, a 2K-bit (256x8) EPROM. 1971 - "Floppy" disks -- First were 8-inch, hence very flexible ("floppy"). The 8" became commercially available in 1971. 1973 (ca) - Magnetic TAPE CASSETTE memory 1976 - Shugart Associates introduced the first 5¼-inch floppy (flexible) disk drive 1977 - EEPROM - invented by Eli Harari at Hughes - a BYTE erasable device 1979 - CMOS SRAM (static RAM, 4T/6T cell, implemented as a latch) - first introduced by HP then its spinoff as Integrated Device Technology. I believe first devices were 1K (1024x1), and later organized as x4 then x8.
    [Show full text]
  • The Graphic Display of Computer Memory Data
    University of Windsor Scholarship at UWindsor Electronic Theses and Dissertations Theses, Dissertations, and Major Papers 7-21-1969 The graphic display of computer memory data. Satish P. Agrawal University of Windsor Follow this and additional works at: https://scholar.uwindsor.ca/etd Recommended Citation Agrawal, Satish P., "The graphic display of computer memory data." (1969). Electronic Theses and Dissertations. 6548. https://scholar.uwindsor.ca/etd/6548 This online database contains the full-text of PhD dissertations and Masters’ theses of University of Windsor students from 1954 forward. These documents are made available for personal study and research purposes only, in accordance with the Canadian Copyright Act and the Creative Commons license—CC BY-NC-ND (Attribution, Non-Commercial, No Derivative Works). Under this license, works must always be attributed to the copyright holder (original author), cannot be used for any commercial purposes, and may not be altered. Any other use would require the permission of the copyright holder. Students may inquire about withdrawing their dissertation and/or thesis from this database. For additional inquiries, please contact the repository administrator via email ([email protected]) or by telephone at 519-253-3000ext. 3208. INFORMATION TO USERS This manuscript has been reproduced from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction.
    [Show full text]
  • Computer Conservation Society
    Issue Number 76 Winter 2016/7 Computer Conservation Society Aims and objectives The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; and the Museum of Science and Industry (MSI) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from BCS, fees from corporate membership, donations and by the free use of the facilities of our founding museums. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer. The CCS also enjoys a close relationship with the National Museum of Computing.
    [Show full text]
  • Random Access Memory (RAM)
    P-2 Digital Design & Applications Semiconductor Memory (Unit-V) By: A K Verma SOS in Electronics & Photonics Pt. Ravishankar Shukla University, Raipur (C.G.) 1 What is Memory? • In computing, memory refers to the physical devices used to store programs (sequences of instructions) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic device. The term primary memory is used for the information in physical systems which function at high-speed (i.e. RAM), as a distinction from secondary memory, which are physical devices for program and data storage which are slow to access but offer higher memory capacity. If needed, primary memory can be stored in secondary memory, through a memory management technique called "virtual memory“.[1] 2 History • In the early 1940s, memory technology mostly permitted a capacity of a few bytes. The first electronic programmable digital computer, the ENIAC, using thousands of octal-base radio vacuum tubes, could perform simple calculations involving 20 numbers of ten decimal digits which were held in the vacuum tube accumulators. • The next significant advance in computer memory came with acoustic delay line memory, developed by J. Presper Eckert in the early 1940s. Through the construction of a glass tube filled with mercury and plugged at each end with a quartz crystal, delay lines could store bits of information within the quartz and transfer it through sound waves propagating through mercury. Delay line memory would be limited to a capacity of up to a few hundred thousand bits to remain efficient.
    [Show full text]
  • Optical RAM and Integrated Optical Memories: a Survey
    Alexoudi, T. , Kanellos, G. T., & Pleros, N. (2020). Optical RAM and integrated optical memories: a survey. Light, science & applications, 9, 91. https://doi.org/10.1038/s41377-020-0325-9 Publisher's PDF, also known as Version of record License (if available): CC BY Link to published version (if available): 10.1038/s41377-020-0325-9 Link to publication record in Explore Bristol Research PDF-document This is the final published version of the article (version of record). It first appeared online via Nature at https://doi.org/10.1038/s41377-020-0325-9 . Please refer to any applicable terms of use of the publisher. University of Bristol - Explore Bristol Research General rights This document is made available in accordance with publisher policies. Please cite only the published version using the reference above. Full terms of use are available: http://www.bristol.ac.uk/red/research-policy/pure/user-guides/ebr-terms/ Alexoudi et al. Light: Science & Applications (2020) 9:91 Official journal of the CIOMP 2047-7538 https://doi.org/10.1038/s41377-020-0325-9 www.nature.com/lsa REVIEW ARTICLE Open Access Optical RAM and integrated optical memories: a survey Theoni Alexoudi1, George Theodore Kanellos2 and Nikos Pleros1 Abstract The remarkable achievements in the area of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for information storage directly in the optical domain, enabling fast access times, increased bandwidth and transparent cooperation with optical interconnect lines. This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics in terms of their energy, speed and footprint.
    [Show full text]
  • System-On-A-Chip
    System-on-a-chip From Wikipedia, the free encyclopedia Jump to: navigation, search System-on-a-chip or system on chip (SoC or SOC) is an idea of integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. SoC is believed to be more cost effective since it increases the yield of the fabrication and because its packaging is simpler. Contents [hide] • 1 Structure • 2 Design flow • 3 Fabrication • 4 See also • 5 External links [edit] Structure y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller-based System-on-a-Chip A typical SoC consists of: • One or more microcontroller, microprocessor or DSP core(s). • Memory blocks including a selection of ROM, RAM, EEPROM and Flash. • Timing sources including oscillators and phase-locked loops. • Peripherals including counter-timers, real-time timers and power-on reset generators. • External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI. • Analog interfaces including ADCs and DACs. • Voltage regulators and power management circuits. These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC.
    [Show full text]
  • An Optical Delay Line Memory Model with E Cient Algorithms
    An Optical Delay Line Memory Mo del with Ecient Algorithms y z John H. Reif Akhilesh Tyagi Department of Computer Science Department of Computer Science Duke University Iowa State University Durham, NC 27706 Ames, IA 50011 Abstract The extremely high data rates of optical computing technology 100 MWords p er second and upwards present unprecedented challenges in the dynamic memory design. An optical ber loop, used as a delay line, is the b est candidate for primary, dynamic memory at this time. However, they p ose sp ecial problems in the design of algorithms due to synchronization requirements b e- tween the lo op data and the pro cessor. We develop a theoretical mo del, whichwe call the lo op memory mo del LLM, to capture the relevantcharacteristics of a lo op based memory. An imp or- tant class of algorithms, ascend/descend { which includes algorithms for merging, sorting, DFT, matrix transp osition and multiplication and data p ermutation { can b e implemented without any time loss due to memory synchronization. We develop b oth sequential and parallel implementa- tions of ascend/descend algorithms and some matrix computations. Some lower b ounds are also demonstrated. 1 Intro duction 1.1 The Success of VLSI Theory Over the last 15 years, VLSI has moved from b eing a theoretical abstraction to b eing a practical reality. As VLSI design to ols and VLSI fabrication facilities such as MOSIS b ecame widely available, the algorithm design paradigms such as systolic algorithms [Kun79], that were thought to b e of theoretical interest only,have b een used in high p erformance VLSI hardware.
    [Show full text]
  • Volatile Memory (Temporary)
    2234-18 Meeting of Modern Science and School Physics: College for School Teachers of Physics in ICTP 27 April - 3 May, 2011 Information storage Igor Lukyanchuk University of Picardie Amiens France Igor Lukyanchuk Information Storage 40-70s: Mechanical… For computers 50-90s electronic 2000… Materials… Tendencies in technology “Macro” “Micro” “Nano*” 1m-1cm-1mm m mm nm m Mecanical Electronic Functional devices devices materials bc… 50s 40s-2000 90s-… Technology: structural material and molecular level *See also: Wednesday, April, 27 10.00-11.00 Yuri GALPERIN Introduction to nano-physics Objective: what « smart » properties of material can be used for memory storrage? What ! Physical Principle is beoyond? See also: Thursday, April, 28 8.30-9.30 Giuseppe BALESTRINO Tailoring of new materials History: First computers: The German Z3 (1941) was the first general- purpose digital electromechanical, computer, It used relays for all functions. Destroyed in a bombing raid on Berlin in December 1943. Power Consumption: Around 4000 watts Average calculation Speed: Addition 0.8 seconds Multiplication 3 seconds Relays memory Elements: Around 2,000 relays (1,400 for the memory) Frequency: 5.3 Hertz Data memory: 64 words with a length of 22 bits The ten British Colossus computers (used for cryptanalysis starting in 1943) were designed by Tommy Flowers. The Colossus computers were digital, electronic, and were programmed by plugboard and switches, but they were dedicated to code breaking and not general purpose.[24] ENIAC Electronic Numerical Integrator And Computer) was the first general-purpose digital programming electronic computer. ENIAC was designed to calculate artillery firing tables for the United States Army's Ballistic Research Laboratory.
    [Show full text]
  • Analysis of a Tunnel-Diode Delay-Line Reflex Memory Cell
    AN ABSTRACT OF THE THESIS OF Ronald Lee Johnson for the M.S. in Electrical Engineering (Name) (Degree) (Major) Date thesis is presented / 'a Title ANALYSIS OF A TUNNEL -DIODE DELAY -LINE REFLEX MEMORY CELL Abstract approved Redacted for privacy (Major professor) The operation of a tunnel -diode delay -line memory cell is examined in some detail, and a digital computer program which approximately simulates the operation of this memory cell is devel- oped. The data from the computer simulation is compared with the available experimental data and found to agree very closely for clock frequencies up to 100 megahertz. The computer simulation should be accurate at higher frequencies, but limitations in the experimental system preclude the necessary verification. The simulation data, augmented by experimental data, is shown to be useful in answering questions concerning the relative resistance levels of the various components of the circuit, the most desirable tunnel -diode specifications, and the proper timing and termination of the pulses on the delay line. The computer simulationhas in this way added to the previous understanding of the operation of the memory cell, and it has opened the door to further analysis of this and other related tunnel -diode circuits. ANALYSIS OF A TUNNEL -DIODE DELAY -LINE REFLEX MEMORY CELL by RONALD LEE JOHNSON A THESIS submitted to OREGON STATE UNIVERSITY in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE June 1966 APPROVED: Redacted for privacy Assistant Professor of Electrical Engineering Redacted for privacy \--Head of Department of electrical Engineering Redácted for privacy Dean of Graduate School Date thesis is presented I ( , 156,5" Typed by Beryl Johnson ACKNOWLEDGMENT The author wishes to thank Professor Amort for the timely suggestions and encourage- ment he gave throughout the course of this study.
    [Show full text]
  • Information Storage and Spintronics 10
    Information Storage and Spintronics 10 Atsufumi Hirohata Department of Electronic Engineering 13:30 Monday, 02/November/2020 (B/B 006 & online) & 12:00 Thursday, 05/November/2020 (online) Quick Review over the Last Lecture DRAM : Read-out operation of 1C1T : Data stored in a capacitor. “1”-data : 1 V + ΔV = 2 V ® Electric charge needs to be refreshed. ® DRAM requires large power consumption. 3.6 V ON 2 V = 1 V + ΔV Refresh operation of 1C1T : “0”-data : 1 V – ΔV = 0 V 3.6 V ON 0 V = 1 V – ΔV * http://www.wikipedia.org/; * http://users.cis.fiu.edu/~prabakar/cda4101/Common/notes/lecture09.html 10 Static Random Access Memory • Volatile memory developmement • 6T-SRAM architecture • Read / write operation • 1T-SRAM • Various ROMs Memory Types Rewritable Volatile Dynamic DRAM Static SRAM Non-volatile Static MRAM FeRAM PRAM Read only Non-volatile Static PROM Mask ROM Read majority Non-volatile Static Flash (Writable) EPROM * http://www.semiconductorjapan.net/serial/lesson/12.html Manchester Automatic Digital Machine In 1949, Frederic C. Williams and Tom Kilburn developed Manchester Mark 1 : One of the earliest stored-programme computers * http://www.computer50.org/mark1/; ** http://www.wikipedia.org/ Williams-Kilburn Tube Cathode-ray tube to store data : Utilise a minor change of electron charges at a fluorescent screen when an electron hit it. * http://www.wikipedia.org/ Delay Line Memory In 1947, John P. Eckart invented a mercury delay line memory : Utilise an ultrasonic wave generated by a transducer to store a data. * http://www.wikipedia.org/ Selectron Tube In 1953, Jan A.
    [Show full text]