DOCSLIB.ORG

An Optical Delay Line Memory Model with E Cient Algorithms

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
An Optical Delay Line Memory Model with E Cient Algorithms An Optical Delay Line Memory Mo del with Ecient Algorithms y z John H. Reif Akhilesh Tyagi Department of Computer Science Department of Computer Science Duke University Iowa State University Durham, NC 27706 Ames, IA 50011 Abstract The extremely high data rates of optical computing technology 100 MWords p er second and upwards present unprecedented challenges in the dynamic memory design. An optical ber loop, used as a delay line, is the b est candidate for primary, dynamic memory at this time. However, they p ose sp ecial problems in the design of algorithms due to synchronization requirements b e- tween the lo op data and the pro cessor. We develop a theoretical mo del, whichwe call the lo op memory mo del LLM, to capture the relevantcharacteristics of a lo op based memory. An imp or- tant class of algorithms, ascend/descend { which includes algorithms for merging, sorting, DFT, matrix transp osition and multiplication and data p ermutation { can b e implemented without any time loss due to memory synchronization. We develop b oth sequential and parallel implementa- tions of ascend/descend algorithms and some matrix computations. Some lower b ounds are also demonstrated. 1 Intro duction 1.1 The Success of VLSI Theory Over the last 15 years, VLSI has moved from b eing a theoretical abstraction to b eing a practical reality. As VLSI design to ols and VLSI fabrication facilities such as MOSIS b ecame widely available, the algorithm design paradigms such as systolic algorithms [Kun79], that were thought to b e of theoretical interest only,have b een used in high p erformance VLSI hardware. Along the same lines, the theoretical limitations of VLSI predicted by area-time tradeo lower b ounds [Tho79]have b een found to b e imp ortant limitations in practice. A preliminary version of this pap er app eared in Proc. of the ADVANCED RESEARCH in VLSI: International Conference 1991, MIT Press, March 1991. y supp orted in part by DARPA/ARO contract DAAL03-88-K-0195, Air Force Contract AFOSR-87-0386, DARPA/ISTO contract N00014-88-K-0458, NASA sub contract 550-63 of primecontract NAS5-30428 and by NSF Grant NSF-IRI-91-00681. z supp orted by NSF Grant MIP-8806169, NCBS&T Grant 89SE04 and a Junior Faculty Developmentaward from UNC, Chap el Hill. This work was p erformed when the second author was with UNC, Chap el Hill. 1 1.2 The Promise of Optical Computing The optical computing technology is considered to b e one of the several technologies that could provide a b o ost of 2-3 orders of magnitude over the currently used semiconductor silicon based technology,in computing sp eed. The eld of electro-optical computing, however, is at its infancy stage; comparable to the state of VLSI technology,say,10years ago. Fabrication facilities for manykey electro-optical comp onents are not widely available { instead, the crucial electro-optical devices must b e sp ecially made in the lab oratories. However, a numb er of prototyp e electro-optical computing systems have b een built recently { p erhaps most notably at Bell Lab oratories under Huang [Hua80, Hua84], and also at Boulder under Jordan see b elow. In addition, several optical message routing devices have b een built at Boulder [MJR89], Stanford and USC [Lou91], [MG90, MMG90], [SS84]. Thus optical computing technology has matured to the p oint that prototypical computing machines can b e built in the research lab oratories. But it certainly has not attained the maturity of VLSI technology. What is likely to o ccur in the future? The technology for electro-optical computing is likely to advance rapidly through the 90s, just as VLSI technology advanced in the late 70s and 80s. Therefore, following our past exp erience with VLSI, it seems likely that the theoretical underpinnings for optical computing technology { namely the discovery of ecient algorithms and of resource lower b ounds, are crucial to guide its development. This seems to us to b e the right moment for the algorithm designers to get involved in this enterprise. A careful interaction b etween the architects and the algorithm designers can lead to a b etter thought-out design. This pap er is an attempt in that direction. 1.3 Data Storage: A Key Problem in Optical Computing The optical computing technology can obtain extremely high data rates b eyond what can b e obtained by current semiconductor technology. Therefore, in order to sustain these data rates, the dynamic storage must b e based on new technologies which are likely to b e completely or partially optical. Jordan at the Colorado Opto electronic Computing Systems Center [Jor89b] and some other groups have prop osed and used optical delay line lo ops for dynamic storage. In these data storage systems, an optical b er, whose characteristics match the op erating wavelength, is used to form a delay line lo op. In particular, the system sends a sequence of optically enco ded bits down one end of the lo op and after a certain delay which dep ends on the length and optical characteristics of the lo op, the optically enco ded bits app ear at the end of the lo op, to b e either utilized at that time and/or once again sentdown the lo op. This idea of using propagation delay for data storage dates back to the use of mercury delay lo ops in early electronic computing systems b efore the advent of large primary or 4 secondary memory storage. Jordan [Jor89b] has b een able to store 10 bits p er b er lo op with the b er length of approximately one kilometer. This was achieved in a small, low cost prototyp e system with 2 a synchronous lo op without very precise temp erature control. Jordan used such a delay lo op system to build the second known purely optical computer after Huang's, which can simulate a counter. Note that this do es not represent the ultimate limitations on the storage capacity of optical delay lo ops, which could in principle provide very large storage using higher p erformance electro-optical transducers and multiple lo ops. Maguire and Prucnal [JP89] suggest using optical delay lines to form disk storage. The main problem with such a dynamic storage is that it is not a random-access memory. A delay line lo op cannot b e tapp ed at many p oints since a larger numb er of taps leads to excessive signal degradation. This implies that if an algorithm is not designed around this shortcoming of the dynamic storage, it mighthavetowait for the whole length of the lo op for each data access. Systolic algorithms [Kung, [Kun79]] also exhibit such a tightinter-dep endence b etween the dynamic storage and the data access pattern. 1.4 Lo op Memory Mo del and Our Results In this pap er, we prop ose the lo op-memory mo del LMM as a mo del of sequential electro-optical computing with delay line based dynamic storage. The lo op-memory mo del contains the basic features that current delay lo op systems use, as well as the features that systems in the future are likely to use. It would seem that the restrictive discipli ne imp osed on the data access patterns by a lo op memory would degrade the p erformance of most algorithms, b ecause the pro cessor mighthave to idle waiting for data. However, we demonstrate that an imp ortant class of algorithms, ascend/descend algorithms, can b e realized in the lo op memory mo del without any loss of eciency. Note that many problems including merging, sorting, DFT, matrix transp osition and multiplication and data p ermutation are solvable with an ascend/descend algorithm describ ed in Section 3. In fact, we give sequential algorithms covering a broad range for the numb er of lo ops required. A parallel implementation p erforming the optimal amountofwork is also shown. The work p erformed by a parallel algorithm running on p pro cessors in time T is given by p T . An ascend or descend phase takes time O n log n in LMM using log n lo ops of sizes 1; 2; 4; :::;n. Note that a straight-forward emulation of a butter y network with O n log n time p erformance re- quires O n lo ops: n lo ops of size 1, n=2 of size 2, n=4 of size 4, :::, 1 of size n. It can b e implemented p 1:5 in time n just with two lo ops of sizes n and n each. This can b e generalized into an ascend-descend 1:5 k=2 scheme with time nk + n 2 with 2 k log n lo ops. At this p oint in time, a lo op is a precious resource in optical technology, and hence tailoring an algorithm around the numberofavailable lo ops is an imp ortant capability. The k -lo op adaptation of the ascend/descend algorithm provides just this 2 capability. A single lo op pro cessor takes n time. A matching lower b ound also exists for this case, 3 which is derived in Section 6 from one tap e Turing machine crossing sequence arguments. Matrix multiplication and matrix transp osition can also b e p erformed in LMM without any loss of time. We also consider a butter y network with p log p LMM pro cessors, where 1 <pn. The work of pro cessors, time pro duct of this network for ascend-descend algorithms is shown to b e O n log n.
Load more

Recommended publications
  • DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA
    Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_
    [Show full text]
  • Metal Ultrasonic Delay Lines
    Research Paper 2453 rOOmOI of R~eo"h of The NO tiO ~;;:if ~;=asoni;l~~i~;~~~:: Russell W . Mebs, John H. Darr, and John D. Grimsley A study was made of the applicability of a number of metals and a lloys for therm all y stable ultrasonic delay lin es. A preliminary iavestigation was made of different types of pressure holders and ad­ hesi ves for use in crystal t ransducer attachments and of the iafluence of specimen length on attenuation for valious m etals and alloy. The effect of cold-work, annealing, and specimen cross section on attenuation was a lso determined for a representati ve isoelastic alloy. Measurements of temperature variation of signal attenuation, distort ion, a nd delay t im e on a number of assembled delay lines indicated t hat an isoelastic a lloy employing over cured epoxy-resin crystal attachments gave best over-all t ransmission characteristics. No correlation was obtainable between strength and SOLl nd-transmission characteristics with varioLls cemented joints. 1. Introduction variations in pulse attenuation and distortion with acceleration or change of temperature. The ultrasonic delay line has come into wide use Only a general survey will be given of the basic in recent years with the development of radar, com­ theory of ultrasonic transmission as related to delay ~uters , and other electronic devices [1 , 2, 3, 4V It lines of 50 tLsec or less. More comprehensive 's a means for delaying a signal for a predetermined treatments have been given elsewhere [2, 4, and 5]. ~hort period to be accurately reproduced for use at _tn appropriate later instant.
    [Show full text]
  • History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch Cards - Herman Hollerith (Of IBM Forerunner) Invented "IBM" Punch Cards to Be Used for the 1890 Census
    Computer Memory History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch cards - Herman Hollerith (of IBM forerunner) invented "IBM" punch cards to be used for the 1890 census. 1932 - Drum memory 1947 - Delay line memory 1949 - Magnetic CORE memory 1950 - Magnetic TAPE memory 1955 - Magnetic DISK memory - IBM RAMAC was first one 1957 - Plated wire memory 1962 - Thin film memory 1968 (ca) - Paper tape - Had beginnings dating back to 1846, but became widely used with teletype machines such as the Teletype Model 33 ASR, which were adopted early on by minicomputers as a primitive terminal. 1970 - Bubble memory 1970 - DRAM - Invented by Intel, first device was the 1101, organized as 256x1, followed by the 4x larger (1024x1) 1103(A) -- regarded as the world's first commercial DRAM (intro in October 1970). 1971 - Bipolar SRAM - Fairchild 256x1 (note IBM made a 16-bit SRAM in late 1960s. AMD made a second source of a 64x1 SRAM by Fairchild in 1971.) 1971 - EPROM - Invented by Dov Frohman of Intel as the i1702, a 2K-bit (256x8) EPROM. 1971 - "Floppy" disks -- First were 8-inch, hence very flexible ("floppy"). The 8" became commercially available in 1971. 1973 (ca) - Magnetic TAPE CASSETTE memory 1976 - Shugart Associates introduced the first 5¼-inch floppy (flexible) disk drive 1977 - EEPROM - invented by Eli Harari at Hughes - a BYTE erasable device 1979 - CMOS SRAM (static RAM, 4T/6T cell, implemented as a latch) - first introduced by HP then its spinoff as Integrated Device Technology. I believe first devices were 1K (1024x1), and later organized as x4 then x8.
    [Show full text]
  • The Graphic Display of Computer Memory Data
    University of Windsor Scholarship at UWindsor Electronic Theses and Dissertations Theses, Dissertations, and Major Papers 7-21-1969 The graphic display of computer memory data. Satish P. Agrawal University of Windsor Follow this and additional works at: https://scholar.uwindsor.ca/etd Recommended Citation Agrawal, Satish P., "The graphic display of computer memory data." (1969). Electronic Theses and Dissertations. 6548. https://scholar.uwindsor.ca/etd/6548 This online database contains the full-text of PhD dissertations and Masters’ theses of University of Windsor students from 1954 forward. These documents are made available for personal study and research purposes only, in accordance with the Canadian Copyright Act and the Creative Commons license—CC BY-NC-ND (Attribution, Non-Commercial, No Derivative Works). Under this license, works must always be attributed to the copyright holder (original author), cannot be used for any commercial purposes, and may not be altered. Any other use would require the permission of the copyright holder. Students may inquire about withdrawing their dissertation and/or thesis from this database. For additional inquiries, please contact the repository administrator via email ([email protected]) or by telephone at 519-253-3000ext. 3208. INFORMATION TO USERS This manuscript has been reproduced from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction.
    [Show full text]
  • Computer Conservation Society
    Issue Number 76 Winter 2016/7 Computer Conservation Society Aims and objectives The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; and the Museum of Science and Industry (MSI) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from BCS, fees from corporate membership, donations and by the free use of the facilities of our founding museums. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer. The CCS also enjoys a close relationship with the National Museum of Computing.
    [Show full text]
  • Random Access Memory (RAM)
    P-2 Digital Design & Applications Semiconductor Memory (Unit-V) By: A K Verma SOS in Electronics & Photonics Pt. Ravishankar Shukla University, Raipur (C.G.) 1 What is Memory? • In computing, memory refers to the physical devices used to store programs (sequences of instructions) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic device. The term primary memory is used for the information in physical systems which function at high-speed (i.e. RAM), as a distinction from secondary memory, which are physical devices for program and data storage which are slow to access but offer higher memory capacity. If needed, primary memory can be stored in secondary memory, through a memory management technique called "virtual memory“.[1] 2 History • In the early 1940s, memory technology mostly permitted a capacity of a few bytes. The first electronic programmable digital computer, the ENIAC, using thousands of octal-base radio vacuum tubes, could perform simple calculations involving 20 numbers of ten decimal digits which were held in the vacuum tube accumulators. • The next significant advance in computer memory came with acoustic delay line memory, developed by J. Presper Eckert in the early 1940s. Through the construction of a glass tube filled with mercury and plugged at each end with a quartz crystal, delay lines could store bits of information within the quartz and transfer it through sound waves propagating through mercury. Delay line memory would be limited to a capacity of up to a few hundred thousand bits to remain efficient.
    [Show full text]
  • Optical RAM and Integrated Optical Memories: a Survey
    Alexoudi, T. , Kanellos, G. T., & Pleros, N. (2020). Optical RAM and integrated optical memories: a survey. Light, science & applications, 9, 91. https://doi.org/10.1038/s41377-020-0325-9 Publisher's PDF, also known as Version of record License (if available): CC BY Link to published version (if available): 10.1038/s41377-020-0325-9 Link to publication record in Explore Bristol Research PDF-document This is the final published version of the article (version of record). It first appeared online via Nature at https://doi.org/10.1038/s41377-020-0325-9 . Please refer to any applicable terms of use of the publisher. University of Bristol - Explore Bristol Research General rights This document is made available in accordance with publisher policies. Please cite only the published version using the reference above. Full terms of use are available: http://www.bristol.ac.uk/red/research-policy/pure/user-guides/ebr-terms/ Alexoudi et al. Light: Science & Applications (2020) 9:91 Official journal of the CIOMP 2047-7538 https://doi.org/10.1038/s41377-020-0325-9 www.nature.com/lsa REVIEW ARTICLE Open Access Optical RAM and integrated optical memories: a survey Theoni Alexoudi1, George Theodore Kanellos2 and Nikos Pleros1 Abstract The remarkable achievements in the area of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for information storage directly in the optical domain, enabling fast access times, increased bandwidth and transparent cooperation with optical interconnect lines. This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics in terms of their energy, speed and footprint.
    [Show full text]
  • System-On-A-Chip
    System-on-a-chip From Wikipedia, the free encyclopedia Jump to: navigation, search System-on-a-chip or system on chip (SoC or SOC) is an idea of integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. SoC is believed to be more cost effective since it increases the yield of the fabrication and because its packaging is simpler. Contents [hide] • 1 Structure • 2 Design flow • 3 Fabrication • 4 See also • 5 External links [edit] Structure y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller-based System-on-a-Chip A typical SoC consists of: • One or more microcontroller, microprocessor or DSP core(s). • Memory blocks including a selection of ROM, RAM, EEPROM and Flash. • Timing sources including oscillators and phase-locked loops. • Peripherals including counter-timers, real-time timers and power-on reset generators. • External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI. • Analog interfaces including ADCs and DACs. • Voltage regulators and power management circuits. These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC.
    [Show full text]
  • Transforming Education for a World of Opportunity Competitions For
    University of Michigan AIChE February 2, 2012 This Week’s Speakers: Intel Energy-Efficient Computing Intel helps drive best sustainable business practices for energy-conscious manufacturing Technology innovation and sustainable business practices help us create products Transforming Education for a World of that are more energy efficient and have a Opportunity smaller ecological footprint than previous generations, while maintaining the highest With over 200 programs in more than 70 countries, Intel works with and supports standards for our microprocessors. governments, NGO’s and communities to achieve Energy-efficient performance educational reform that enables children to excel in the global economy. Our processors are designed to help support the effort to minimize the world’s concerns Competitions for Inspiring Innovators and with the environmental impact of Entrepreneurs Information and Communication Today's students are innovators of tomorrow. Technology (ICT). We’re helping businesses Find out how we enable the next generation of assess how IT can reduce CO2 emissions scientists, engineers, and entrepreneurs through across the global economy. competitions. EDUCATION Technology for Advancing Education We're using technology to enhance learning Intel is helping to transform the lives of environments. See how Intel helps improve millions through education. For over a education worldwide with advanced technology, decade, we've been working with countries, Internet access, and digital content. communities, and schools worldwide to bring the resources and solutions needed Programs for Improving Teaching and for advancing education. We collaborate Learning with governments, policy-makers, and local Intel works directly with students, teachers, and vendors to turn their vision into reality. universities to enable tomorrow’s innovators.
    [Show full text]
  • Volatile Memory (Temporary)
    2234-18 Meeting of Modern Science and School Physics: College for School Teachers of Physics in ICTP 27 April - 3 May, 2011 Information storage Igor Lukyanchuk University of Picardie Amiens France Igor Lukyanchuk Information Storage 40-70s: Mechanical… For computers 50-90s electronic 2000… Materials… Tendencies in technology “Macro” “Micro” “Nano*” 1m-1cm-1mm m mm nm m Mecanical Electronic Functional devices devices materials bc… 50s 40s-2000 90s-… Technology: structural material and molecular level *See also: Wednesday, April, 27 10.00-11.00 Yuri GALPERIN Introduction to nano-physics Objective: what « smart » properties of material can be used for memory storrage? What ! Physical Principle is beoyond? See also: Thursday, April, 28 8.30-9.30 Giuseppe BALESTRINO Tailoring of new materials History: First computers: The German Z3 (1941) was the first general- purpose digital electromechanical, computer, It used relays for all functions. Destroyed in a bombing raid on Berlin in December 1943. Power Consumption: Around 4000 watts Average calculation Speed: Addition 0.8 seconds Multiplication 3 seconds Relays memory Elements: Around 2,000 relays (1,400 for the memory) Frequency: 5.3 Hertz Data memory: 64 words with a length of 22 bits The ten British Colossus computers (used for cryptanalysis starting in 1943) were designed by Tommy Flowers. The Colossus computers were digital, electronic, and were programmed by plugboard and switches, but they were dedicated to code breaking and not general purpose.[24] ENIAC Electronic Numerical Integrator And Computer) was the first general-purpose digital programming electronic computer. ENIAC was designed to calculate artillery firing tables for the United States Army's Ballistic Research Laboratory.
    [Show full text]
  • Analysis of a Tunnel-Diode Delay-Line Reflex Memory Cell
    AN ABSTRACT OF THE THESIS OF Ronald Lee Johnson for the M.S. in Electrical Engineering (Name) (Degree) (Major) Date thesis is presented / 'a Title ANALYSIS OF A TUNNEL -DIODE DELAY -LINE REFLEX MEMORY CELL Abstract approved Redacted for privacy (Major professor) The operation of a tunnel -diode delay -line memory cell is examined in some detail, and a digital computer program which approximately simulates the operation of this memory cell is devel- oped. The data from the computer simulation is compared with the available experimental data and found to agree very closely for clock frequencies up to 100 megahertz. The computer simulation should be accurate at higher frequencies, but limitations in the experimental system preclude the necessary verification. The simulation data, augmented by experimental data, is shown to be useful in answering questions concerning the relative resistance levels of the various components of the circuit, the most desirable tunnel -diode specifications, and the proper timing and termination of the pulses on the delay line. The computer simulationhas in this way added to the previous understanding of the operation of the memory cell, and it has opened the door to further analysis of this and other related tunnel -diode circuits. ANALYSIS OF A TUNNEL -DIODE DELAY -LINE REFLEX MEMORY CELL by RONALD LEE JOHNSON A THESIS submitted to OREGON STATE UNIVERSITY in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE June 1966 APPROVED: Redacted for privacy Assistant Professor of Electrical Engineering Redacted for privacy \--Head of Department of electrical Engineering Redácted for privacy Dean of Graduate School Date thesis is presented I ( , 156,5" Typed by Beryl Johnson ACKNOWLEDGMENT The author wishes to thank Professor Amort for the timely suggestions and encourage- ment he gave throughout the course of this study.
    [Show full text]
  • Information Storage and Spintronics 10
    Information Storage and Spintronics 10 Atsufumi Hirohata Department of Electronic Engineering 13:30 Monday, 02/November/2020 (B/B 006 & online) & 12:00 Thursday, 05/November/2020 (online) Quick Review over the Last Lecture DRAM : Read-out operation of 1C1T : Data stored in a capacitor. “1”-data : 1 V + ΔV = 2 V ® Electric charge needs to be refreshed. ® DRAM requires large power consumption. 3.6 V ON 2 V = 1 V + ΔV Refresh operation of 1C1T : “0”-data : 1 V – ΔV = 0 V 3.6 V ON 0 V = 1 V – ΔV * http://www.wikipedia.org/; * http://users.cis.fiu.edu/~prabakar/cda4101/Common/notes/lecture09.html 10 Static Random Access Memory • Volatile memory developmement • 6T-SRAM architecture • Read / write operation • 1T-SRAM • Various ROMs Memory Types Rewritable Volatile Dynamic DRAM Static SRAM Non-volatile Static MRAM FeRAM PRAM Read only Non-volatile Static PROM Mask ROM Read majority Non-volatile Static Flash (Writable) EPROM * http://www.semiconductorjapan.net/serial/lesson/12.html Manchester Automatic Digital Machine In 1949, Frederic C. Williams and Tom Kilburn developed Manchester Mark 1 : One of the earliest stored-programme computers * http://www.computer50.org/mark1/; ** http://www.wikipedia.org/ Williams-Kilburn Tube Cathode-ray tube to store data : Utilise a minor change of electron charges at a fluorescent screen when an electron hit it. * http://www.wikipedia.org/ Delay Line Memory In 1947, John P. Eckart invented a mercury delay line memory : Utilise an ultrasonic wave generated by a transducer to store a data. * http://www.wikipedia.org/ Selectron Tube In 1953, Jan A.
    [Show full text]