University of Michigan AIChE February 2, 2012 This Week’s Speakers: Intel Energy-Efficient Computing Intel helps drive best sustainable business practices for energy-conscious manufacturing Technology innovation and sustainable business practices help us create products Transforming Education for a World of that are more energy efficient and have a Opportunity smaller ecological footprint than previous generations, while maintaining the highest With over 200 programs in more than 70 countries, Intel works with and supports standards for our microprocessors. governments, NGO’s and communities to achieve Energy-efficient performance educational reform that enables children to excel in the global economy. Our processors are designed to help support the effort to minimize the world’s concerns Competitions for Inspiring Innovators and with the environmental impact of Entrepreneurs Information and Communication Today's students are innovators of tomorrow. Technology (ICT). We’re helping businesses Find out how we enable the next generation of assess how IT can reduce CO2 emissions scientists, engineers, and entrepreneurs through across the global economy. competitions. EDUCATION Technology for Advancing Education We're using technology to enhance learning Intel is helping to transform the lives of environments. See how Intel helps improve millions through education. For over a education worldwide with advanced technology, decade, we've been working with countries, Internet access, and digital content. communities, and schools worldwide to bring the resources and solutions needed Programs for Improving Teaching and for advancing education. We collaborate Learning with governments, policy-makers, and local Intel works directly with students, teachers, and vendors to turn their vision into reality. universities to enable tomorrow’s innovators. Technology that brings quality education to Learn about our worldwide education programs. more people, while sustaining local communities and economies—that's our unwavering commitment. We’re on the web! Announcements http://www.engin.umich.edu/societies/aiche/AIChE/Home.html AIChE Duess To join AIChE this semester: Semester without luncheons - $10 ($15 if not a national member) One semester with luncheon - $25 ($30 if not a national member) Join the National AIChE Why register to be a National AIChE Scan the above image with your i-thing/device member? It’s easy, free, and they send to view our Facebook page for event updates and reminders!!! How easy is that?! you a pen in the mail. Here are the quick and easy steps: AICHE Happy Hour rd 1) Go to www.aiche.org/scaleup When : Friday February 3 4:00-6:00pm Where: Good Time Charlie’s 2) Click Apply Online 3) Enter your info Grab some free appetizers and meet with other 4) Click Join! AICHE members and mentors! You don’t need to If you joined last year, don’t forget to be 21 to attend! renew your membership this year! Novellus Info Session th Mentorship program: Sophomores who When: Monday February 6 6:00-7:00pm do not already have an AIChE mentor may Where: 1013 Dow Find what Novellus has to offer! request one at [email protected]. We will soon be planning a number of great Join The AICHE IM Broomball Team mentorship events, just in time for career When: Thursdays at 11:20 Where: Yost Ice Arena fair. You MUST register to be on the AIChE team by NOON on game day (T hursday, if you want to play the first game) on the Athleague website. You If you have any suggestions for only need to register once. food, email Christine at [email protected]! Bridging the Memory Gap If you know what mercury delay lines are you either have diligently studied computer history or have a good “memory." Mercury delay lines were used in early digital computers as memory to store program and data. It is slow. The processor must sit idle and wait for the instruction or data to come around to be used. Thus from the very beginning of the digital computer era, there existed a discrepancy between the logic speed and the memory response time. This discrepancy is called the memory gap. Technologists and researchers have spent much effort to find better memory technologies that can match up to the speed of the logic processor. After mercury delay line memory, a few technologies were invented and used such as CRT (Williams Tubes) memory and core memory . They were faster than mercury delay lines but were still slow in comparison with logic. By the late sixties and early seventies semiconductor memories were beginning to appear. Dynamic Random Access Memory (DRAM) was invented in 1967 and represented grea t progress in density and access time. Even though it did not result in memory performance catching up fully with processor performance, it came pretty close. There was hope that from then on memories and processors would benefit from the same semiconducto r technology advancement and would scale together in performance. Unfortunately this did not happen as planned. This was because of significant divergences between the semiconductor technology used for DRAM memories and the technology used for digital logic circuits. Since the eighties, the performance gap between memory and processor has started to widen again. While the microprocessor performance increased at the rate of roughly 50% per year, the speed of DRAM memory improved at a rate of only 7% per year. Processor architecture began to advance on several fronts to compensate for the growing gap. Advances on one front attempted to reduce the memory access latency via caching. Caching is a very effective scheme to bring down the average memory access latency because memory access patterns exhibit spatial and temporal localities. Most of the time, an access to data or instruction hits the cache and results in a very short delay only. Advances in architecture also worked to better tolerate memory latency through methods like out of order execution. Out of order execution allows other instructions that are not blocked by the memory access to continue to execute, thus allowing the processor to bypass any data resolution delays. Unfortunately these architectural techniques require the implementation of more complex logic circuitry, causing power consumption to increase, and this has led us to a point where the return on investment of these complex techniques is diminishing. Moreover, memory has been aiming at density reduction only. There have been few corresponding architectural techniques to improve performance on the memory side. Besides performance, power consumption is becoming a very important criterion for system design. High power consumption complicate d the thermal solution and increases the operation cost of a computer system. We must include the operational cost into the total cost of the computer and not just the system hardware cost. Today, it is estimated that memory accounts for 20 to 40 percent of a computer system’s total power. The proportion is increasing as the density and performance requirements of DRAM increase. One example is the over-fetching incurred due to the way current DRAM die is organized. It activates thousands of bits with each request, but only returns a small number of data bits to the processor. This is rather inefficient. Another example of the DRAM energy inefficiency comes from the fact that DRAM dies are put together on a DIMM and multiple DIMMs may share a channel to communicate with the processor. A single request must activate multiple dies and drive more than one load. Moreover, DRAM also needs to be refreshed periodically to ensure that data is retained in the memory deviecs. The DRAM consumes power even though there is no actual data activity. This is bad for laptop, tablet and handheld platforms because users want instant on from standby and for standby to last for multiple days between charges. We are starting a memory research project with the Industrial Technology Research Institute (ITRI) of Taiwan to address the performance gap and to reduce the power consumption of memory. Novel techniques are being investigated to extend DRAM refresh time to reduce standby power. We are also looking into using an extra (vertical) dimension to help reduce the physical distance between data transfers to save even more energy. Allowing DRAM dies to stack on each other opens up many new opportunities for architectural improvement. We will build models and utilize simulation to explore the design space holistically to find the highest performance, lowest power solution possible. A prototype is planned as well to demonstrate our research results. Making the Memory more power efficient and faster is a challenging task. This challenge has existed since the dawn of digital computer, and it is growing. If we don’t do anything it will severely impede the further advancement of computing systems. It is exciting to work on a difficult and important problem! Source: Shih-Lien Lu, Intel Labs Sr. Principal Engineer, Monday, December 5th, 2011: http://techresearch.intel.com/newsdetail.aspx?Id=34 ChemE of the Week Avi Wolf What are you hobbies/ favorite sport? Fill in the bubbles with the numbers 1-5 so I love playing tennis, but my favorite sport to watch is football with the NY Giants. I may even head to Indianapolis for the super bowl just for that every row, column, and strand has the the atmosphere... let me know if you're going so we can car pool! numbers 1-5. What is your favorite engineering class? Dare I say ChE 487, Senior Design? It's not just a rite of passage which we all must endure, but it's one that we only share with each other. I find others just don't fathom or understand our experiences there. What is your favorite non-engineer class? I know you all are thinking I'm going to say Orgo I, but I've had better: a class in Leadership in the ROTC program.