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Proquest Dissertations u Ottawa I.'I 'nr.i-i-ili' r;iii,iiliriiMr I '.iii.iihi's iini'.i'i illy ITTTT FACULTE DES ETUDES SUPERIEURES ^==1 FACULTY OF GRADUATE AND ET POSTOCTORALES U Ottawa POSDOCTORAL STUDIES L'UmversitcS eanadienne Canada's university Amine Kharrat AUTEUR DE LA THESE / AUTHOR OF THESIS M.Sc. (Systems Science) GRADE/DEGREE System Science FACULTE, ECOLE, DEPARTEMENT / FACULTY, SCHOOL, DEPARTMENT A Floating-point Analog-to-Digital Architecture for a Wide Range-Dynamic Acquisition System TITRE DE LA THESE / TITLE OF THESIS Voicu Groza DIRECTEUR (DIRECTRICE) DE LA THESE / THESIS SUPERVISOR CO-DIRECTEUR (CO-DIRECTRICE) DE LA THESE / THESIS CO-SUPERVISOR EXAMINATEURS (EXAMINATRICES) DE LA THESE/THESIS EXAMINERS Emil Petriu Tet Yeap Gary W. Slater Le Doyen de la Faculte des etudes superieures et postdoctorales / Dean of the Faculty of Graduate and Postdoctoral Studies A Floating-Point Analog-to-Digital Architecture for a Wide Range-Dynamic Acquisition System By Amine Kharrat A Thesis Presented to School of Graduate Studies and Research In partial fulfillment of the Requirements for the degree of Master of Science Master program in Systems Science University of Ottawa Ottawa, Ontario, Canada, 2009 Copyright © 2009 Amine Kharrat Library and Archives Bibliotheque et 1*1 Canada Archives Canada Published Heritage Direction du Branch Patrimoine de I'edition 395 Wellington Street 395, rue Wellington OttawaONK1A0N4 OttawaONK1A0N4 Canada Canada Your file Votre reference ISBN: 978-0-494-61147-0 Our We Notre reference ISBN: 978-0-494-61147-0 NOTICE: AVIS: The author has granted a non­ L'auteur a accorde une licence non exclusive exclusive license allowing Library and permettant a la Bibliotheque et Archives Archives Canada to reproduce, Canada de reproduire, publier, archiver, publish, archive, preserve, conserve, sauvegarder, conserver, transmettre au public communicate to the public by par telecommunication ou par I'Internet, preter, telecommunication or on the Internet, distribuer et vendre des theses partout dans le loan, distribute and sell theses monde, a des fins commerciales ou autres, sur worldwide, for commercial or non­ support microforme, papier, electronique et/ou commercial purposes, in microform, autres formats. paper, electronic and/or any other formats. The author retains copyright L'auteur conserve la propriete du droit d'auteur ownership and moral rights in this et des droits moraux qui protege cette these. Ni thesis. Neither the thesis nor la these ni des extraits substantiels de celle-ci substantial extracts from it may be ne doivent etre imprimes ou autrement printed or otherwise reproduced reproduits sans son autorisation. without the author's permission. In compliance with the Canadian Conformement a la loi canadienne sur la Privacy Act some supporting forms protection de la vie privee, quelques may have been removed from this formulaires secondaires ont ete enleves de thesis. cette these. While these forms may be included Bien que ces formulaires aient inclus dans in the document page count, their la pagination, il n'y aura aucun contenu removal does not represent any loss manquant. of content from the thesis. ••I Canada Abstract In this thesis, the floating-point analog-to-digital conversion approach has been investigated for the implementation of a computer acquisition system for wide range- dynamic signals. The Floating-point A/D converters (FP-ADC) can dissociate the resolution from the wide range and thus an ADC with a moderate resolution can achieve a wide dynamic range. This dissertation studies the floating-point analog-to-digital converters and describes their characteristics and specifications. More specifically it analyses the sequential FP-ADC and improves the state of the art in conversion time as well as precision in floating-point analog-to-digital converters. It shows an implementation of the sequential FP-ADC on a daughter card which is connected to a Stratix Field Programmable Gate Array (FPGA) from Altera. The correctness of the design was verified by computer simulations while the functionality of the implemented FP-ADC on the manufactured 4-layer Printed Circuit Board (PCB) was tested on a test bench controlled by a PC. II Acknowledgments This thesis would have been impossible to complete without the support and help I received. I would like to acknowledge those who have provided me with the opportunity to finish this thesis and my graduate studies. First I would like to thank my supervisor and professor at the School of Information Technology and Engineering at the University of Ottawa, Dr. Voicu Groza. I am deeply grateful for his guidance and support and his devotion and patience with me during the course of my research. I would also like to thank the members and staffs at the University of Ottawa and all parties who have been involved in this process especially Analog Devices for providing me with samples. And finally I would like to express my gratitude and appreciation to my family and friends for their understanding and encouragements for the period of my graduate studies. Ill Acronyms ADC Analog-to-Digital Converter CMOS Complementary Metal-Oxide Semiconductor DAC Digital-to-Analog Converter DNL Differential Nonlinearity DR Dynamic Range DSP Digital Signal Processing ENOB Effective Number of Bits FP-ADC Floating Point Analog-to-Digital Converter FPGA Field Programmable Gate Array INL Integral Nonlinearity Error LSB Least Significant Bit MSB Most Significant Bit PCB Printed Circuit Board PDF Probability Density Function PGA Programmable Gain Amplifier RMS Root Mean Square SNR Signal Noise to Ratio UART Universal Asynchronous Receiver and Transmitter VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuits Table of Contents A Floating-Point Analog-to-Digital Architecture for a Wide Range-Dynamic Acquisition System I Abstract II Acknowledgments Ill Acronyms IV Table of Contents V List of figures VIII List of tables XI List of tables XI Chapter 1 1 1. Introduction 1 1.1. Motivation 2 1.2. Contribution 3 1.3. Thesis overview 4 Chapter 2 6 2. Fundamentals 6 2.1. Floating-point representation versus fixed-point representation 6 2.2. Floating-point arithmetic standard 8 2.2.1. General layout 9 2.3. Analog-to-digital converter background 10 2.4. General specifications of an analog-to-digital converter 13 2.4.1. Analog/Digital conversion relationship 13 V 2.4.2. Characteristics of an analog-to-digital converter 16 2.4.2.1. Accuracy parameters 16 2.4.2.2. Operational Characteristics 21 2.5. Quantization 22 2.5.1. Fixed-point quantization 22 2.5.2. Floating-point quantization 24 2.5.3. Floating-point quantization noise 27 Chapter 3 29 3. Quantization of a wide range dynamic signals 29 3.1. ADC architecture 29 3.1.1. Integrating ADC 30 3.1.2. Flash ADC 30 3.1.3. Logarithmic ADC 31 3.1.4. Sigma-Delta (E - A) ADC 32 3.1.5. Pipelined and Sub ranging ADC 33 3.1.6. Successive Approximation Register (SAR) ADC 34 3.2. Review of floating-point A/D converters 34 Chapter 4 42 4. System Description 42 4.1. The proposed FP-ADC architecture 42 4.2. System Architecture 44 4.3. Daughter Card FP-ADC Subsystem Description 45 4.4. FPGA Subsystem Description 51 4.5. The memory block 56 4.6. The Control Unit 60 Chapter 5 62 5. Simulations and Testing 62 5.1. FP-ADC Subsystem Simulation and Testing 62 5.2. FPGA Subsystem Simulation and Testing 76 5.2.1. Transmitter Simulation 77 5.2.2. Receiver Simulation 78 5.2.3. Memory Simulation 80 5.2.4. Control Unit Simulation 81 5.3. Results and Conclusion 83 Chapter 6 85 6. Conclusions and Future Work 85 6.1. Conclusions 85 6.2. Contribution of the thesis 85 6.3. Future work 86 References 88 VII List of figures Figure 2-1 A simple digital processing system [8] 7 Figure 2-2 IEEE 754 Format of Floating Point Numbers 9 Figure 2-3 Staircase ADC Transfer Function 11 Figure 2-4 Ideal 3-bit A/D converter 14 Figure 2-5 Ideal 3-bit D/A converter 15 Figure 2-6 Illustration of DNL, INL, gain error and offset 21 Figure 2-7 PDF of quantization error 23 Figure 2-8 A Floating-point quantizer 25 Figure 2-9 Input-output staircase function for a floating-point quantizer with a 3-bit mantissa [15] 26 Figure 2-10 Floating-point quantization noise 27 Figure 2-11 The PDF of floating-point quantization noise [15] 28 Figure 3-1 A non-uniform floating-point quantizer with a 2-bit mantissa [18] 35 Figure 3-2 A uniform quantizer with a 2-bit mantissa [18] 37 Figure 3-3 Block diagram of sequential floating-point ADC 38 Figure 3-4 Block diagram of parallel floating-point ADC 40 Figure 4-1 Block diagram of sequential floating-point A/D converter 43 Figure 4-2 Flowchart of a floating-point A/D conversion 43 Figure 4-3 Block diagram of the system architecture 44 Figure 4-4 FP-ADC Schematic 46 Figure 4-5 Gain settings for a triangular input signal 48 Figure 4-6 S/H Waveforms 49 Figure 4-7 FP-ADC Layout 50 Figure 4-8 FP-ADC Daughter-Card 51 Figure 4-9 FPGA subsystem 52 Figure 4-10 Memory block 56 Figure 4-11 RAM module 57 Figure 4-12 Block diagram of data.vhd 58 Figure 4-13 FSMData.vhd 58 Figure 4-14 FSMController.vhd 59 Figure 4-15 Control Unit 61 Figure 5-1 FP-ADC Simulation Circuit 63 Figure 5-2 SHI tracking the incoming signal 64 Figure 5-3 PGA Output 65 Figure 5-4 The exponent simulation 65 Figure 5-5 SHI output compared to SH2 output 66 Figure 5-6 SH2 output 67 Figure 5-7 The mantissa simulation 68 Figure 5-8 Input Signal (1.25Vpp, lKHz) 69 Figure 5-9 Clock Signal (Bottom) Inverter Output (Top) 69 Figure 5-10 Clock Signal (Bottom) Monostable Output (Top) 70 Figure 5-11 Clock Signal
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