MT-200: Minimizing Jitter in ADC Clock Interfaces

Home , Effective number of bits, Jitter

Applications Engineering Notebook MT-200 One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Minimizing Jitter in ADC Clock Interfaces by the Applications Engineering Group POWER SUPPLY Analog Devices, Inc. INPUT VREF DATA ANALOG OUTPUT IN THIS NOTEBOOK INPUT ADC

Since jitter around the threshold region of a clock interface CLOCK FPGA INTERFACE can corrupt the dynamic performance of an analog-to- INPUT CONTROL digital converter (ADC), this notebook provides an overview of clocking considerations and jitter-reduction techniques.

The Applications Engineering Notebook Educational Series TABLE OF CONTENTS Clock Input Noise...... 2 Frequency Domain View ...... 3 Time Domain View ...... 2 Phase Domain View ...... 4 Effect of Slew Rate...... 3 Solutions for Clocking Converters ...... 5

REVISION HISTORY 1/12—Revision 0: Initial Version

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CLOCK INPUT NOISE Jitter around the threshold region of the clock interface can TIME DOMAIN VIEW corrupt the timing of an analog-to-digital converter (ADC). For example, jitter can cause the ADC to capture a sample at the wrong time, resulting in false sampling of the analog input and reducing the signal to noise (SNR) ratio of the device. A reduction in jitter can be achieved in a number of different ways, including improving the clock source, filtering, frequency division, and clock circuit hardware. This document provides dV suggestions on how to improve the clock system to achieve the best possible performance from an ADC.

Noise in the circuit between the clock and ADC is the root ERROR VOLTAGE cause of clock jitter. Random jitter is caused by random noise, which is distinguished by its unbounded character and follows statistical distributions. Major random noise sources include

• Thermal (Johnson or Nyquist) noise is caused by Brownian ENCODE motion of the charge carriers. • Shot noise is related to the dc current flow across a Q1

potential barrier that is not continuous and smooth, but RECTANGULAR

instead is the result of pulses of current caused by the BI-MODEL

individual flow of carriers. NORMAL

• Flicker noise occurs when a dc current is flowing. It is IDEAL 10338-001 caused by traps in semiconductors that hold carriers that Figure 1. Time Domain View of Jitter would normally constitute a dc current flow for a short period before releasing them. Clock jitter is the sample-to-sample variation of the encode • Burst, or popcorn, noise is caused by contamination and clock which includes both external and internal jitter. Full-scale crystal lattice dislocation at the surface of the silicon that SNR is jitter limited by captures and releases carriers in a random manner. S 1 SNR = rms = log(20)log(20 ) jitter N 2π tf Deterministic jitter is caused by interference that shifts the rms ana log jitter threshold in certain ways that are usually bounded by nature. For example, at 1 Ghz with 100 FS rms jitter, the SNR is 64 dB. There are three ways to view the noise in a clock signal: Viewed in the time domain, variation of the encode edge in • Time domain the x-axis direction causes a y-axis error with a magnitude • Frequency domain dependent on the rise time of the edge. Aperture jitter produces • Phase domain errors in the ADC output as shown in Figure 2. The jitter can occur internally in the ADC or externally in the sampling clock or interface circuitry. dV ΔV = × Δt dt ANALOG INPUT dV = SLOPE ΔVRMS = APERTURE JITTER ERROR dt

NOMINAL HELD OUTPUT

ΔtRMS = APERTURE JITTER

HOLD

TRACK 10338-002 Figure 2. Effects of Aperture Jitter and Sampling Clock Jitter

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Figure 3 shows the effects of jitter on SNR. Five traces are the slew rate. Figure 5 shows how increasing the slew rate shown in Figure 3, each representing a different value of jitter. reduces jitter because only noises in the threshold range The x-axis is full-scale analog input frequency, and the y-axis is contribute to jitter. the SNR due to the jitter as opposed to the total ADC SNR. 200

Jitter on a clock is defined from the fSTART and fSTOP offset frequency. For example, a clock may have 200 fsec of jitter integrated from 1 kHz to fs/2 and 170 fsec of jitter integrated 150 from 10 kHz to fs/2. The integration range is dependent upon the end application. 90 100 SNR OF ADC AT 200MHz, AIN VARIES WITH CLOCK JITTER DIGITAL 85 ADC OUTPUT 84dB JITTER RMS (fs) ANALOG 80 INPUT 78dB SAMPLING 50 CLOCK 75 TIO (dB)

A 50 72dB fS 70 100f 0 66dB S 0 2 4 6 65 O NOISE R O NOISE

INPUT SLEW RATE (V/ns) 10338-005 200fS LT 60 60dB Figure 5. Increasing Slew Rate Reduces Jitter AIN = 200MHz 400fS SIGNA 55 FREQUENCY DOMAIN VIEW 1 EACH LINE SHOWS 50 800fS SNRjit = 20log CONSTANT RMS Close-in noise occurs in the region between the center 2πftjitter CLOCK JITTER IN fs 45 frequency of the sample clock to a single sideband (SSB) offset 100 1000 equal to half the signal bandwidth. Wideband noise extends FULL-SCALE ANALOG INPUT (MHz) 10338-003 Figure 3. As Analog Signal Increases, Clock Jitter Increases SNR from the SSB offset to ½ the bandwidth of the clock receiver. The jitter-based SNR and the effective number of bits (ENOB) are related by the equation: SNR = 6.02 N + 1.76 dB where N = ENOB. For full-scale 100 MHz input, 14-bit ENOB requires that the rms jitter be no greater than 0.125 ps or 125 fs. The equation assumes an ADC of infinite resolution where the only error is noise produced by the clock jitter. CLOSE IN NOISE 130 RMS JITTER < 1ps 0.125ps 120 IS VERY HIGH 0.25ps PERFORMANCE TO ENCODE 0.5ps TO DC WITH CLOCK BANDWIDTH 110 1ps 1 NOISE PHASE 2ps SNR = 20 log 10 2 ft 100 jitter 16 BITS TE (dB) A 90 WIDEBAND 14 BITS NOISE 10338-006 80 Figure 6. Frequency Domain View

12 BITS ENOB

O NOISE R O NOISE 70

LT Multiplication in time is convolution in the frequency domain. 10 BITS 60 Therefore, any skirt on the clock is applied to the digitized

SIGNA 50 signal. This increases the EVM of the signal and degrades IF SAMPLING ADCs 40 ANALOG FREQUENCY 70MHz TO 300MHz, overall performance. The amount convolved onto the sample SNR 60dB TO 80dB signal depends on the relationship of the analog frequency to 30 1 10 100 1000 the sample frequency.

FULL-SCALE ANALOG INPUTFREQUENCY (MHz) 10338-004 fsignal Figure 4. Theoretical SNR and ENOB Due Jitter as a Function of Full-Scale SampledOutput = lClockSigna + )log(20 Sinewave Analog Input Frequency fclock Effect of Slew Rate Increasing the slew rate of the clock edge reduces the effects of noise and jitter by leaving the circuit less exposed. On the other hand, a faster slew rate increases the difficulty of circuit design, may cause electromagnetic interference (EMI) issues and may cause interference in other circuits. Note that an oscilloscope with very low input capacitance is needed to accurately measure Rev. 0 | Page 3 of 8 MT-200 Applications Engineering Notebook

–120 The spur is at −74.1 dBc as determined by the following –120 –125 equation: 62.30 –130 +− log(2066 −= 1.74) dBc 78 –135 –10 –140 –20

–145 –30 PHASE NOISE (dBc/Hz) PHASE –150 –40

–50 –155 dBc –60 –160 10 100 1k 10k 100k 1M 10M 100M –70 FREQUENCY (Hz) –80

–90

–100 30.25 30.50 30.75 31.00 31.25

FREQUENCY (MHz) 10338-009 Figure 9. 30.62 MHz Signal when Sampled with a Noisy Clock Clock designers typically provide a phase noise, but not a jitter L specification. The phase noise specification can be converted to jitter by first determining the noise on the clock and then comparing noise to the main clock component using small angle math. DESIRED SIGNA The phase noise power is integrated by calculating the gray area PHASE PHASE NOISE NOISE in Figure 10. SKIRTS SKIRTS 10338-007 Figure 7. The Noise Convolved onto the Sampled Signal Depends on the rise Vphase_noise Relationship of the Analog Frequency to the Sample Frequency Ф ≈ run = Vmain_clock

PHASE DOMAIN VIEW MODULATION ANGLE Ф Phase noise is cause by variations in the time period between MAIN each clock cycle. The end result is that the clock signal varies COMPONENT PHASE NOISE OF CLOCK COMPONENT around a fundamental frequency. This spread of frequencies OF CLOCK will degrade the ADC’s SNR.

ANGULAR RATE OF ENCODE CLOCK

SAMPLE INSTANT: PHASE = 0 i.e. POSITIVE GOING ANGULAR RATE OF 0 CROSSING ENCODE CLOCK INTEGRATE TO ENCODE BANDWIDTH –160 PHASE NOISE (dBc/Hz) PHASE

PHASE, 10k 100k 1M 10M 100M 1G FREQUENCY AND (Hz) 10338-010 AMPLITUDE NOISE ON CLOCK Figure 10. Integrating the Noise from Close-In to the Clock Out to the 10338-008 Bandwidth of the Encode Figure 8. Phase Domain View of Jitter The height is −160 dBc and the width is 10 KHz to 245.76 MHz. In the example shown below, a spur is added to a 78 MHz Therefore, 10×log(245.7e6 − 10e3) = 83.9 dB and −160 + 83.9 dB clock at level of −66 dBc and is used to control an ADC = 76.1 dBc of integrated noise. sampling a 30.62 MHz analog signal.

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6 3 PNoise −= dBc Hz + −=×−× 1.76100.101076.245log(10/160 dBc

PNoise 10/ = − 10/1.76 −4 Jitterphase ×≅ 102 ×= 102 ×= 10217.2 radians for small angles

Jitter ×10217.2 −4 Jitter = Phase = = 1435. pS 6 2πfOsc π ×× 1076.2452 At different offsets from the carrier, the slope of the noise can 2 + 10 × log(30 )M=- 87.3 dBc be different. For example, the A1 region is typically 1/f noise while the A4 region is considered broadband noise. RSS 10^(−87.9/10)+10^(−85.2/10)+10^(−87.3/10) = −81.7 dBc PNoise = −81.7 dBc

PNoise 10/ = − 10/7.81 Jitterphase ×≅ 102 ×= 102 = INTEGRATE TO ENCODE BANDWIDTH ×10163.1 −4 radians

A1 A2 A3 A4 for small angles −4

11 Jitter ×10163.1 10k 100k 1M 10M 100M 1G Jitter = Phase = = 151. fS 2πf 6 (Hz) 10338-0 Osc π ×× 10122882 Figure 11. Case Where Noise Varies Across Frequency Range The calculated value is close to the measured value of 158 fS. A = Area = integrated phase noise power (dBc). SOLUTIONS FOR CLOCKING CONVERTERS The jitter can be determined by integrating the noise from A phase locked loop (PLL) can be used to lock the reference close-in to the clock out to the bandwidth of the encode. The clock output to the desired frequency. Figure 12 shows a frequency range must be broken down into smaller bands and reference clock with high noise at a bandwidth of about added together to get the total. 100 kHz. The green and two blue traces are noise sources in A = 10 log10 (A1 + A2 + A3 + A4) an AD9516 clock generator. The red trace is the noise of the external reference feeding the AD9516. The brown trace is A the total noise of the AD9516. The graph shows that the dirty Rms phase jitter (radians) ×≈ 102 10 reference clock is the reason for the noise problem. A –40 REFERENCE CLK NOISE 10 FINAL AD9516 OUTPUT NOISE (PECL OUTPUT) ×102 VCO NOISE Rms jitter (seconds) ≈ –60 AD9516 PLL NOISE 2πfOsc LOOP FILTER NOISE REF-IN OPEN LOOP –80 fOsc = oscillator frequency

–100

10 k to 100 k –120 (−133.5 + −141.6) = −137.5

PHASE NOISE (dBc/Hz) PHASE –130 2 + 10 × log(90 k)=−87.9 dBc –160

100 k to 1 M –180 10 100 1k 10k 100k 1M 10M 100M

(−141.5 + −147.8) = −144.7 FREQUENCY (Hz) 10338-012 2 + 10 × log(900 k)=−85.2 dBc Figure 12. Jitter Caused by Dirty Reference Clock In this example, a PLL is used to filter the output of the 10 M to 40 M reference clock. The PLL bandwidth is set to 30 Hz and a good quality VCXO is used. The PLL removes the unwanted (−161.7 + −162.5) = −162.1 jitter from the recovered system clock as shown in Figure 13.

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–75

–85

–95

–105

–115

PHASE NOISE (dBc/Hz) PHASE –125

–135

–145

–155 1 10 100 1k 10k 100k 1M

FREQUENCY (Hz) 10338-013 Figure 13. PLL Removes Unwanted Jitter In this example, an ADF4002 is used as the PLL to clean the recovered input reference clock. The AD9516 clock generator is then used to produce multiple clocks. Tx LO EXT

ZIF OR CIF UP DAC TO 184MHz EXTERNAL PA Tx DLK RF OUTPUT π 0dBm TO +10dBm 90 PIN AD9122 ATTN DIODE

DAC ADL5541 ADL5320

ADL5375 DAC

AD5601/AD5611/ AD5621

AD8375 ATTENUATED π RF OUTPUT ADC ATTN AD9434 AAF ADL5367/ IMAGE REJECT TYPICAL ADL5365 IF-184MHz AD9516 CLOCK GENERATION, NETWORK FANOUT, CLKOUT DISTRIBUTION PLL

ADF4150 + ADF4002 + ADCLK925 VCO VCXO ADF4002 + VCXO ADCLK905 PLL ADF4350 PLL PLL CLOCK CLEANUP Rx LO EXT (61.44MHz) CLOCK LO CLEANUP GENERATION, (13.0MHz) FANOUT, POWER DISTRIBUTION TO SPI DIRECT SPI FROM FPGA DEVICES SPI BRIDGE TO DEVICES WITH CONTROL PINS

USB LOCAL SPI MCP23S17 (OPTIONAL) CLOCK MASTER MICROCONTROLLER 16-BIT PORT EXPANDER REF IN CLOCK (n × 30.72MHz) OUT AUX USB INTERFACE

NOISY INPUT CLEAN UP REFERENCE INPUT NOISE CLOCK 10338-014 Figure 14. The AD9523, AD9524, and AD9523-1 clock generators integrate the functions of jitter clean and clock generation/distribution into a single device. The AD9524 device has seven outputs while the AD9523 and AD9523-1 have 15 outputs.

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Tx LO EXT

ZIF OR CIF UP DAC TO 184MHz EXTERNAL PA RF OUTPUT Tx DLK π 0dBm TO +10dBm 90 PIN AD9122 ATTN DIODE

DAC ADL5541 ADL5320

ADL5375 DAC AD5601/AD5611/ AD5621

AD8375 ATTENUATED π RF OUTPUT ADC ATTN AD9434 AAF ADL5367/ IMAGE REJECT TYPICAL ADL5365 IF-184MHz

NETWORK CLKOUT PLL

ADF4150 + CLOCK SYNTHESIS VCO AND DISTRIBUTION ADF4002 + VCXO ADCLK905 PLL ADF4350 PLL PLL CLOCK CLEANUP Rx LO EXT (61.44MHz) LO CLEANUP (13.0MHz) POWER TO SPI DIRECT SPI FROM FPGA DEVICES SPI BRIDGE TO DEVICES WITH CONTROL PINS AD9523 USB LOCAL SPI MCP23S17 (OPTIONAL) CLOCK MASTER MICROCONTROLLER 16-BIT PORT EXPANDER REF IN CLOCK (n × 30.72MHz) OUT AUX USB INTERFACE

NOISY INPUT INTEGRATED CLOCK CLEAN UP,

REFERENCE CLOCK GENERATION, FANOUT 10338-015 Figure 15. The driver design of the Analog Devices AD9523, AD9524, and AD9523-1 offer multimode output which means that it’s possible to use a common 100 Ω differential resistor and change a register value to change from LVPECL, LVDS, and HSTL signal formats. Each signal format has advantages and disadvantages as shown in the charts below. All signal formats have different voltage swings. Select the format with best swing for the application but remember that a lower swing uses less power.

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3.3V

GND 10338-017 Figure 16.

Table 1. LVPECL Signal Format Pros and Cons Pros Cons quasidifferential high power high slew rates requires a bipolar device that is not available on CMOS processes can accept near/far termination fanout capability relatively quiet such that it doesn’t corrupt other signals easily

3.5mA

10338-016 Figure 17.

Table 2. LVDS Signal Format Pros and Cons Pros Cons true differential low signaling (±0.4 V) often does not yield highest slew some variants can accept near/far termination care needs to be taken to insure aggressor signals equally couple to differential LVDS lines quiet such that it doesn’t corrupt other signals easily low power rates at receiver resulting in higher noise than LVPECL

Table 3. CML Signal Format Pros and Cons Pros Cons true differential common mode voltage near ground or VCC high slew rate particularly suitable for the most demanding applications quiet

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