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Chapter 8 Ed For the mechanical is Chapter 8 ed. example, path showing parts missing. The descriptive path shown proceeds from the PDP-8 computer to the processor and from there to the arithmetic unit, or more Structural Levels of the PDP-S^ specifically, to the Accumulator (AC) register of the arithmetic unit. Next, the logic implementing the register transfer operations C. Gordon Bell / Allen Newell / and functions for the jth bit of the Accumulator is given, followed and needed for this Daniel P. Siewioi'ek by the flip-flops gates particular implementa- tion. Finally, on the last segment of the path, there are the electronic circuits and components from which flip-flops and gates A map of the PDP-8 design hierarchy, based on the Structural are constructed. Levels View of Chap. 2, is given in Fig. 1, starting from the PMS structure, to the ISP, and down through logic design to circuit Abstract electronics. These description levels are subdivided to provide Representations more organizational details such as registers, data operators, and 1 also lists some of the methods used to represent the functional units at the register transfer level. Figure physical computer abstractly at the different description levels. As The relationship of the various description levels constitutes a mentioned only a small part of the PDP-8 description tree structure, where the organizationally complex computer is previously, tree is represented here. The many documents which constitute the top node and each descending description level represents the complete representation of even this small computer include increasing detail (or smaller component size) until the final circuit wiring lists, circuit schematics, printed circuit element level is reached. For simplicity, only a few of the many logic diagrams, board photo etching masks, production description diagrams, possible paths through the structural description tree are illustrat- production parts lists, testing specifications, programs for testing and diagnosing faults, and manuals for modification, production, 'Originally printed in C. G. Bell, J. C. Mudge, and J. E. McNamara, and use. As the discussion continues down the Computer Engineering: A DEC View of Hardware System Design, Digital maintenance, will that the tree Press, 1978, pp. 209-228. abstract description tree, the reader observe |X| indicates (igurs numb*r of instanc* Fig. 1. PDP-8 hierarchy of descriptions. no Chapter 8 Structural Level* of the PDP-8 | 111 conveniently represents the constitutent objects of each level and The I/O Bus is nearly the same for the PDP-5, 8, 8/S, 8/1, and their interconnection at the next level. highest 8/L. Hence, any controller can be used on any of the above there is computers provided an appropriate logic level converter The PMS Level and 8/S (PDP-5, 8, use negative polarity logic; the 8/1 and 8/L, - The I/O Bus is the link to the The PDP 8 computer in PMS notation is: positive logic). controllers for processor-controlled data transfers. Each word transferred is a C[PDP-8 technoIogy:transistors: 12 b/w: designated by processor in-out transfer (lOT) instruction. Due ' ' ' to the cost of descendants: PDP-8/S, PDP-8/I, PDP-8/L, high hardware in 1965, the PDP-8 I/O Bus protocol was '8/E, '8/?, '8/M, '8/A, 'CMOS-8; designed to minimize the amount of hardware to interface a antecedents: ' PDP-5; peripheral device. As a result, only a minimal number of control were defined with the Mp[core; #0:7; 4096 words; tc:1.5 |As/word];] signals largest portion of I/O control Pc(Mps(2 to 4 words); performed by software. A detailed structure of the instruction length: 1|2 words; processor and memory (Fig. 4) shows the I/O Bus and Data Break address/instruction : 1 connections to the ; registers and control in the operations on data:(=, +, Not, And, Minus notation used in the initial PDP-8 reference manual. This is a (negate), Srr l(/2), Sir 1 (x2), +) diagram essentially functional block diagram. The for a optional operations:(x ,/,nomialize); corresponding logic controller is given in Fig. 3 in terms of elements data-types:word, integer. Boolean vector; logic design (ANDs and ORs). The operation of the I/O Bus starts when the operations for data access:4); processor sends a control signal anr) sets the six I/O selection lines P(display; '338); (lO. SELECT <0:5>) to specify a particular ' controller. Each is P(c; LINC); controller hardwired to respond to its unique ' 6-bit code. The local S( I/O Bus; 1 Pc; 64K); control, K[k], select signal is then used to ' form three local commands when ANDed with the three lOT Ms(disk, DECtape, magnetic tape);" command lines from the processor. These command lines are T(paper tape, card, analog, cathode-ray tube) called lO. PULSE. 1, 10.PULSE.2, and IO.PULSE.4. Twelve data bits are transmitted either to or from the As an example of PMS structure, the LINC-8-338 is shown in processor, indirectly 2; it consists of three under the controller's control. This is the Fig. processors (designated P): Pc(' LINC), accomplished by using and AND/OR gates in the controller for data to the PcC PDP-8), P.display('338). The LINC processor is a very input processor, and the AND for data to the controller. capable processor with more instructions than the PDP-8 and is gate input A single skip is used so that the can test a available in the structure to interpret programs written for the input processor status bit in the LINC. Because controller. A controller communicates back to the of the rather limited instruction set being processor via the line. controller interpreted, one would hardly expect to find all the components interrupt request Any wanting attention ORs its into the present in Fig. 2 in an actual configuration. simply request signal interrupt request signal. The switches Normally, the controller an is (S) between the memory and the processor allow signal causing interrupt also connected to the and instructions are eight primary memories (Mp) to be connected. This switch, in skip input, skip used in the PMS called software polling that determines the S(' memory Bus; 8 Mp; 1 Pc; time-multiplexed; 1.5 specific interrupting device. The Data Break jis/word), is actually a bus with a transfer rate of 1.5 microseconds input for Direct Memory Access provides a word. The switch makes the direct access path for a processor or a controller to via the per eight memory modules logically memory The number of equivalent to a single 32,768-word memory module. There are processor. access ports to memory can be two other connections expanded to eight the DM01 Data a (a switch and a link) to the processor by using Multiplexer, ' switch. the console. are ' The DM01 port is from a excluding They the S( I/O Bus) and L( Data requested processor (e.g. , LINC Break; Direct or Model 338 Display Processor) or a controller Memory Access) for interconnection with peripher- (e.g.; magnetic al A or controller a devices. Associated with each device is a switch, and the I/O tape). processor supplies memory address, a read Bus links all the devices. or write access request, and then or data for the A simplified PMS diagram (Fig. 3) shows accepts supplies the accessed word. In the structure and the logical-physical transformation for the I/O configuration (Fig. 1), Pc['LINC] and ' P[ 338] are connected to the Bus, Memory Bus, and Direct Memory Access link. Thus, the I/O multiplexer and make requests to for both Bus is: memory their instructions and data in the same way as the PDP-8 processor. The global control of these processor ' programs S( I/O Bus duplex; 1 is time-multiplexed; Pc; 64K;Pc controlled, via the processor over the I/O Bus. The processor issues start K requests; t:4.5 n,s/w) and stop commands, initializes their state, and examines their Section 3 of Historical 112 Part 1 Fundamentals Computers Significance TIT.WvM- 10 ch.r/s. » b/ch«r. »4 ch.rl zy T(pap«r tape lr«ad«( 300 char/i | (punch 100ch»r/sl 8 b/char) 01 T(.ncr«m«nt«l pent plot 300 point/s. in/ point) Tlcafd. rMder. 200 800 c»rd/m>nl Kcard punch, 100 card/mm) •r, 300 lin«/fT 120 col/lin* n I T (l,n«. prii chT//coll ULI I 64 display araa 10 x 10 m^i 6 X 5 01 I 05 m/potnt) UJ I 3.S/s/potnt TIDaiaphone. 12-48 kb/sl Ltanatog output. - hEHIH U(»0 63, analog, input -10 volial 03-EH Kl#0 63. Teletvp*. 110, 180 b/«l ECtapa, addrassabla magnattc tap* ' - I 133 260 ft. 350 char/in, 3 b/chai I LLI I liS/w englh D- (#0 7. magnatic tapa. 36 45 75' 112 5 in/- iG-EI-E200,556,800 b/in 6 8 b/chail D- ^H_ .III. Wsl#0WsliiiO 3. hsadftsad haad disk. 1 dalay 0-17 ms, 1 S — 66 ^s/w. 32768 vvl (166 Ms/w 26214 K I 1 I "t—J ^J (12. 1 pantv)b/w)pantvlb/w) X 10 in^ P(dtsplav. 33tl -| T(#0 3. CRT, display, area 10 y* T(0 3, light, pan) I TIiKO 3. push buttons, consolal y- Pc( Laboratory nsirumant Computar/LINC) 1. LINNCtapa, addrassabla magr>atic tape. 6 25kw/s IMsliVO y I T(ifO 15. knobs, arulog. input) 1 Mp (core. 1 5 i-s/w, 4096 w.
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