Editorial Jane C. Blake, Editor Helen L. Patterson, Associate Editor Kathleen M. Stetson, Associate Editor Circulation Catherine M. Phillips, Administrator Sherry L. Gonzalez Production Terri Autieri, Production Editor Anne S. Katzeff, Typographer Peter R. Woodbury, Illustrator Advisory Board Samuel H. Fuller, Chairman Richard W Beane Donald 2.Harbert Richard J. Hollingsworth Alan G. Nemeth Jeffrey H. Rudy Stan Smits Michael C. Thurk Gayn B. Winters The Digital TecbnicalJoutnnl is published quarterly by Digital Equipment Corporation, 146 Main Street ML01-3/B68, Maynard, Massachusetts 01754-2571. Subscriptions to the Journal are $40.00 for four issues and must be prepaid in U.S. funds. University and col- lege professors and Ph.D. students in the electrical engineering and computer science fields receive complimentary subscriptions upon request. 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Abstracting with credit of Digital Equipment Corporation's authorship is permitted. All rights reserved. The information in theJournal is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in theJortrnnl. Documentation Number EY-J886E-DP The following are trademarks of Digital Equipment Corporation: ACMS, ALL-IN-1,Alpha AXE the AXP logo, AXT: DEC, DEC 3000 AXE DEC 4000 AXI: DEC 6000 AXI: DEC 7000 AXp DEC 10000 AXl? DEC DBMS for OpenVMS, DEC Fortran, DEC OSWl AXE DEC Pascal, DEC RAL1.Y- DEC Rdb for OpenVMS, DECchip 21064, DECnet, DECnet for OpenVMS &XI: DECnet for OpenVMSVAX, DECnet/OSI, DECnet-VAX, DECstation, DECstation 5000, DECwindows, DECWORLD, Digital, the Digital logo, DNA, OpenVMS. OpenVMS AXI: OpenVMS RMS OpenVMS VAX, PDP-11, Q-bus, Thinwire, TURBOchannel, IJLTRM, VAX, VAX-11/780, VAX 4000, VAX 6000, VAX 7000, VW 8700, VrLv 8800, VAX 10000, VAX Fortran, VAX Pascal, VMS, and VMScluster. CMY-I is a registered trademark of Cray Research, Inc HP is a registered trademark of Hewlett-Packard Company. Cover Design IBM is a registered trademark of International Business Machines, Inc. The DECchip 21064, the fzrst implementation LSI Logic is a trademark of LSI Logic Corporation of Digitalk Alpha AXP computer architecture, Macintosh is a registered trademark of Apple Computer, Inc. is the world'sfastest single-chip micropocessolr MIPS is a trademark of MIPS Computer Systems, Inc. Represented on our couer by the RrlP logo, the Motorola is a registered trademark of Motorola, Inc. DECchip takes its phce among sywzbols of other OSWl is a registered trademark of Open Software Foundation, Inc. dewicesfrom computing history, including PAL is a registered trademark of Advanced Micro Devices, Inc. the vacuum tube, apuncb card, sketches of SPEC, SPECfp, SPECint, and SPECmark are registered trademarks of the Standard Bubbagek Analytical Engine, a wheel from the Performance Evaluation Cooperative. ~aciculke,and an abacus. SPICE is a trademark of the University of California at Berkeley The cover was aksi~nedby Deborah Fulck oJ UNIX is a registered trademark of UNM System Laboratories, Inc. Digital's Corporate Human Factors Group ,with Windows and Windows NT are trademarks of Microsoft Corporation. the help of Knzn Design. Book production was done by Quantic Communications, Inc Contents 17 Forauord Robert M. Supnik Alpha AXP Architecture and Systems 19 Alpha AXP Architecture Richartl L. Sites 35 A 200-MHz 64-bitDual-issue CMOS Microprocessor Daniel W Dobberpuhl. Richard T. Witek. Randy Allrnon. Robert Anglin, Davitl Bertilcci. Sharon Britton, Lintla Chao, liobert A. Conrad, Daniel E. [)ever, Bruce Gieaeke, Soha M.N. H;lssoun, Gregory W. Hoeppnel; KathrynKuchler, Maureen Ladtl, Burton M. Lear): Liam Madden, EtlwardJ. McLellan, Derrick R. Meyer, James Montanaro, Donald A. Priore, Vidya Rajagop:~l;~n,Sridhar Sarnucl~~l;~, and Sribal:~nS;lnrIianam 51 The Alpha Demonstration Unit:A High-performance Multiprocessorfor Sopware and Chip Development Charles I? Thacker, David G. Conro!: ;lnd Lawrence C. Stewart 66 The Design of the DEC3000 AXP Systems, Two High-performance Workstations Todd A. I)i~tton,Daniel Eiref, Nlrgh R. K~rrth,JnmesJ.Reisert, ant1 Robin I,. Ste~vart 82 Design and Performance of lhe DEC 4000 AXP Departmental Server Computing Systems Barry A. M;~skas,Stephen E Shirron, and Nicholas A Wlrcliol 100 Technical Description of the DEC 7000 and DEC 10000 AXP Family Brian R. Allison and Catharine van Ingen 1 11 Porting OpenVMS from VAX to Alpha AXP Nancy P Kronenbrg, Thomas R. Benson, Wayne M. (hrtloza, Ravindran J;~jian~~atlian, ant1 BenjaminJ. Thomas Ill 12 1 The GEM Optimizing Compiler System Davitl S. Hlickstein, Peter W Craig, <:aroJine S. Davidson, R. Neil Riman,Jc, Kent D. <;lossop, Richartl H.Grove, Steven 0.I-lobbs, and William H. Noyce 137 Binary Translation Richard L. Sites, Anton Chernoff. Mattliew B. Kirk, M;~uriceP Marks, and Scott (;. Robinson 153 Porting Digital's Database Management Prodzrcts to the Alpha AXP Platforrn Jeffrey A. Coffler. Zia Mohatnecl, and I'eter M. Spiro 165 DECnet for OpercVMS AXP: A Case History James V. (:olombo, Pamela). Rickard, ant1 Paul Benoit 181 Using Simzrlation to Develop and Port SoJfu)are George A. 1):lrcy 111, llonaltl F, Rrcntlel; SrcphenJ. Morris, ;~ntl~Michacl V. IIcs AIpha AXP Program Management 193 Enrollment Management, Managing the Alpha AXP Program Peter E Conklin I Editor's Introduction req~~irements:~nd to allow :~pplicationflexibility The result of their design efforts is a microproces- sor that operates at speeds up to 200 MHz-the fastest commercially available chip in the industry Early implementations of this chip became part of a prototype system, the Alpha Demonstration Unit. As Chuck Thacker, Dave Conro): and Larry Stewart explain in their paper, the prototype servecl the overaII Alpha ,tYl' program by giving software devel- opers early access (ten months) to AXP-compliant hardware. Because of tlie architectural emphasis on Jane C. Blake multiple processors, prototype designers focused Editor on delivering a robust multiprocessing system. The ;iuthors tliscuss the significance of tlie choice of a backplane interconnect for a multiprocessor, corn- 'T'his special issue of tlie Digit~llTeclnrlical Jourf1crl pare different ;ipproaches to cache coherence, ancl presents the computer architecture that Digital describe the system modules and packaging. believes will become the universal platform for With constraints different from those of the pro- computing over the next 25 years. A signific;uit totype, the li;~rdwareprocloct projects are repre- ~liilestonein the comp;cny's history the i\lplia ASP sentetl here b), three different implementations: architecture arises out of Digital's extensive etigi- desktop, departmental, and data center systems. In neering experience antl puts into place a cohesive, the desktop area, the I>EC 3000 UPfamily of work- .I'lexible framework for high-perform:~nce 64-bit stations are balanced u~iiprocessorsyste~ns. Totlcl IlISC computing. This issue contains papers repre- Dutton, Dan Eiref, Hugh Kurth. Jim Reisert, and sentative of the scope of tlie program across Iiobin Stewart review tlie rlecision to replace the Digital's Engineering organization, including hartl- traditional common system bus with a crossbar \\?;Ire systems, an operating system, compilers, system intercontiect constructetl of ASI(:S. This new binary tr;~nslators,network ant1 database software, interconnect allorved the designers to meet the and simulators. goals of Low memory latency, high memory band- The results of the engineering efforts cliscusscd width, ;~nd~>ii~ii~nal (:I'll-I/O memory contention in in these papers reflect three primary goals fix a cost-competitive manner. tlie Alpha AXI' architecture: high performance, The I>EC 4000 AXI' system is a tlepartmental longevit!; and e;~symigration from tlie 32-bit VAX server that iniplements the IEEE Futurebus+ stan- VMS computer line. Dick Sites, one of the chief tlard. Barry Maskas, Stephen Shirron, and Nick Alpha AXl' architects, 1i;rs written a definitive p;cper Wrcliol present tlie reasoning behind the system th;lt explains how key architectural decisions were architecture antl technology decisions that resulted made relative to the gonls. He reviews the similari- in the ;~chievementof optimized uniprocessor per- ties and differences between the UP;rrcIiitecti~re form;ince, tlu;rl-l>rocessorsymmetric multiprocess- and other RIS<: ;crchitectures, ant1 then presents ing, and baJ;uiced 1/0 tlirouglipi~t.lletnils of the details of-'the design, including data and instruction subsystems that make up this expanditble modular formats. In