A Cascaded DC-AC-AC Grid-Tied Converter for PV Plants with AC-Link

electronics

Article A Cascaded DC-AC-AC Grid-Tied Converter for PV Plants with AC-Link

Manuel A. Barrios 1,2,* ,Víctor Cárdenas 1 , Jose M. Sandoval 1, Josep M. Guerrero 2,* and Juan C. Vasquez 2

1 Engineering Department, Autonomous University of San Luis Potosi, Dr. Manuel Nava No. 8, Col. Zona Universitaria Poniente, San Luis Potosí 78290, Mexico; [email protected] (V.C.); [email protected] (J.M.S.) 2 Center for Research on Microgrids (CROM), Department of Energy Technology, Aalborg University, 9220 Aalborg, Denmark; [email protected] * Correspondence: [email protected] (M.A.B.); [email protected] (J.M.G.)

Abstract: Cascaded multilevel converters based on medium-frequency (MF) AC-links have been proposed as alternatives to the traditional low-voltage inverter, which uses a bulky low-frequency transformer step-up voltage to medium voltage (MV) levels. In this paper, a three-phase cascaded DC-AC-AC converter with AC-link for medium-voltage applications is proposed. Three stages integrate each DC-AC-AC converter (cell): a MF square voltage generator; a MF transformer with four windings; and an AC-AC converter. Then, k DC-AC-AC converters are cascaded to generate the multilevel topology. This converter’s topological structure avoids the per-phase imbalance; this simpliﬁes the control and reduces the problem only to solve the per-cell unbalance. Two sets of simulations were performed to verify the converter’s operation (off-grid and grid-connected modes). Finally, the papers present two reduced preliminary laboratory prototypes, one validating

the cascaded configuration and the other validating the three-phase configuration. Keywords: AC-link; medium-frequency magnetic link; photovoltaic; multilevel converter; cascaded Citation: Barrios, M.A.; Cárdenas, V.; Sandoval, J.M.; Guerrero, J.M.; converter; AC-AC converter; matrix converter Vasquez, J.C. A Cascaded DC-AC-AC Grid-Tied Converter for PV Plants with AC-Link. Electronics 2021, 10, 409. https://doi.org/10.3390/ 1. Introduction electronics10040409 At the end of 2019, the global renewable generation capacity was 2537 GW. Solar energy was the renewable energy with the most significant growth reaching a global Academic Editor: Francisco Gordillo capacity of 586 GW (23% of the global renewable generation capacity) [1] According to Received: 8 January 2021 the global weighted-average levelized cost of energy (LCOE), the cost for electricity from Accepted: 4 February 2021 utility-scale photovoltaics (PV) plants has fallen 82% in the last decade. Similarly, crystalline Published: 8 February 2021 solar PV modules’ price has fallen 90% in Europe in the same period [2]. The fall in prices and the photovoltaics’ growth in the last years have required tech- Publisher’s Note: MDPI stays neutral nologies and innovations advances in power electronic converters to connect large-scale with regard to jurisdictional claims in PV power plants to the grid. Nowadays, the most widespread utility-scale topology to published maps and institutional affil- interface solar PV modules to the medium-voltage (MV) grids is the two- or three-level iations. low-voltage (LV) centralized inverter [3–5]. This topology commonly consists of multiple PV arrays (the number of PV modules could easily reach millions of them [6]) attached to a DC-DC converter, increasing the PV array voltage and correctly feeding the low-voltage centralized inverter. Finally, a low-frequency (LF) transformer steps up the LV AC to Copyright: © 2021 by the authors. generate the required voltage for a utility-scale grid (6–36 kV) [7–11]. Licensee MDPI, Basel, Switzerland. This classic configuration faces some disadvantages. The main drawback is the line- This article is an open access article frequency transformer. Even though manufacturers are trying to reduce and optimize distributed under the terms and the transformer’s space and volume, it is still huge, making installation and maintenance conditions of the Creative Commons complex and expensive [8,12,13]. Attribution (CC BY) license (https:// Another issue is the limitation (normativity and insulations) to 1 kV on the DC side. In creativecommons.org/licenses/by/ addition, a high total harmonic distortion (THD) makes the use of line-frequency passive 4.0/).

Electronics 2021, 10, 409. https://doi.org/10.3390/electronics10040409 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 409 2 of 21

filter mandatory; nevertheless, due to the medium-frequency switching harmonics and high current levels, the filter’s efficiency is impaired. As it was mentioned, the main problem with the classic configuration is the large transformer; hence, other works have tried to stay away from using it [14–17]. Thus, transformerless alternatives have been considered. These alternatives consist of using high-rated switches, but even with the state-of-the-art switches (6.5 kV), there is a limit in the inverter’s AC output voltage; in the best case, it could be 3.582 kV. Another possibility of implementing the classic configuration to reach MV levels involves the series connection of multiple high-rated switches. This approach brings its challenges: problematic physical construction, intricate gate driver design, use of snubber networks, large filters, and high conduction losses due to the on-state voltage drop [18]. Multilevel converters have been proposed and used to overcome some of the pre- viously discussed problems [12,19–23]. Multilevel converters show interesting features like direct integration to the MV grid if a suitable number of levels are applied; therefore, this converter could be considered a transformer-less converter for MV-grid integration [11,24,25]. Due to the high number of levels in a staircase form, the waveform in the converter’s output is closer to a sinusoidal signal; this implies that the THD could be minimal [10,25,26]. The two formers features can be achieved without using high-rated voltage switches; in other words, to achieve the MV levels and a low THD, commercial switches can be implemented [10]. The only issue to overcome is that the voltage required will increase accordingly to the MV-grid level. Several multilevel converters have been proposed since the seventies, such as diode clamped also known as neutral point clamped (NPC), flying capacitor (FC), cascaded h-bridge (CHB), and the modular multilevel converter (MMC), among others. Still, the previous four are fundamental structures [27]. The diode clamped remains in use in the industrial environment [28,29]. The number of voltage levels produced by this converter is m, and requires m − 1 capacitors [30]. The capacitors are used as DC sources; therefore, the switches must block the capacitor’s voltage. The flying capacitor’s output levels are generated by the capacitors that float with respect to the ground potential; hence, the switch must block this voltage [31,32]. This topology provides redundant switching states that can balance the voltage in the flying capacitors [33]. The CHB converter is built cascading k full-bridge converters and requires multiple isolated DC sources [30]. The number of levels m and DC sources k are related as m = 2k + 1; therefore, a high number of DC sources are required [34]. PV farms commonly use multiple PV strings, and each PV string generates its own DC voltage. The MMC converter provides an alternative multilevel topology [35,36]. Three legs integrate an MMC converter, and each leg has two arms, and each arm has k cascaded converters; the MMC has a common DC source. The most common implementation is the HB converter. The main drawback in the use of MMC includes the circulating current between legs. The newest and more complex multilevel converters are based on these four, and in some applications, the line-frequency transformer is required by means of isolation, normativity, or security. The sizing and design methods for eleven cascaded multilevel converter (CMC) were addressed in reference [20]. The authors also provide considerations and a detailed procedure for the power stage. A three-cell seven-level CHB was evaluated in reference [19], and the control method was based on traditional voltage-oriented control. This standard control scheme required the addition of two stages: one stage considers the maximum power point tracking (MPPT) for each module or string, and the other stage controls the DC-link voltages drift. In reference [22], a current-control technique and the switching scheme of a cascaded five-level inverter with a single-phase photovoltaic grid- tied system were introduced. In reference [23], a cascaded H-Bridge multilevel converter for photovoltaic systems without voltage or current sensors at the DC-side was proposed. The effectiveness of the proposed structure was experimentally validated on a 2 kW single- phase seven-level CHB laboratory prototype. Electronics 2021, 10, 409 3 of 21

In the last decade, MF transformers have been considered to minimize the size and weight of the line frequency transformers in traditional PV farms connected to the grid; but this MF link requires an additional step to transform the MF-AC square voltage to line-frequency AC voltage. There are two options to perform the frequency transformation: the first option is a two-step power conversion (AC-DC/DC-AC), in which a MF rectifier produces a new DC link that feeds an inverter converter [37,38]. Reference [12] presents a high-performance solution based on a power electronic transformer (PET); it included a medium-frequency transformer, DC-links, and multilevel converters on the low-voltage or on the high-voltage side. In reference [21], a high-frequency link-cascaded medium- voltage converter was proposed for direct grid integration of renewable sources. The common magnetic link generates several isolated and balanced DC sources for feeding all the h-bridge inverter cells of the MMC converter. A direct stage conversion (AC-AC) is the second option to transform an MF-AC voltage to low-frequency AC voltage [39–43]. In reference [44], a direct method conversion was implemented. The converter has four stages of energy conversion: DC-DC/DC- AC/AC-AC/AC-AC. The converter uses a switching frequency of 2880 Hz and the work focuses on the designing and operation of the converter under unbalanced insolation. Finally, presenting an experimental test: in three-phase (3PH) and in single-phase (1PH) cascaded configuration, in which it reports an operating of 450 W. Besides, there are tests to validate the zonal power balancer, but there are not close-loop experimental tests of the proposed converter neither in three-phase configuration nor cascaded configuration. This paper presents a multilevel medium-voltage power converter with MF-AC links that simplifies the grid integration of large-scale PV farms. This proposal overcomes some drawbacks related to grid-tie PV plants: use of line-frequency transformers and filters; avoiding using high-rated switches (>6.5 kW) or the use of series connection switches; elimination of the MF rectifying stage; and promoting modularity. This three-phase multilevel converter is built cascading some converters interconnected with each other via medium-frequency multiple winding transformers. These transformers generate a MF-AC link. In the primary side, there is only one winding sup- plied by a square-wave converter. There are three windings on the secondary side; each winding plus a suitable converter generates each of the three-phase output voltages. This topology has been selected because it has some exciting features: (1) It includes medium-frequency AC links (MF transformer). (2) MF switching, which allows the re- duction of passive elements. (3) AC-AC direct conversion from MF-AC voltage to LF-AC voltage eliminates the necessity of a medium-frequency rectifier. (4) Multiple DC links. (5) Multilevel output voltage that in consequence, permits interfacing with medium-voltage utilities with a low THD. (6) Does not require a line-frequency transformer. (7) Modularity (multiple DC-AC-AC converters can be cascaded) [45]. The rest of the document is organized as follows: Section2 describes the proposed converter topology, its modulation strategy, and the proposed converter’s design. Section3 discusses the three-phase multilevel converter’s control strategy. Section4 shows simulations to validate the operation of the proposed topology in open-loop under off-grid mode as well as in close-loop under on-grid mode. Section5 discusses experimental tests over two laboratory prototypes. Finally, in Section6, the discussion is presented.

2. Grid-Tied Converter with AC Link Besides many other state-of-the-art topologies, the one proposed in this paper is integrated by some conventional converters that combined present exciting features. In Figure1, the proposal multilevel grid-tied converter with MF-AC links is depicted in the form of a block diagram. The suggested converter facilitates the incorporation of utility-scale PV plants into the MV utility. Figure2 shows the block diagram of the conventional two-levels centralized converter for medium-voltage levels in comparison with the proposed converter. Electronics 2021, 10, x FOR PEER REVIEW 4 of 21

Electronics 2021, 10, x FOR PEER REVIEW 4 of 21

Electronics 2021, 10, 409 4 of 21 levels centralized converter for medium-voltage levels in comparison with the proposed converter. levels centralized converter for medium-voltage levels in comparison with the proposed converter.

FigureFigure 1. 1.A Acascaded cascaded three-phase three-phase (3PH) (3PH) DC-AC-AC DC-AC-AC converterconverter forfor utility-scale utility-scale photovoltalic photovoltalic (PV) (PV) farm. farm. Figure 1. A cascaded three-phase (3PH) DC-AC-AC converter for utility-scale photovoltalic (PV) farm.

FigureFigureFigure 2. 2. 2. Classic ClassicClassic configurationconfiguration conﬁguration toto interconnectinterconnect PV PVPV arrays arrays arrays to to to the the the medium-voltage medium-voltage medium-voltage (MV) (MV) (MV) grid. grid. grid.

ThisThisThis proposed proposed proposed topology topology isis built built cascading cascading kk kthree-phasethree-phase three-phase DC-AC-AC DC-AC-AC DC-AC-AC converters. converters. converters. Some Some Some convertersconvertersconverters integrateintegrate thisthis DC-AC-ACDC-AC-AC converter; converter; converter; one one one is is referred is referred referred to asto to theas asthe input the input converterinput converter converter and andandthe the othersthe othersothers as the asas outputthe output converters. converters.converters. The inputThe The input andinput outputand and output output converters converters converters are interconnected are are intercon- intercon- through a medium-frequency multiple winding transformer that isolates the PV arrays from nectednected throughthrough aa medium-frequency multiple multiple winding winding transformer transformer that that isolates isolates the the PV PV the utility. The multiple winding transformer involves four windings. The ﬁrst winding is arraysarrays fromfrom thethe utility.utility. The multiplemultiple windingwinding transformer transformer involves involves four four windings. windings. The The firstthe primary,winding and is the it isprimary, connected and with it is the connected input converter. with the The input rest converter. of the windings The rest integrate of the firstthe winding secondary; is thus,the primary, the secondary and it and is connected its corresponding with the output input converter converter. (each The winding rest of the windingswindings integrate integrate the secondary; thus, thus, the the secondary secondary and and its its corresponding corresponding output output con- con- verteris connected (each winding to one output is connected converter) to one generate output a converter) three-phase generate electrical a three-phase system. electri- verter (each winding is connected to one output converter) generate a three-phase electrical system.To cascade the DC-AC-AC converter and achieve the multilevel output voltage, the cal system. convertersTo cascade connected the DC-AC-AC to the MF transformers’converter and secondary achieve the windings multilevel are output cascaded voltage, with their the To cascade the DC-AC-AC converter and achieve the multilevel output voltage, the converterscorresponding connected windings to the from MF transformers’ other multiwinding secondary transformers. windings are The cascaded multilevel with output their converters connected to the MF transformers’ secondary windings are cascaded with their correspondingvoltage will present windings a low from THD other that dependsmultiwinding on how transformers. many converters The aremultilevel cascaded. output This work considers three cascaded converters to simplify the analysis and the simulations’ correspondingvoltage will present windings a low fromTHD thatother depends multiwinding on how manytransformers. converters The are multilevel cascaded. Thisoutput running time, but in general, the number of cascaded converters (cells) may be k. voltagework considers will present three a lowcascaded THD convertersthat depends to simplifyon how manythe analysis converters and theare simulations’cascaded. This workrunning considers time, but three in general, cascaded the convertersnumber of cascadedto simplify converters the analysis (cells) and may the be ksimulations’. running time, but in general, the number of cascaded converters (cells) may be k.

ElectronicsElectronicsElectronics2021 2021 2021,,10 10, ,10, 409 x, xFOR FOR PEER PEER REVIEW REVIEW 55 of5of of 2121 21

2.1.2.1. The The Single-Phase Single-Phase DC-AC-AC DC-AC-AC Converter Converter ToTo understandunderstand understand howhow how thethe the entireentire entire proposedproposed proposed topologyto topologypology works,works, works, FigureFigure Figure3 3 shows 3shows shows the the the block block block diagramdiagram ofof of thethe the DC-AC-AC DC-AC-AC DC-AC-AC converter converter converter in in ain single-phasea asing single-phasele-phase conﬁguration. configuration. configuration. The The The series series series connection connec- connec- oftiontion more of of more thanmore than one than 3PHone one 3PH DC-AC-AC 3PH DC-AC-AC DC-AC-AC converter co converternverter builds builds builds the multilevel the the multilevel multilevel structure. structure. structure.

1 1 : : n n

i i i i i + iDCDC 1 1 2 2 + VVPWMPWM −−

FigureFigure 3. 3. Block Block diagram diagram of of a a single-phasesingle-p single-phasehase DC-AC-AC DC-AC-AC converter.converter. converter.

TheThe blockblock block diagramdiagram diagram is is explainedis explained explained from from from left left left to to rightto right right because because because the the powerthe power power flow flow flow from from from the PVthe the plantPVPV plant plant goes goes ingoes that in in that direction:that direction: direction: • • TheThe PV PV modules modules are are thethe the firstfirst first stage;stage; stage; theythey they are are interconnectedinterconnected interconnected inin in serialserial serial parallelparallel parallel arraysarrays arrays toto to satisfysatisfysatisfy thethe the design design and and regulations’ regulations’ powerpower power levels.leve levels.ls. For For the the purposes purposes of of this this explanation, explanation, thethethe PVPV PV modulesmodules modules areare are replacedreplaced replaced byby by idealideal ideal DCDC DC powerpower power supplies.supplies. supplies. • • TheThe secondsecond second stage stage stage converts converts converts the the DCthe DC voltageDC voltag voltag frome efrom from the PVthe the modules PV PV modules modules to a medium-frequency to to a amedium-fre- medium-fre- squarequencyquency AC square square voltage. AC AC Manyvoltage. voltage. converters Many Many converte canconverte do thisrsrs can workcan do do half-bridge, this this work work full-bridge,half-bridge, half-bridge, push- full- full- pull,bridge,bridge, flyback, push-pull, push-pull, dual-active-bridge, flyback, flyback, dual-active-bridge, dual-active-bridge, and others. and and others. others. • • TheThe third third stage stage stage consists consistsconsists of of a aferrite-base a ferrite-base ferrite-baseddd medium-frequency medium-frequency medium-frequency transformer, transformer, transformer, which which which iso- iso- isolateslateslates and and and steps steps steps up up up the the the voltage. voltage. voltage. The The The primary primary winding windingwinding is isis plugged pluggedplugged into into into stage stage two, two, andand and thethethe secondarysecondary secondary windingwinding winding feedsfeeds feeds stagestage stage four.four. four. • • TheThe fourthfourth fourth stagestage stage hashas has thethe the tasktask task toto to convertconvert convert aa a MF-ACMF-AC MF-AC voltagevoltage voltage toto to aa a low-frequencylow-frequency low-frequency ACAC AC voltage.voltage.voltage. There There are are twotwo two methodsmethods methods toto to accomplishaccomplish accomplish thatthat that task:task: task: aa a two-steptwo-step two-step (involves(involves (involves aa a MFMF MF rectifierrectifierrectifier andand and anan an inverter)inverter) inverter) andand and aa directadirect direct approach.a pproach.approach. TheThe The directdirect direct methodmethod method couldcould could eliminateeliminate eliminate thethethe MF-rectifier,MF-rectifier, MF-rectifier, getget get bidirectionalbidirectional bidirectional powerpower power flow,flow, flow, and and and improve improve improve efficiency. efficiency. efficiency. FigureFigure4 4 presents 4presents presents aa schematic aschematic schematic viewview view ofof of the the the DC-AC-AC DC-AC-AC DC-AC-AC converter.converter. converter. AsAs As inin in Figure Figure Figure3 ,3, the3, the the PVPV arrays arrays were were interchanged interchanged byby by idealideal ideal DCDC DC powerpower power suppliessupplies supplies toto to facilitatefacilitate facilitate thethe the explanation.explanation. explanation. TheThe The DCDC supply supply feeds feeds a a push-pull push-pull converter converter thatthat that works works asas as a a MF MF square square wave wave voltage voltage generator generator (second(second(second stage).stage). stage).

i2i2

iZ1iZ1 ZZ1 1 ZZ2 2 iQ2iQ2 1 1 : : n n + iDCiDC + ++ + + v2v2 VVPWMPWM v v1 −− ++ −1− −− VVDCDC QQ2 QQ1 −− 2 1 ZZ3 3 ZZ4 4

FigureFigure 4. 4. A A singles-phase singles-phase DC-AC-AC DC-AC-AC converter’s converter’s proposal. proposal.

TheThe push-pullpush-pull push-pull converterconverter converter uses uses uses a transformera atransformer transformer action action action to transferto to transfer transfer power power power from from from the primarythe the pri- pri- sidemarymary to side theside to secondary to the the secondary secondary side. Thisside. side. converterThis This conver conver requiresterter requires requires two switches two two switches switches operating operating operating alternatively alterna- alterna- (Qtivelytively1 and (Q (Q Q1 21and); and this Q Q2 means);2 );this this thatmeans means only that that one only only switch one one is switch ONswitch for is theis ON ON entire for for the durationthe entire entire ofduration duration the switching of of the the period.switchingswitching This period. period. operation This This operationcould operation be reﬂectedcould could be be inreflected reflected lower conductionin in lower lower conduction conduction losses. In losses. addition,losses. In In addi- thisaddi- symmetriction,tion, this this symmetric symmetric conﬁguration configuration configuration of the switches of of the the reduces sw switchesitches the reduces reduces radiated the the electromagnetic radiated radiated electromagnetic electromagnetic emissions (also,emissionsemissions minimizing (also, (also, minimizing theminimizing transformer’s the the transformer’s transformer’s leakage inductance leakage leakage isinductance inductance vital to minimize is is vital vital to theto minimize minimize electromag- the the neticelectromagneticelectromagnetic interference. interference. interference. Moreover, the Moreover, Moreover, two identical the the two low-sidetwo identical identical switches’ low-side low-side implementation switches’ switches’ implemen- implemen- requires onlytationtation one requires requires DC supplier only only one one for DC DC the supplier supplier gate driver. for for the the The gate gate transformer driver. driver. The The transf action transformer regulatesormer action action the regulates regulates output v voltagethethe output output in voltage2 voltagein a feed-forward in in v 2v 2in in a afeed-forward feed-forward manner; therefore, manner; manner; the therefore, therefore, output voltage the the output output solely voltage voltage depends solely solely on

Electronics 2021, 10, 409 6 of 21

the transformer turn ratio and the DC power supply value. The magnetic core is efficient because the flux accumulation in one polarity is canceled in the other due to the bipolar operation. One overcome is that the switches have to support two times the voltage of the DC power supply. Due to the features mentioned above, the push-pull converter is implemented in the second stage. Regarding the fourth stage, a couple of converters can directly convert a MF-AC voltage to line-frequency voltage (also known as AC-AC converters or Matrix converters); the half-bridge converter and the full-bridge are the most widespread. Because of the push-pull converter, it is impossible to ensure zero volts systematically; only +VDC and −VDC are possible; therefore, it is necessary to choose the full-bridge converter. The final objective of this converter is to inject the sinusoidal current waveform into the utility. There are two switching strategies to operate an AC-AC converter: switching controlled by current and switching controlled by voltage [46–48]. The second one is the most convenient solution for the proposed DC-AC-AC converter because the push-pull converter and the full-bridge converter can be synchronized easily [49]. It is essential to determine that the standard sign over the load voltage is always retained. Hence, to operate the converter correctly, the commutation strategy should change the polarity on v2 from the load point of view. For example, if the voltage on VPWM is required to be positive when v2 is negative, then Q2,Z2, and Z3 must be ON; in this case, the voltage on the VPWM terminals will be negative.

2.2. Modulation Strategy for a Single-Phase DC-AC-AC Converter

The modulation strategy must synthesize a square MF-AC voltage from v2 into an equivalent sinusoidal pulse width modulation (SPWM) in the VPWM’s terminals of the full- bridge converter. The input and output converters must be synchronized and commuting at the same frequency rate to reach this objective. A variant of the unipolar SPWM is the modulation implemented on AC-AC converter. Compared with bipolar SPWM, the unipolar SPWM can effectively double the switching frequency. This benefit is appreciated in the harmonic spectrum of the output voltage waveform. The harmonic components related to the switching frequency and their sidebands are canceled; besides, the dominant harmonic located at the double the switching frequency is withdrawn but not their bands [50]. Due to the actual DC-AC-AC converter being a three-phase system, there are three AC-AC converters. The previous strategy is extended using three modulation waveforms and its counter-phase waveforms; thus, each pair of the modulated signal is shifted 120◦ from each other. The output voltage of the proposed converter (Figure1) is multilevel; hence, it is important to apply a proper modulation technique. Due to its benefits [51], phase-shifted multicarrier sinusoidal PWM (PSPWM) modulation is chosen. The effective switching frequency (m − 1)fc obtained with the PSPWM modulation in the output voltage VPWM is an attractive feature. In other techniques, this frequency is not as high as in PSPWM. A direct effect of implementing the PSPWM, considering a low-frequency modulation ratio mf, is a widely free zone of switching harmonics; the most significant harmonic appears at (m − 1)fc. In this modulation, the amplitude and frequency of all triangular signals are the same, but they are 360◦/(m − 1) phase-shifted from each other, and the number of carriers is (m − 1).

2.3. Design of Seven-Levels 3PH DC-AC-AC Converter As stated earlier, multilevel topologies allow for high-voltage levels, effectively increasing the output frequency [33,44,50], and low THD due to the lower harmonic content. Other exciting features come from three-phase systems; the magnetic link makes it possible to cancel the single-phase component found twice in the line frequency in the DC current waveform. In Table1 are the main parameters that this design will consider for the seven-levels 3PH DC-AC-AC converter. Electronics 2021, 10, 409 7 of 21

Table 1. Design parameters of the cascaded 3PH DC-AC-AC converter.

Parameter Acronym Value

Rated Power Po 324.16 kW Output voltage VLL 13.20 kV DC-link voltage VDC 1 kV Switching frequency fsw 9.96 kHz Output levels m 7 Inductor Li 60 mF Capacitor C 100 nF Line-frequency f 60 Hz

Let m be the number of voltage levels at the output, then the required number of independent DC sources is k = (m − 1)/2 = 3, (1) and each independent DC source should have the same voltage amplitude. Due to each AC-AC converter producing a fundamental frequency component Vo1, Vo2, and Vo3, then the Vo is given by the output voltages addition of each cascaded converter

Vo = Vo1 + Vo2 + Vo3, (2)

considering that the phase to neutral voltage (Vo) is Vo = Vop sin(ωot), with ωo = 2πf. It is known from the three-phases electrical system that the rated output power of a converter is

3Vop Iop √ P = = 3V I = 3V I , (3) o 2 LL o o o and when contemplating the values from Table1, the root meand square (RMS) output current (Io) results in 14.17 A and RMS Vo is 7.62 kV. With the output current, the equivalent resistive load per phase is 2 3Vo Ro = = 537.52 Ω (4) Po When the modulation index is 0.9, the transformer turns ratio results in

Vop n = = 3.99, (5) kmaVDC and it should warrant the system’s operation with a minimum voltage in the input supply and the maximum load, considering that the modulation index at 0.9 is high. Hence, let n be 4.5; this results in a new modulation index of 0.7983. As the value of the DC source is known as well as the transformer turn ratio; then, the MF-transformer’s voltages across the three secondary windings are

|v2| = nVDC = 4.50 kV, (6)

and its corresponding peak current can be calculated as √ i2p = 2 Io = 20.05 A (7)

If there are no losses in the process of energy transformation, the average and peak current [52] in each of the k DC input supplies are

Po IDC = = 72.03 A, (8) k VDC

3ni2p IDCp = √ = 191.40 A. (9) 2 Electronics 2021, 10, x FOR PEER REVIEW 8 of 21 Electronics 2021, 10, 409 8 of 21

correspondingly. Finally, the selection of the DC-link capacitor is calculated as follows correspondingly. Finally, the selection of the DC-link capacitor is calculated as follows P C ==6878.88μ F. (10) link 2π fvvΔP Clink = oDCDC= 6878.88 µF. (10) 2π fo∆vDCvDC

3.3. Control Control Strategy Strategy FigureFigure 55 displaysdisplays the the control control scheme scheme of of the the proposed proposed converter. converter. A A 3PH 3PH phase-locked phase-locked looploop (PLL) (PLL) is isimplemented implemented to tosynchronize synchronize the the converter converter with with the thegrid; grid; an inductance-ca- an inductance- pacitance-inductancecapacitance-inductance (LCL) (LCL) filter ﬁlter interconnects interconnects the the multilevel multilevel converter converter with with the the utility. utility. AsAs usual usual in ingrid-tied grid-tied converters, converters, one one external external loop loop and one and internal one internal regulates regulates the converter the con- byverter means by of means the voltage-oriented of the voltage-oriented control (V controlOC) under (VOC) the undersynchronous the synchronous rotating reference rotating frame.reference frame.

FigureFigure 5. 5. ControlControl scheme scheme of of the the proposed proposed converter. converter.

TheThe cascaded cascaded DC-AC-ACDC-AC-AC convertersconverters will will work work together together as aas controlled a controlled current current source sourcefeeding feeding the utility, the asutility, shown as inshown Figure in1. BecauseFigure 1. PV Because arrays workPV arrays as a current work as source, a current their source,voltages their are voltages dependable are dependable on the current on the extracted current and extracted the level and of the light level intensity; of light in inten- other sity;words, in other the PVwords, arrays’ the outputPV arrays’ voltages output depend voltages on depend the operating on the pointoperating in the point PV curvesin the PV(current curves versus (current voltage versus and voltage power and versus power voltage). versus voltage). Note that Note the that cascaded the cascaded DC-AC-AC DC- AC-ACconverters converters have the have same the circulatingsame circulating current current in each in phaseeach phase (ia, ib ,(i anda, ib, andic); therefore,ic); therefore, it is itchallenging is challenging to carryto carry an independentan independent grid grid current-control current-control loop loop to regulateto regulate each each DC-link DC- linkvoltage. voltage. Thus, Thus, the thek DC-link k DC-link voltages’ voltages’ average average must must be computed be computed into into a single a single cascaded cas- cadedgrid current-controlgrid current-control loop asloop was as proposed was proposed in [53 ].in [53]. TheThe current-control current-control loop loop (the (the inner inner loop) loop) in in practice practice should should be be designed designed to to be be faster faster thanthan the the outer outer loop loop to to follow thethe givengiven reference.reference. Hence, Hence, the the inner inner loop loop controls controls the the current cur- rentinjected injected to the to utilitythe utility employing employing a simple a simple PI controller PI controller through throughdq→abc dq→transformation,abc transformation,considering considering decoupling decoupling between betweenId and IIdq andcontrol. Iq control.va, v bv,a and, vb, andvc are vc are generated generated after after the thetransformation transformation from fromdq framedq frame to abcto abcof theof the control control signals signalsVd Vandd andVq. Vq. InIn the the external external control control loop loop Gc2G(s)c2, (sthe), thek DC-linkk DC-link voltages’ voltages’ average average is regulated is regulated to con- to trolcontrol the cascaded the cascaded converters’ converters’ output output power. power. If the If the DC DC link link is iscontrolled controlled to to be be constant, constant, thenthen the the energy energy extracted extracted from from the the PVs PVs can can be injected be injected into into the grid the gridby charging by charging and dis- and chargingdischarging the theDC-link DC-link capacitors. capacitors. To Toachieve achieve this, this, the the PV PV power power and and the the active active output output powerpower should should be be in equilibrium employingemploying thethe instantaneous instantaneous power power theory theory [54 [54].]. In In general, gen- the outer control loop will generate the current reference for the inner loop G (s). The eral, the outer control loop will generate the current reference for the inner loop Gc3c3(s). The previousprevious sentence sentence means means that that the the deviation deviation of of the the averaged averaged of of the the kk DC-linkDC-link voltages voltages from from

Electronics 2021, 10, 409 9 of 21

* the reference value is reflected in the inner current loop to adjust the control signals V d * and V q. The signals va, vb and vc cannot be directly applied to the SPWM generator to control the converter. If this happened, then the DC-link capacitors would suffer a voltage deviation because of different operating conditions created by unequal power distribution between the cells. Commonly, there are two types of power imbalance: per-cell and per-phase. Because of this converter’s nature and configuration, the per-phase power imbalance does not occur; this is an outstanding advantage compared to other topologies in the state-of-art. In those topologies, each phase and each cascaded converter are fed with an independent source of powers (PV + DC/AC converter). On the contrary, in this paper’s proposed topology, the three-phases of each cascaded converter (DC-AC-AC converter) are fed with the same source of power; this is a natural balance due to the magnetic link. Therefore, the problem is reduced to solve the per-cell imbalance. In reference [55], a power-imbalance method was described. This method is based on sharing the cascaded converters’ usage equally in the same amount of the imbalance. The per-cell imbalance occurs when each DC-AC-AC converter’s power processes are not equal (Pa1 6= Pa2 6= Pak). The per-cell imbalance affects the DC link since it is controlled like the average of the k DC-sources; thus, there is no certainty on how each DC-link voltage will react, but a voltage drift of the DC links will happen, distorting the converter voltage. To surmount the drift problem in the DC-link capacitors, it is necessary to compensate the voltage reference signals va, vb and vc in the modulation stage using a feed-forward mechanism that considers each of the DC-link voltage deviations. The k DC-link voltages pass through the controller Gc1k(s) to perform feed-forward compensation. The output of the controller reflects each deviation of the corresponding DC- link voltage from the average reference value. The three-phase voltage reference signals va, * vb and vc are divided by the modified DC-link voltages (V DCk) coming from the addition of Gc1k(s) with VDCk; as a result, k groups of independent modulation indexes are generated for each of the k DC-AC-AC converters. The changes to the respective modulation indices affect the current that the converter draws from the corresponding DC-link capacitors and thus alter the DC-link voltages. In this way, the k DC-link voltages are regulated to a given reference value (1 kV in the simulations). The unbalanced situation limits the harmonic components’ cancellation in the kth carrier group produced by each cascaded converter; as a direct effect of this dilemma, the VPWM voltage’s THD increase. Consequently, the free zone of switching harmonics is reduced because the most significant harmonic appear at 2fc. Various THD minimization methods have been proposed to extend the free zone of harmonics during unbalanced situ- ations. By removing the low-order harmonic distortion found in the unipolar pulse-width carrier frequency, these methods optimize the multilevel converters’ switching angles.

4. Simulations This section is divided into two subsections: open-loop off-grid mode and closed-loop on-grid mode. The ﬁrst section is about the power electronics system’s performance and the validation of the proposed converter considering ideal DC power supplies. The close-loop section will explain how the converter is controlled while it is connected to the grid.

4.1. Open-Loop Off-Grid Mode Simulations To verify the system’s proper operation, some off-grid simulations were done (Figures6 and7). The line-to-line voltage is set to 13.20 kV, and the total power output is 324.16 kW. ElectronicsElectronics2021 2021, ,10 10,, 409 x FOR PEER REVIEW 1010 ofof 2121

VdcVDC1

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(a) 0.5500 Volts (kV) Volts

00 V V 21A 11 Time (s) Time (s) 5.05k

(b) 00 Volts (kV) Volts −5.0-5k 0 10m 20m 30m 40m 50m 0 0.2m 0.4m 0.6m 0.8m 1.0m Time (s) Time (s) VPWMA VPWMB VPWMC Time (s) 1010k

Vo_aV VVo_b VVo_c A B C Time (s) 1010k

(d) 00 Volts (kV) Volts −-10k10 0 10m 20m 30m30m 40m40m 50m50m TimeTime (s)

FigureFigure 6. VoltageVoltage waveform waveform simulations simulations of of the the proposed proposed converter. converter. (a) (DCa) DCsource; source; (b) step-up (b) step-up voltage;voltage; (c) multilevel three-phase three-phase line-neutral line-neutral output output voltages; voltages; and and (d ()d three-phase) three-phase line-neutral line-neutral outputoutput voltages.voltages. As was discussed in previous sections, three cascaded converters are considered. Due to off-gridAs was mode, discussed a resistive in previous load is connectedsections, three through cascaded an inductance-capacitance converters are considered. (LC) ﬁlter. Due Someto off-grid simulation’s mode, parametersa resistive load are listed is connect in Tableed 1through and others an areinductance-capacitance obtained from equations (LC) 1filter. to 10. Some In this simulation’s simulation, parameters the PV arrays are were listed substituted in Table 1 by and ideal others power are supplies. obtained from equationsFigure 16 toshows 10. In the this most simulation, representative the PV waveforms arrays were in thissubstitu proposedted by converter. ideal power Figure sup- 6plies.a shows the voltage one of the three DC power supplies. Its value is 1 kV; therefore, the push-pullFigure converter’s 6 shows the power most representative switches will block wave 2forms kV; hence, in this itproposed is recommendable converter. toFigure use switches6a shows with the voltage a blocking one voltage of the three of 3.3 DC kV. power Since the supplies. DC voltage Its value should is 1 not kV; be therefore, higher than the 1push-pull kV due to converter’s safety and power insulation switches constraints, will bloc a transformerk 2 kV; hence, must it is be recommendable implemented to to step use upswitches the voltage. with a blocking In this simulation, voltage of 3.3v1 iskV. scaled Since upthe throughDC voltage the should transformer’s not be higher turn ratio than from1 kV 1due kV to to safety 4.5 kV; andv2A insulation, v2B, and v constraints,2C are identical; a transformer this is depicted must be in Figureimplemented6b, where to thestep medium-frequencyup the voltage. In this square simulation, waveforms v1 is arescaled presented up through on the the left transformer’s side, and a zoomed turn ratio view from is shown1 kV to in 4.5 the kV; right v2A, side. v2B, and v2C are identical; this is depicted in Figure 6b, where the medium-frequencyIn Figure6c, square the cascaded waveforms three-phase are presented converters on the generate left side, the and seven-level a zoomed lineview to is neutralshown in voltages the right in side.VPWM terminals; its peak voltage reaches 13.5 kV and the THD is 20.64%.In Figure The blocking 6c, the cascaded voltage associatedthree-phase with converters the AC-AC generate converter’s the seven-level switches line is 4.5to neu- kV; therefore,tral voltages 6.5 in kV VPWM IGBT terminals; collector-emitter its peak voltage voltage reaches is suitable 13.5 forkV thisand stagethe THD [56]. is If20.64%. more AC-DC-DCThe blocking are voltage cascaded, associated then thewith voltage the AC-AC rating converter’s of the semiconductors switches is 4.5 willkV; therefore, decrease linearly.6.5 kV IGBT For example,collector-emitter suppose voltage 3.0 kV devicesis suitable are for used this and stage considering [56]. If more a derating AC-DC-DC of 50%; are incascaded, that case, then nine the cascaded voltage converters rating of the will semi be requiredconductors to generate will decrease a stare linearly. output voltageFor exam- of 13.5ple, kVsuppose peak. 3.0 Finally, kV devices in Figure are6 usedd, the and three-phase considering sinusoidal a derating line of to 50%; neutral in that voltages case, nine are present,cascaded clearly converters shifted will 120 be◦ one required after another;to generate the fundamentala stare output component voltage of is13.5 60 Hz,kV peak. with aFinally, peak value in Figure of 10.77 6d, the kV. thr Theee-phase RMS phase-neutral sinusoidal line and to neutra line-linel voltages voltages are are present, 7.62 kV clearly and 13.2shifted kV, 120° respectively. one after another; the fundamental component is 60 Hz, with a peak value of 10.77 kV. The RMS phase-neutral and line-line voltages are 7.62 kV and 13.2 kV, respectively.

Electronics 2021, 10, 409 11 of 21 Electronics 2021, 10, x FOR PEER REVIEW 11 of 21

I(RfuenteA)iDC1

190

(a) Current (A)

iDC1

110

(b) Current Current (A) 0

0 200 400 600 800 Frequency [Hz]

i21A i21B i21C Time (s) 20

−20

I(Roa)iA iBI(Rob) iC I(Roc) Time (s) 20

(d) 0 Current Current (A)

−20 0 10m 20m30m 40m 50m TimeTime (s)

Figure 7. Main current waveform for the open-loop simulation.simulation. ((aa)) DCDC source;source; ((bb)) currentcurrent harmonic har- monicspectrum; spectrum; (c) current (c) waveformcurrent waveform through the through secondary the secondary windings; andwindings; (d) line-output and (d) currentline-output waveforms. current waveforms. Figure7 shows the most relevant current waveforms of the converter. Figure7a illustratesFigure the 7 shows current the waveforms most relevant in the current ﬁrst DC-link; waveforms its average of the and converter. peak current Figure values 7a il- lustratesare 110.11 the A andcurrent 191.40 waveforms A, respectively. in the first The DC ﬁrst-link; impression its average when and the peak DC current link current values is areseen 110.11 in detail A and is that 191.40 there A, is respectively. a harmonic situated The first at impression six times the when fundamental the DC link frequency, current but is seenafter in verifying detail is the that harmonic there is a spectrum harmonic in situated Figure7 b,at itsix is times evident the that fundamental the DC components frequency, butare theafter only verifying low-frequency the harmonic harmonic. spectrum This in is Figure supported 7b, it by is theevident fact thatthat thethe simulationsDC compo- nentsconsider are athe three-phase only low-frequency system balanced; harmonic. therefore, This is the supported second harmonic by the fact current that the component simula- tionsis canceled consider via a the three-phase magnetic link.system Thus, balanced the ripple; therefore, current’s the shape second is onlyharmonic related current to the componentmedium-frequency is canceled switching via the harmonics magnetic inlink. the Thus, power the switches. ripple Incurrent’s Figure7 shapec, the secondaryis only re- windingslated to the current medium-frequency waveform are illustrated,switching harmon one perics secondary in the power winding. switches. Its peak In Figure current 7c, is the20.05 secondary A in any windings of the medium-frequency current waveform transformers. are illustrated, Finally, one per Figure secondary7d shows winding. the pure Its peaksinusoidal current current is 20.05 waveform A in any throughout of the medium the resistive-frequency load; transformers. the RMS and Finally, peak currents Figure on7d showseach phase the pure are 14.017 sinusoidal A, and current 20.05 A,waveform respectively. throughout the resistive load; the RMS and peak currents on each phase are 14.017 A, and 20.05 A, respectively. 4.2. Closed-Loop On-Grid Mode Simulations 4.2. Closed-LoopThe next simulations On-Grid Mode (Figures Simulations8 and 9) use a SW250poly PV module (SolarWorld, Bonn, Germany); the main parameters of the PV module are as follows: cells per module The next simulations (Figures 8 and 9) use a SW250poly PV module (SolarWorld, are 60; the voltage at maximum power (Vmpp) is 30.8 V; current at maximum power (Impp) is Bonn, Germany); the main parameters of the PV module are as follows: cells per module 8.12 A; and the maximum power (Pmax) is 250 Wp. Therefore, 2000 cells are considered to are 60; the voltage at maximum power (Vmpp) is 30.8 V; current at maximum power (Impp) is reach 1000 V, and thirteen PV modules parallel integrate the PV array. The DC-link voltage 8.12 A; and the maximum power (Pmax) is 250 Wp. Therefore, 2000 cells are considered to

Electronics 2021, 10, 409 12 of 21

reference is 1000 V; the grid’s line-to-line RMS voltage is 13.20 kV. The grid’s interconnection is through an LCL ﬁlter, which values are 60 mH, 100 nF, and 170 µH, respectively. In Figure8, the most representative waveforms of the simulation are drawn as follows: (a) DC-link voltages; (b) power available versus power generated in the PV; and (c) PV currents. This scenario is described as follows: the light intensity for the three PV arrays is 1000 W/m2 for the time t interval given in seconds s, 0 ≤ t < 0.1 s; this means that the voltages’ values, powers, and currents remain equal in any of the three sets. The magnitude of three DC links voltages, the available and the harvesting powers, and the currents are 1 kV, 108.05 kW, and 108.05 A, respectively. 2 In the next interval, 0.1 s ≤ t < 0.2 s, the light intensity changes accordingly: PV1 = 800 W/m , 2 2 PV2 = 500 W/m , and PV3 = 400 W/m . This change of light intensity produces several disturbances in the three sets of waveforms. First, the DC-link voltages got an overshoot; Electronics 2021, 10, x FOR PEER REVIEWthe maximum overshoot belongs to VDC1 = 1009.51 V, with a settling time of 55.5 ms. 12 of 21 Second, each PV array’s available power decreased from 108.05 kW in every PV array to 74.16 kW, 51.57 kW, and 40.28 kW for PV1, PV2, and PV3, respectively. By the time t, reaches 155.5 ms, the harvested power equals the available power in the PV arrays. Third, the PV’s reachcurrent 1000 also V, is affected;and thirteen they dropPV modules immediately parallel following integrate each irradiation.the PV array. However, The DC-link they volt- ageslowly reference climb up is while1000 theV; the external grid’s loop line-to-li regulatesne theRMS DC-link voltage voltage. is 13.20 As inkV. the The available grid’s inter- connectionpower’s waveform, is through at t an = 155.5 LCL ms,filter, each which PV current values reaches are 60 themH,Impp 100with nF, the and given 170 lightµH, respectively.intensity (74.16 A, 51.57 A, 40.27 A).

S7.Vcd1VDC1 VDC2S7.Vcd2 VDC3 S7.Vcd3

10101.01k

(a) 10001k Voltage (V) Voltage 990990

Ppv1pv1 Pmpv2 ppt1 pv3Pm ppt2 P Pm ppt3 P P P available Tim e (s)

100100k

(b) 66.6667k66.66 Power (kW)Power

33.3333k33.33

i_pipv1 v 1 ii_ppv2 v 2 ipv3i_p v 3 Tim e (s)

100100

33.333333.33

050m 0.1 0.15 0.2 0.25 0.25 TimeTim e (s)

FigureFigure 8. Main waveformswaveforms of of the the simulation. simulation. (a) ( DC-linka) DC-link voltages; voltages; (b) Available (b) Available versus versus generated generated powerpower in the PV;PV; and and (c ()c photovoltaics) photovoltaics (PV) (PV) currents. currents.

In Figure 8, the most representative waveforms of the simulation are drawn as follows: (a) DC-link voltages; (b) power available versus power generated in the PV; and (c) PV currents. This scenario is described as follows: the light intensity for the three PV arrays is 1000 W/m2 for the time t interval given in seconds s, 0 ≤ t < 0.1 s; this means that the voltages’ values, powers, and currents remain equal in any of the three sets. The magnitude of three DC links voltages, the available and the harvesting powers, and the currents are 1 kV, 108.05 kW, and 108.05 A, respectively. In the next interval, 0.1 s ≤ t < 0.2 s, the light intensity changes accordingly: PV1 = 800 W/m2, PV2 = 500 W/m2, and PV3 = 400 W/m2. This change of light intensity produces several disturbances in the three sets of waveforms. First, the DC-link voltages got an overshoot; the maximum overshoot belongs to VDC1 = 1009.51 V, with a settling time of 55.5 ms. Sec- ond, each PV array’s available power decreased from 108.05 kW in every PV array to 74.16 kW, 51.57 kW, and 40.28 kW for PV1, PV2, and PV3, respectively. By the time t, reaches 155.5 ms, the harvested power equals the available power in the PV arrays. Third, the PV’s current also is affected; they drop immediately following each irradiation. However, they slowly climb up while the external loop regulates the DC-link voltage. As in the available power’s waveform, at t = 155.5 ms, each PV current reaches the Impp with the given light intensity (74.16 A, 51.57 A, 40.27 A). The last interval considers from t = 0.2 s until t < 0.3 s; the light conditions changes as follows: PV1 = PV2 = PV3 = 850 W/m2. The waveform’s behavior in the steady state will be similar to the case where the light intensity was 1000 W/m2; therefore, the explanation will be brief. The DC links show a transitory; in this case, the overshoots are slightly superior to the previous case, but after 25 ms, the DC links get controlled to 1 kV. In Figure 8b, the

Electronics 2021, 10, x FOR PEER REVIEW 13 of 21

extracted PV power in the three PV array increases to 79.81 kW. These waveforms present a negative overshoot because the maximum power cannot be surpassed; in other words, this is an effect of the PV currents, which have a spike. (c) the steady-state PV currents are 79.81 A. The test continues in Figure 9. Here also there are three sets of waveforms: (a) The average DC-link voltages, (b) the grid injected currents, and (c) LCL’s capacitor voltages. At the beginning of the simulation, a transitory with a peak time equal to 31.25 ms. At t = 0.1 s, the first S0 step is materialized; its effect is seen in (a), (b), and (c) as happened in the previous figure. The set (a) shows the little perturbation that the averaged DC-link suffers. The inductor’s current is well controlled, as can be seen in Figure 9b. There are not con- Electronics 2021, 10, 409 siderable overshoots; on the contrary, its shape is purely sinusoidal. In the first interval13 of 21 of time, the RMS value is 14.16 A; during the next period (t = 1 to t < 2) the RMS currents drop to 7.29 A, and this magnitude is reached after 0.352 ms.

FigureFigure 9. 9. MainMain waveformswaveforms for closed-loop simulation. simulation. (a (a) )Averaged Averaged DC-link DC-link voltage; voltage; (b ()b current) current injectedinjected to to the the grid, grid, and and ( c(c)) inductance-capacitance-inductance inductance-capacitance-inductance (LCL)’s (LCL)’s capacitor capacitor voltage. voltage.

TheFinally, last intervalin Figure considers 9c are the from capacitor’st = 0.2 s voltage; until t < at0.3 t s;= 0.1 the s, light there conditions is no deformation changes as of 2 follows:the sinusoidal PV1 = PVwaveforms,2 = PV3 = 850perhaps W/m the. The solar waveform’s intensity change. behavior Its in RMS the steady value remains state will con- be 2 similarstant the to theentire case test where (13.20 the kV light line-to-line). intensity was From 1000 t W/m= 0.2 s; until therefore, t < 0.3 the s, explanationother transitory will beshows brief. up The in DCthe linksDC links. show This a transitory; voltage drift in this at tcase, = 0.2 thes can overshoots be practically are slightly neglected; superior at the toend the of previous this interval, case, the but voltage after 25 settles ms, the at DC1.0 kV. links Regarding get controlled the injected to 1 kV. current In Figure to the8b, grid, the extractedits RMS value PV power increases in the to three 10.45 PV A. array Lastly, increases the capacitor’s to 79.81 kW.peak These voltage waveforms continues present stable a(18.67 negative kV) overshootwith no alteration because all the the maximum way to the power interval. cannot be surpassed; in other words, this is an effect of the PV currents, which have a spike. (c) the steady-state PV currents are 79.815. Experimental A. Results The test continues in Figure9. Here also there are three sets of waveforms: (a) The averageIn order DC-link to voltages,verify the (b) analysis the grid and injected simulati currents,on results, and two (c) LCL’sreduced capacitor versions voltages. of a la- Atboratory the beginning prototype of were the simulation, built: a five-level a transitory single-phase with a peakDC-AC-AC time equal converter to 31.25 (Figure ms. 10), At tand = 0.1 a sthree-level, the first S0 three-phase step is materialized; DC-AC-AC its converter effect is seen (Figure in (a), 11). (b), These and reduced (c) as happened versions inare the focused previous on figure. validating The setthe (a) conceptual shows the id littleea of perturbation the proposed that topology. the averaged These DC-link scaled- suffers. The inductor’s current is well controlled, as can be seen in Figure9b. There are not considerable overshoots; on the contrary, its shape is purely sinusoidal. In the first interval of time, the RMS value is 14.16 A; during the next period (t = 1 to t < 2) the RMS currents drop to 7.29 A, and this magnitude is reached after 0.352 ms. Finally, in Figure9c are the capacitor’s voltage; at t = 0.1 s, there is no deformation of the sinusoidal waveforms, perhaps the solar intensity change. Its RMS value remains constant the entire test (13.20 kV line-to-line). From t = 0.2 s until t < 0.3 s, other transitory shows up in the DC links. This voltage drift at t = 0.2 s can be practically neglected; at the end of this interval, the voltage settles at 1.0 kV. Regarding the injected current to the grid, its RMS value increases to 10.45 A. Lastly, the capacitor’s peak voltage continues stable (18.67 kV) with no alteration all the way to the interval. Electronics 2021, 10, 409 14 of 21

5. Experimental Results In order to verify the analysis and simulation results, two reduced versions of a Electronics 2021, 10, x FOR PEER REVIEW 14 of 21 Electronics 2021, 10, x FOR PEER REVIEWlaboratory prototype were built: a ﬁve-level single-phase DC-AC-AC converter (Figure14 10 of), 21

and a three-level three-phase DC-AC-AC converter (Figure 11). These reduced versions are focused on validating the conceptual idea of the proposed topology. These scaled- down converters are off-grid, and a resistive load is used in the converter outputs after an down converters are off-grid, and a resistive load is used in the converter outputs after an LC filter. ﬁlter. LC filter.

(a) (b) (a) (b) Figure 10.10. Photographs of the actual setupsetup forfor thethe single-phasesingle-phase ﬁve-levelfive-level DC-AC-ACDC-AC-AC converter:converter: (a) printedprinted circuitcircuit boardboard Figure 10. Photographs of the actual setup for the single-phase five-level DC-AC-AC converter: (a) printed circuit board (PCB) of one single cell and (b) setup for the single-phase two cascaded DC-AC-AC converters. (PCB)(PCB) of of one one single single cell cell and and (b ()b setup) setup for for the the single-phase single-phase two two cascaded cascaded DC-AC-AC DC-AC-AC converters. converters.

(a) (b) (a) (b) Figure 11. Photographs of the actual setup for the three-phase three-level DC-AC-AC converter: (a) PCB of the three-phase Figure 11. Photographs of the actual setup for the three-phase three-level DC-AC-AC converter: (a) PCB of the three-phase FigureDC-AC-AC 11. Photographs converter and of ( theb) setup actual for setup the forthree-phase the three-phase DC-AC-AC three-level conver DC-AC-ACter (from top converter: to bottom: (a )DC-power PCB of the supply, three- DC-AC-AC converter and (b) setup for the three-phase DC-AC-AC converter (from top to bottom: DC-power supply, phasedSPACE). DC-AC-AC converter and (b) setup for the three-phase DC-AC-AC converter (from top to bottom: DC-power dSPACE). supply, dSPACE). 5.1. Single-Phase Multilevel DC-AC-AC Converter 5.1. Single-Phase Multilevel DC-AC-AC Converter 5.1. Single-PhaseThe first reduced Multilevel version DC-AC-AC consists Converter of two cascaded DC-AC-AC converters; the dia- The first reduced version consists of two cascaded DC-AC-AC converters; the dia- gramThe is shown ﬁrst reduced in Figure version 12. A consistssingle-phase of two DC-AC-AC cascaded DC-AC-AC converter (Figure converters; 10a) theis built diagram with gram is shown in Figure 12. A single-phase DC-AC-AC converter (Figure 10a) is built with sixis shown IXTT69N30P in Figure MOSFETs 12. A single-phase (Littelfuse, DC-AC-ACChicago, IL, converterUSA), two (Figure for the 10push-pulla) is built converter with six six IXTT69N30P MOSFETs (Littelfuse, Chicago, IL, USA), two for the push-pull converter and four for the AC-AC converter. Each switch in the AC-AC converter is integrated by a and four for the AC-AC converter. Each switch in the AC-AC converter is integrated by a MOSFET and a diode bridge which gives the feature of a bidirectional switch. Four MOSFET and a diode bridge which gives the feature of a bidirectional switch. Four 15ETH03 diodes (Vishay, Malvern, PA, USA) were selected for the diode bridge. Regard- 15ETH03 diodes (Vishay, Malvern, PA, USA) were selected for the diode bridge. Regard- ing the medium-frequency transformer, an ETD-59 transformer core (TDK Corporation, ing the medium-frequency transformer, an ETD-59 transformer core (TDK Corporation, Tokyo, Japan) with N97 material was selected. Switching signals are generated in a Tokyo, Japan) with N97 material was selected. Switching signals are generated in a

Electronics 2021, 10, 409 15 of 21

IXTT69N30P MOSFETs (Littelfuse, Chicago, IL, USA), two for the push-pull converter and four for the AC-AC converter. Each switch in the AC-AC converter is integrated by a MOSFET and a diode bridge which gives the feature of a bidirectional switch. Four Electronics 2021, 10, x FOR PEER REVIEW 15 of 21 Electronics 2021, 10, x FOR PEER REVIEW15ETH03 diodes (Vishay, Malvern, PA, USA) were selected for the diode bridge. Regarding15 of 21

the medium-frequency transformer, an ETD-59 transformer core (TDK Corporation, Tokyo, Japan) with N97 material was selected. Switching signals are generated in a TDSM28F379D DSP (Texas Instruments Incorporated, Dallas, TX, USA) and postprocessed for the switching TDSM28F379DTDSM28F379D DSPDSP (Texas(Texas InstrumentsInstruments IncorIncorporated,porated, DallDallas,as, TX,TX, USA)USA) andand postpro-postpro- strategy in a FPGA Nexys 4 (Digilent, Pullman, WA, USA). cessedcessed forfor thethe switchingswitching strategystrategy inin aa FPGAFPGA NexysNexys 44 (Digilent,(Digilent, Pullman,Pullman, WA,WA, USA).USA).

iDC1 i21 iDC1 i21 Io Io + + + + VPWM Vo VPWM− Vo − −− iDC2 i22 iDC2 i22

Push-Pull AC-AC Push-Pull AC-AC FigureFigureFigure 12. 12.12. Diagram DiagramDiagram of ofof the thethe ﬁve-level five-levelfive-level singles singlessingles phase phasephase DC-AC-AC DC-AC-ACDC-AC-AC converter. converter.converter.

TheTheThe parameters parametersparameters of ofof the thethe single-phase single-phasesingle-phase DC-AC-AC DC-AC-ACDC-AC-AC converter converterconverter are areare the thethe following: following:following: output outputoutput RMSRMS voltagevoltage VVo = 127 127 V; V; input input voltage voltage DC DC source source VDCV = 120= 120 V; switching V; switching frequency frequency fsw = RMS voltage Vo = 127 V; input voltage DC source VDC DC= 120 V; switching frequency fsw = f 9.960= 9.960 kHz; kHz; line-frequencyline-frequency fo = 60f =Hz; 60 output Hz; output inductance inductance L = 1.8L mH;= 1.8 output mH; output capacitance capaci- C 9.960sw kHz; line-frequency fo = 60o Hz; output inductance L = 1.8 mH; output capacitance C tance= 3.5 CµF;= resistive 3.5 µF; resistive load R = load 20 ΩR; transformer’s= 20 Ω; transformer’s turn ratio turn n = 2; ratio andn modulation= 2; and modulation index ma = = 3.5 µF; resistive load R = 20 Ω; transformer’s turn ratio n = 2; and modulation index ma = index0.75.0.75. ma = 0.75. FigureFigureFigure 13 13a13aa exhibits exhibitsexhibits the thethe most mostmost representative representativerepresentative voltage voltagevoltage waveforms wavefowaveformsrms of aofof single aa singlesingle cell. cell.cell. Channel Chan-Chan- (Ch)nel (Ch) 2 illustrates 2 illustrates the square the square MF AC MF voltage AC voltagev1 of v the1 of transformer’s the transformer’s primary primary winding; winding; the nel (Ch) 2 illustrates the square MF AC voltage v1 of the transformer’s primary winding; dutythe duty cycle cycle of v2 ofis v 50%.2 is 50%. Ch3 Ch3 shows shows the voltage the voltagev2 in v the2 in transformer’sthe transformer’s secondary secondary winding, wind- the duty cycle of v2 is 50%. Ch3 shows the voltage v2 in the transformer’s secondary wind- theing, voltage the voltage of v2 is ofn timesv2 is nv 1times. Finally, v1. Ch4Finally, depicts Ch4 the depicts three-level the three-level voltages in voltagesVPWM obtained in VPWM ing, the voltage of v2 is n times v1. Finally, Ch4 depicts the three-level voltages in VPWM due to the unipolar SPWM modulation technique; its amplitude is directly related to the obtainedobtained duedue toto thethe unipolarunipolar SPWMSPWM modulationmodulation technique;technique; itsits amplitudeamplitude isis directlydirectly re-re- voltagelated to present the voltage on v2 present. on v2. lated to the voltage present on v2.

((aa)) ((bb)) Figure 13. Main voltage and current waveforms in a single cell: (a) Channel (Ch)2 primary winding voltage, Ch3 secondary FigureFigure 13.13. MainMain voltage voltage and and current current waveforms waveforms in a insingle a single cell: (a cell:) Channel (a) Channel (Ch)2 primary (Ch)2 primary winding windingvoltage, Ch3 voltage, secondary Ch3 winding voltage, Ch4 VPWM voltage and (b) Ch2 current in the DC-link, Ch3 secondary winding current, Ch4 resistor’s winding voltage, Ch4 VPWM voltage and (b) Ch2 current in the DC-link, Ch3 secondary winding current, Ch4 resistor’s secondary winding voltage, Ch4 VPWM voltage and (b) Ch2 current in the DC-link, Ch3 secondary winding current, Ch4 current.current. resistor’s current. The main current waveforms are in the oscilloscope’s screenshot in Figure 13b. Ch2 TheThe mainmain currentcurrent waveformswaveforms areare inin thethe oscilloscope’soscilloscope’sscreenshot screenshotin inFigure Figure 13 13b.b.Ch2 Ch2 shows the current iDC in the DC link; this current is the same that is flowing through the shows the current iDC in the DC link; this current is the same that is flowing through the shows the current iDC in the DC link; this current is the same that is ﬂowing through MF transformer’s central tap. The shape of the current waveform of iDC is similar to DC- MF transformer’s central tap. The shape of the current waveform of iDC is similar to DC- link current in a two-level inverter. The average and peak currents of iDC can be calculated link current in a two-level inverter. The average and peak currents of iDC can be calculated accordingaccording toto EquationsEquations (8)(8) andand (9).(9). InIn contrastcontrast withwith ththee simulationssimulations wherewhere nono overshootsovershoots werewere presented,presented, thethe MFMF trantransformer’ssformer’s centralcentral taptap currentcurrent showsshows overshootsovershoots ofof approxi-approxi- mately 20% in the experimental results. Ch3 displays the current i2 in the MF transformer’s mately 20% in the experimental results. Ch3 displays the current i2 in the MF transformer’s secondary winding; its RMS value is 4.16 A. Ch4 reveals the current io that flows in the secondary winding; its RMS value is 4.16 A. Ch4 reveals the current io that flows in the resistorresistor itsits RMS,RMS, andand peakpeak valuesvalues areare 6.266.26 AA andand 8.858.85 A,A, respectively.respectively.

Electronics 2021, 10, x FOR PEER REVIEW 16 of 21

Electronics 2021, 10, 409 16 of 21 Regarding the single-phase multilevel configuration, Figure 10b is the actual setup’s photography. Figure 14a shows the main experimental results based on the multilevel configuration; two cascaded 1PH DC-AC-AC converters are used to generate the five- thelevel MF output transformer’s voltage. Ch3 central shows tap. the The five-level shape of output the current voltage waveform VPWM with of aniDC approximateis similar toamplitude DC-link currentof 480 V. in Ch4 a two-level is the output inverter. voltage The after average the LC and filter, peak with currents a RMS of valueiDC can of 207 be calculatedV. The voltages according spikes to in Equations the total (8)VPWM and terminals (9). In contrast are generated with the due simulations to the delivery where of nothe overshootsenergy of the were MF presented, transformer’s the MFleakage transformer’s inductance central when tapthe currentcurrent showspath is overshootsbroken due oftoapproximately the hard-switching 20% commutation in the experimental in the ma results.trix converters. Ch3 displays Ch1 the reveals current the iRMS2 in the current MF transformer’son the resistive secondary load; its RMS winding; value its is RMS 7.49 valueA. Finally, is 4.16 the A. mathematical Ch4 reveals the channel current indicatesio that flowsthe output in the resistorpower measured its RMS, and in the peak resistive values areload, 6.26 and A andits value 8.85 A, is respectively.1.54 kW, (770 W per converter).Regarding the single-phase multilevel configuration, Figure 10b is the actual setup’s photography.Figure 14b Figure presents 14a more shows experimental the main experimental results in the results multilevel based configuration. on the multilevel In this configuration;scenario, one of two the cascaded two cascaded 1PH DC-AC-AC DC-AC-AC converters converters are is inactive, used to generatewhile the the other five- is levelactive. output Considering voltage. that Ch3 each shows division the five-level represents output 4 ms, voltage the secondVPWM withDC-AC-AC an approximate converter amplitudeis turned on of 480t = V.18 Ch4ms. isAs the seen output in the voltage waveforms, after the th LCe introduced filter, with perturbation a RMS value ofdoes 207 not V. Thegenerate voltages any spikes disturbing in the voltage total V orPWM currentterminals overshoot. are generated Ch1 presents due to the the current delivery in ofthe the re- energysistive ofload; the MFits peak transformer’s value changes leakage from inductance 9.40 A whento 18.60 the A. current Ch3 illustrates path is broken the voltage due to thebefore hard-switching the LC filter; commutation its waveform in changed the matrix from converters. three levels Ch1 (with reveals a peak the value RMS of current 239.80 onV) theto five-levels resistive load; (with its a RMS peak value value is of 7.49 479.10 A. Finally, V) after the the mathematical second converter channel is turned indicates on. theCh4 output depicts power output measured voltage after in the the resistive LC filter load,; the peak and itsvoltage value changed is 1.54 kW,from (770 141.00 W perV to converter).294.00 V.

(a) (b)

FigureFigure 14. 14.Experimental Experimental results results ( a(a,b,b),), Ch3 Ch3 and and Ch4 Ch4 output output voltage, voltage, before before and and after after the the LC LC ﬁlter filter respectively, respectively, Ch1 Ch1 output output currentcurrent trough trough the the resistive resistive load, load, mathematical mathematical channel channel (ChMath) (ChMath) mean mean output output power. power.

5.2. Three-PhaseFigure 14b presentsDC-AC-AC more Converter experimental results in the multilevel configuration. In this scenario,The onesecond of the reduced two cascaded version consists DC-AC-AC of one converters DC-AC-AC is inactive, converter while in a thethree-phase other is active.configuration; Considering the diagram that each is division shown in represents Figure 15. 4 ms,The the 3PH second DC-AC-AC DC-AC-AC converter converter is as- issembled turned onwitht =four18 ms.IXTH36N50P As seen in MOSFETs the waveforms, (Littelfuse, the introduced Chicago, IL, perturbation USA) for the does AC-AC not generateconverter, any and disturbing two IXFK100N65X2 voltage or (Littelfuse, current overshoot. Chicago, Ch1IL, USA) presents integrate the current the push-pull in the resistiveconverter. load; The its bidirectional peak value changesswitches fromare integrated 9.40 A to 18.60in the A. same Ch3 way illustrates that in the the voltage first re- beforeduced the version. LC filter; its waveform changed from three levels (with a peak value of 239.80 V) to five-levels (with a peak value of 479.10 V) after the second converter is turned on. Ch4 depicts output voltage after the LC filter; the peak voltage changed from 141.00 V to 294.00 V.

5.2. Three-Phase DC-AC-AC Converter The second reduced version consists of one DC-AC-AC converter in a three-phase conﬁguration; the diagram is shown in Figure 15. The 3PH DC-AC-AC converter is assembled with four IXTH36N50P MOSFETs (Littelfuse, Chicago, IL, USA) for the AC-AC converter, and two IXFK100N65X2 (Littelfuse, Chicago, IL, USA) integrate the push-pull

Electronics 2021, 10, 409 17 of 21

Electronics 2021, 10, x FOR PEER REVIEW 17 of 21 converter. The bidirectional switches are integrated in the same way that in the ﬁrst reduced version. Electronics 2021, 10, x FOR PEER REVIEW 17 of 21

Medium Frequency magnetic link

Medium Frequency magnetic link iDC i2A i2B i2C

iDC i2A i2B i2C

Push-Pull AC-ACiinvA AC-ACiinvB AC-AC iinvC Push-PullL AC-ACiinvA AC-ACiinvB AC-AC iinvC L iA C iA C Phase A Phase A Phase B Phase B Phase C Phase C Figure 15. Block diagram of a three-level three-phase DC-AC-AC converter. Figure 15. BlockFigure diagram 15. Block of a diagramthree-level of a three-levelthree-phase three-phase DC-AC-AC DC-AC-AC converter. converter. Regarding the medium-frequency transformer, an EE 110/36 transformer core Regarding the medium-frequencyRegarding the medium-frequency transformer, transformer, an EE an EE110/36 110/36 transformer transformer core core (TYDZ, Guangzhou,(TYDZ, Guangzhou, China) with China) PC40 with material PC40 was material selected. was The selected. modulation The modulation strategy was strategy gener- (TYDZ, Guangzhou,atedwas China) ingenerated dSPACE with in environment dSPACE PC40 materialenvironment through awas DS1006 thro selected.ugh processor a DS1006 The accompanied processormodulation byaccompanied a DS5203strategy board by a was generated in (dSPACEDS5203dSPACE board GmbH, environment (dSPACE Paderborn, GmbH, thro Germany). Paderborn,ugh a DS1006 This Germany). last boardprocessor This was last programmed accompanied board was withprogrammed by the a RTI DS5203 board (dSPACEFPGAwith the Programming GmbH, RTI FPGA Paderborn, Programming by Xilinx System Germany). by Xilinx Generator System This Simulink last Generator board blockset. Simulink was programmed blockset. with the RTI FPGA ProgrammingThisThis converterconverter was bywas designedXilinx designed System to to be be one oneGenerator of theof the three three cascadedSimulink cascaded 3PH blockset. 3PH DC-AC-AC DC-AC-AC converter. con- Theverter. parameters The parameters of the converter of the converter are the following:are the following: output voltageoutput Vvoltage= 55.0 VLL V = 55.0; input VRMS; This converter was designed to be one of the three cascaded 3PH DC-AC-ACLL RMS con- voltageinput voltage DC source DC sourceVDC = 60VDC V; = switching 60 V; switching frequency frequencyfsw = 10 f kHz;sw = 10 line-frequency kHz; line-frequencyfo = 50Hz; fo = verter. The parametersoutput50 Hz; of inductanceoutput the converterinductanceL = 1.8 areL mH; = 1.8the output mH; following: output capacitance capacitance outputC = 27voltage Cµ F;= 27 transformer’s µF; VLL transformer’s = 55.0 turnVRMSratio ;turn input voltage DC nratiosource= 1.34; n = and1.34;VDC modulation =and 60 modulation V; switching index indexma = frequency 0.55.ma = 0.55. fsw = 10 kHz; line-frequency fo = 50 Hz; output inductanceFigureFigure L 1616a =a 1.8 presentspresents mH; thethe output waveformswaveforms capacitance generatedgenerated C byby = phase phase27 µF; A oftransformer’s the three-phase turn DC-AC- ACAC converter.converter. Ch1Ch1 illustratesillustrates thethe currentcurrent throughthrough thethe resistiveresistive loadload ofof phasephase AA;; itsits RMSRMS ratio n = 1.34; and modulation index ma = 0.55. valuevalue isis 136.0136.0 mA.mA. Ch3Ch3 andand Ch4 Ch4 are are the the line line to to neutral neutral output output voltages voltages of ofV PWMAVPWMA andandV VAA.. Figure 16a presentsItsIts amplitudesamplitudes the wave areare 45.045.0forms VV andand generated 90.090.0 V,V, respectively.respectively. by phase Both BothA of voltagesvoltages the three-phase areare measuredmeasured DC-AC- beforebefore andand AC converter. Ch1afterafter illustrates thethe LCLC filter.filter. the Figure Figurecurrent 16 16bb through depicts depicts the the the line-to-line line-to-line resistiveV VPWM PWMload output of phase voltagesvoltages A; beforebeforeits RMS thethe LCLC value is 136.0 mA.filter,filter, Ch3 itsits and shapeshape Ch4 hashas are fivefive the levelslevels line asas expected,expected,to neutral andand output thethe peak-to-peakpeak-to-peak voltages voltage voltageof VPWMA forfor each eachand phase phaseVA. isis Its amplitudes are360.0360.0 45.0 V. V.V and 90.0 V, respectively. Both voltages are measured before and after the LC filter. Figure 16b depicts the line-to-line VPWM output voltages before the LC filter, its shape has five levels as expected, and the peak-to-peak voltage for each phase is 360.0 V.

(a) (b)

FigureFigure 16.16. ((aa)) WaveformsWaveforms generatedgenerated in phase A A of of the the three-phase three-phase DC DC-AC-AC-AC-AC converter. converter. Ch1 Ch1 Output Output current, current, Ch2 Ch2 Line Line to neutral output voltage before filter, Ch3 Line to neutral output voltage after filter and (b) line-to-line voltages (VPWM) before to neutral output voltage before filter, Ch3 Line to neutral output voltage after filter and (b) line-to-line voltages (VPWM) the filter, Ch1 Phase AB, Ch3 Phase BC, Ch4 Phase CA. before the filter, Ch1 Phase AB, Ch3 Phase BC, Ch4 Phase CA.

TheThe nextnext ﬁgurefigure representrepresent thethe line-to-lineline-to-line voltagesvoltages andand currentscurrents inin thethe converter.converter. InIn (a) thisthis casecase the line to to line line voltages voltages are are measured measured after( afterb) the the LC LC filter, ﬁlter, the the results results are are shown shown in inFigure Figure 17a; 17 a;the the peak-to-peak peak-to-peak and and the the RMS RMS values values are are 165.0 165.0 V V and and 54.9 54.9 V, V, respectively. Figure 16. (a) Waveforms generated in phase A Finally,of the three-phase in Figure 17b DC are-AC-AC the three-phase converter. ou Ch1tput Output currents current, with an Ch2 RMS Line value to of 137.00 neutral output voltage before filter, Ch3 Line to neutralmA. As outputwas expected, voltage the after waveforms filter and are (b completely) line-to-line sinusoidal; voltages (theyVPWM show) before a peak value the filter, Ch1 Phase AB, Ch3 Phase BC, Ch4 Phaseof 193.74 CA. mA.

The next figure represent the line-to-line voltages and currents in the converter. In this case the line to line voltages are measured after the LC filter, the results are shown in Figure 17a; the peak-to-peak and the RMS values are 165.0 V and 54.9 V, respectively. Finally, in Figure 17b are the three-phase output currents with an RMS value of 137.00 mA. As was expected, the waveforms are completely sinusoidal; they show a peak value of 193.74 mA.

Electronics 2021, 10, 409 18 of 21

Finally, in Figure 17b are the three-phase output currents with an RMS value of 137.00 mA. Electronics 2021, 10, x FOR PEER REVIEW 18 of 21 As was expected, the waveforms are completely sinusoidal; they show a peak value of 193.74 mA.

(a) (b)

FigureFigure 17. ((aa)) Line Line to to line line voltages voltages (VLL) (VLL) after after the the LC LC filt ﬁlter.er. Ch2 Ch2 Phase Phase AB, AB, Ch3 Ch3 Phase Phase BC, BC, Ch4 Ch4 Phase Phase CA; CA; (b)) Output currents through the three-phase resistive load. Ch1 Phase A, Ch2 Phase B, Ch3 Phase C. currents through the three-phase resistive load. Ch1 Phase A, Ch2 Phase B, Ch3 Phase C.

6. Discussion 6. Discussion The simulation results proved that the proposed converter is an alternative to the The simulation results proved that the proposed converter is an alternative to the existing MV grid-tied converters for PV plants. The off-grid simulations showed that the existing MV grid-tied converters for PV plants. The off-grid simulations showed that the steady-state current and voltage’s behavior worked as expected. Developing a proper steady-state current and voltage’s behavior worked as expected. Developing a proper com- commutation strategy permits that the matrix converter works alongside the MF trans- mutation strategy permits that the matrix converter works alongside the MF transformer former properly. As proof of this, the AC-AC converter effectively transforms the MF-AC properly. As proof of this, the AC-AC converter effectively transforms the MF-AC voltage voltagefrom the from MF transformerthe MF transformer to a LF-AC to a voltage LF-AC without voltage anywithout difﬁculties. any difficulties. The only issueThe only here issueis the here leakage is the inductance leakage inductance in the MF transformer; in the MF transformer; this inductance this causesinductance the well-known causes the well-knownvoltages spikes voltages in the spikes power in switches. the power switches. RegardingRegarding the the uneven uneven light light intensity intensity through through the the multiples multiples PV PV arrays, arrays, the the literature literature showsshows several several solutions solutions on on how how to to handle handle the the per-phase per-phase and and per-cell per-cell imbalance, but but the the proposedproposed DC-AC-ACDC-AC-AC converterconverter solves solves the the per-phase per-phase imbalance imbalance naturally naturally through through the three- the three-phasephase MF-AC MF-AC link. However, link. However, when awhen light a intensity light intensity perturbation perturbation occurs unevenlyoccurs unevenly through throughthe k PV the arrays, k PV different arrays, different levels of energylevels of are energy harvested are harvested from each from PV array; each PV as a array; result, as the a result,per-cell the imbalance per-cell imbalance arises. Various arises. solutions Various solutions have been have proposed, been proposed, but the implemented but the imple- in mentedthis work in ﬁxesthis work the problem fixes the by problem modifying by modulationmodifying modulation indexes accordingly indexes accordingly to the DC-link to thevoltage DC-link deviation. voltage This deviation. solution This is simple solution and wasis simple easy to and implement. was easy The to resultsimplement. (Figure The8) resultsproved (Figure that this 8) technique proved that distributes this technique the imbalance distributes to the thek cascadedimbalance converters. to the k cascaded converters.From the power electronics perspective, the MF transformer was a crucial element in the implementation.From the power Itselectronics standalone perspective, performance the wasMF transformer not presented, was but a itscrucial work element alongside in thethe implementation. push-pull converter Its standalone was successful; performa thisnce allowed was not to presented, continue with but its the work converter’s along- sidedevelopment. the push-pull Another converter critical was aspect successful; is how this the allowed bidirectional to continue switches with are theconstructed. converter’s development.The diode bridge Another with acritical MOSFET aspect implementation is how the bidirectional was selected switches between are the constructed. options, but Theother diode options bridge like with common a MOSFET emitter implementati or commonon collector was selected arrangements between the of IGBTsoptions, might but otherperform options better. like common emitter or common collector arrangements of IGBTs might performBecause better. this is a large topology with many stages, the best way to test the entire systemBecause was to this build is a reduced large topology versions. with At thismany time, stages, as was the seen best in way section to test four, the two entire reduced sys- temversions was to were build tested. reduced The versions. cascaded At single-phase this time, as DC-AC-AC was seen in converter section demonstratedfour, two reduced that versionsthe multilevel were tested. concept The works cascaded in this single-p topology.hase DC-AC-AC As proof, theconverter two cascaded demonstrated converters that theoperate, multilevel injecting concept over works 1500 W in to this a resistive topology. load. As Inproof, the three-phase the two cascaded DC-AC-AC converters converter, operate,the preliminary injecting over tests 1500 demonstrated W to a resistive that the load. three-phase In the three-phase system model DC-AC-AC also worked. converter, Here, themore preliminary work must tests be donedemonstrated to reduce that the noisethe three-phase levels; in this system way, model the converter also worked. can handle Here, moremore work power. must be done to reduce the noise levels; in this way, the converter can handle more Inpower. conclusion, the two reduced versions proved that the converter’s core concept worksIn asconclusion, it should andthe suggeststwo reduced that theversions complete proved topology that the will converter’s work. core concept works as it should and suggests that the complete topology will work.

Electronics 2021, 10, 409 19 of 21

Author Contributions: Conceptualization, M.A.B.; methodology, M.A.B.; validation, M.A.B., V.C., J.C.V. and J.M.G.; formal analysis, M.A.B. and V.C.; investigation, M.A.B. and J.M.S.; methodology, M.A.B., J.M.S. and J.M.G.; project administration, V.C. and J.C.V.; supervision, V.C. and J.M.G.; funding acquisition, V.C. and J.C.V.; writing—original draft, M.A.B.; writing—review and editing, V.C. and J.M.G. All authors have read and agreed to the published version of the manuscript. Funding: This research work was supported by the project UASLP-TRAFOS UASLP/AG-038/18. The authors would like to thank The National Council of Science and Technology of Mexico (CONA- CyT) for the academic scholarship under the grant number 486788. Data Availability Statement: Data is contained within the article. Acknowledgments: This work was supported by VILLUM FONDEN under VILLUM Investigator Grant 25920 from the Center for Research on Microgrids (CROM); www.crom.et.aau.dk. The authors acknowledge to the UASLP Electrical Power Quality and Motor Control Laboratory (LABCEECM) staff for technical and material support during the experimental stage. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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