Data Path & Control Design

Home , Datapath

Data Path & Control Design‐ (i) Simple arithmetic computations (ii) Complex Datapath, Transcendental Functions

Vineet Sahula [email protected]

Dept. of ECE, MNIT Jaipur

Text Marking 1.!!! 2.1 Design‐ representation 2.2.1 RTL components 2.2.3 Register level design

3.2 Data representation‐ Fixed & Floating point

4.1 Fixed point arithmetic, + ‐ ×  4.2 ALU 4.3.1 Floating point arithmetic [4.3.2 Pipelining]

5.1 Control design basics‐ HW 5.2 Control basics‐ Microprogrammed

CAD-DS [V. Sahula] Complex Data Path & Control Design 2

1 Arithmetic Digital Design • RTL symbols & Algorithm State Machine • Control Unit Design • Hard‐wired control • Micro‐programmed control • Example data path • GCD Computer • Shift Add multiplier • Processor‐ RISC/CISC • Complex data path • log • sin cos sin cos • FFT • Processor instruction design • Control field encoding

CAD-DS [V. Sahula] Complex Data Path & Control Design 3

CAD-DS [V. Sahula] Complex Data Path & Control Design 4

2 Data Path Design

CAD-DS [V. Sahula] Complex Data Path & Control Design 5

Data Path Components • Shifters Counters • Adders/Subtracters/Multipliers/Dividers • Multiplexers – 2P input m‐output MUX • Selectors Decoders • Magnitude comparator • Registers – PIPO, SISO

CAD-DS [V. Sahula] Complex Data Path & Control Design 6

3 Arithmetic Data Path • Serial adder • 4‐bit parallel adder – Ripple carry (RCA) – Carry Look Ahead (CLA) – Carry save • Multiplication – Shift‐add – Booth’s coded • Division – Repeated subtraction – Repeated multiplication • Others – GCD computer

CAD-DS [V. Sahula] Complex Data Path & Control Design 7

Ripple Carry Adder

B An-1 n-1 An-2Bn-2 A0 B0

C Cn+1 n C 1-bit 1-bit 1-bit 1 C adder adder  adder 0

S Sn-1 Sn-2 0

Si  Ai  Bi  Ci1

Ci1  Ai Bi  Ci (Ai  Bi )

CAD-DS [V. Sahula] Complex Data Path & Control Design 8

4 Carry Look Ahead Adder‐ Truth Table Looking ahead “Carry” Table Ai Bi Ci Ci+1 pi gi 0 0 0 0 0 0 gi  Ai Bi 0 1 0 0 0 0 p  A  B 1 0 0 0 0 0 i i i 1 1 0 1 0 1

0 0 1 0 0 0 Ci1  gi  piCi 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1

CAD-DS [V. Sahula] Complex Data Path & Control Design 9

CLA‐ 1‐Bit HA‐ implementation Ai Bi

Ai Bi

Ai Bi Ai Bi

Si S i

S i gi  Ai Bi gi pi pi  Ai  Bi

CAD-DS [V. Sahula] Complex Data Path & Control Design 10

5 Carry Look Ahead Adder

An-1Bn-1 An-2Bn-2 A0 B0

C 1-bit Cn-1 1-bit Cn-2 1-bit 0 HA- HA- HA-

Sn-1 Sn-2 S0

p gn-2 pn-1gn-1 n-2 p0 g0

C n Carry-Look Ahead generator

CAD-DS [V. Sahula] Complex Data Path & Control Design 11

Carry Save Adder‐ Principle W,X,Y,Z n‐bit numbers to be added 1. Add X,Y,Z using CSA (Ouput is C,S ) Wallace Tree 2. Add W,C,S using CSA (Ouput is C’,S’ ) 3. Add C’ and S’ Using RCA X YZ 1101 + 0111 CSA 1001 ------W CS S 00011 Saved carry C 11010 CSA W 01010 C’ S’

------Cout 0--- RCA Saved carry S’ 100110 ------C’ 01010 Merged - Sum carry CAD-DS [V. Sahula] Complex Data Path & Control Design 12 SUM 100111

6 Carry Save Adder‐ Implementation

Z3 Z2 Z1 Z0 X Y 3 3 X2Y2 X1Y1 X0Y0

1-bit 1-bit 1-bit 1-bit adder adder adder adder

W3 W2 W1 W0

1-bit 1-bit 1-bit 1-bit adder adder adder adder

C’3 C’2 C’1 C’0

S’3 S’2 S’1 S’0

CAD-DS [V. Sahula] Complex Data Path & Control Design 13

Multiplication Principle

j Pi1  Pi  rj 2 D Forming Partial products Pi’s 3 j S   rj 2 D 0100 D3D2D1D0 j0 P  0  R3R2R1R0 0011  P3 ------0100 P03P02P01P00 0100 P13P12P11P10  j Pi1  2 Pi  rj D 0000 P23P22P21P20 P3 n3 P33P32P31P30 j3 0000 S  rj 2 D ------j0

0001100 S7 S6 S5 S4 S3 S2 S1 S0  P3

CAD-DS [V. Sahula] Complex Data Path & Control Design 14

7 Modified Booth Coding

0100  1111 Booth Recoding Table ------f f f f Ri+1 Ri fi RRi fi+1 3 2 1 0 0 0 0 0 0 0100 001 1 1 1 0 1 0 1 0 0100 1 0 0 0 0 0100 Booth coded 1 1 0 ī 1 0 0 1 1 0 0100 1000î 0 1 1 0 1 ------1 addition 1 0 1 ī 1 01 1 1 100 1 subtraction 1 1 1 0 1 ------4 additions

CAD-DS [V. Sahula] Complex Data Path & Control Design 15

Alternate Methods for Pi

• P1 = P0 + p1 – Recursively compute, Pi = Pi‐1 + pi – requires ONLY one ADDER – For n‐bit numbers, requires n steps

• SUM all Pi s together – needs n/2 adders – Need n/4 adders further for summing n/2 such outputs – … – … till, n/2m=1

– m=log2 n is depth of Adder‐tree, total ADDERS=n‐1 – ONE step process

CAD-DS [V. Sahula] Complex Data Path & Control Design 16

8 Sum All Pistogether … • Adder Tree with depth m for n numbers

+ + + + +

+ + +

+ + A ONE step process Wallace Tree Multiplier + CAD-DS [V. Sahula] Complex Data Path & Control Design 17

Fixed Point Array Multiplier‐ AND Array

CAD-DS [V. Sahula] Complex Data Path & Control Design 18

9 Fixed Point Array Multiplier‐ Adder Array

CAD-DS [V. Sahula] Complex Data Path & Control Design 19

Fixed Point Array Multiplier‐ Array Cell

CAD-DS [V. Sahula] Complex Data Path & Control Design 20

10 Shift Add Multiplier 8 INBUS D/R 8

ShiftA LoadD MultiplicanD LoadA Accumulator MultiplieR ResetA LoadR 8

8 8 8

Adder/Subtracter 8-bit

Reset Shift n LoadS Load Output S R A 0 Load Start Controller R 16 bit Load Clock D ResetA OUTBUS Load S S CAD-DS [V. Sahula] Complex Data Path & Control Design 21

GCD Computer: RTL Description

gcd (IN: X, Y; OUT:Z) REGISTER XR, YR, TEMPR; XR:=X; (Start & Input) YR:=Y; WHILE (XR>0) DO BEGIN IF (XR  YR) THEN BEGIN TEMPR:=YR; (Swap) YR:=XR; XR:=TEMPR; END XR:=XR-YR; (Sutract) END Z:=YR; (Output & End) END gcd;

CAD-DS [V. Sahula] Complex Data Path & Control Design 22

11 Example Check of GCD algorithm

Conditions Actions XR := 20; YR :=12 XR > 0 XR > YR XR := XR-YR := 8; XR > 0 XR  YR YR := 8; XR := 12; XR := XR-YR = 4; XR >0 XR  YR YR := 4; XR := 8; XR := XR-YR = 4; XR > 0 XR  YR YR := 4; XR := 4; XR := XR-YR = 0; XR  0 Z := 4;

CAD-DS [V. Sahula] Complex Data Path & Control Design 23

Data Path‐ GCD Computer Z X Y Reset

Control Unit

Subtract Multiplexers MUX Swap Select XY

Load XR Register YR Register XR Load YR

Subtractor Comparators

(XR  YR) (XR > 0) Datapath Unit

CAD-DS [V. Sahula] Complex Data Path & Control Design 24

12 Division Principles‐

Repeated Subtraction 8-bit numbers ______8 steps R0=D 101 ) 100 1 1 0 R  R  q 2iV 000 i1 i i ------0 R  2iV  i 100 1 q  1 0 1 i  i 1 Ri  2 V ------ 10 0 1 1 0 1 ------Ri1  2Ri  qiV 1 0 00 0 2R  V 1 01 2R0=D  i ------qi   0 1 1 1 2Ri  V 

CAD-DS [V. Sahula] Complex Data Path & Control Design 25

Division: (2)Repeated Multiplication D (16bit) Q  V (8bit)

0.4 0.4 0.4(1 0.3)   0.7 (1 0.3) (1 0.3)(1 0.3) 0.4(1 0.3) 0.4(1 0.3)(1 0.32 )   (1 0.32 ) (1 0.32 )(1 0.32 ) 0.4(1 0.3)(1 0.32 ) 0.4(1 0.3)(1 0.32 )(1 0.34 )   (1 0.34 ) (1 0.34 )(1 0.34 )  n 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 )  (1 0.3n ) 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3n )  (1 0.3n )(1 0.3n ) n 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 )(1 0.3n )  (1 0.32n ) n  0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 )(1 0.3n ) When 0.32n  1 CAD-DS [V. Sahula] Complex Data Path & Control Design 26

13 Repeated Multiplication‐ Algorithm 1. Load D 2. Load R 3. X=(1‐R) 4. Y=(1+X) 5. D=D*Y 6. R=R*Y 7. If R is sufficiently close to 1.0 GOTO Step 8. Else GOTO Step 3. 8. Output D 9. Stop

CAD-DS [V. Sahula] Complex Data Path & Control Design 27

FLOATING POINT ARITHMETIC

CAD-DS [V. Sahula] Complex Data Path & Control Design 28

14 Data Format Classification

• Instructions [Control] • Data

CAD-DS [V. Sahula] Complex Data Path & Control Design 29

Fixed Point Numbers

Signed binary numbers

CAD-DS [V. Sahula] Complex Data Path & Control Design 30

15 Exceptional Conditions

• Overflow/Underflow Z=X+Y

zi=xi  yici‐1

ci=xi yi+ xici‐1 +yici‐1

• v indicates overflow

v=x’n‐1 y’n‐1cn‐2 + xn‐1 yn‐1c’n‐2

CAD-DS [V. Sahula] Complex Data Path & Control Design 31

Floating Point Numbers • Format (‐1)S (1.M)  BE (‐1)S  2E‐127 (1.M) Binary FP no.

CAD-DS [V. Sahula] Complex Data Path & Control Design 32

16 Floating point (8‐bit) • +12 • 0 011 1100

• Mantissa always have 1.XXXX form – Hence, 1 is presumed, and 1‐bit is saved in representation

• SM, (SE, E), M • ______• Mantissa is interpreted as • 1.M now onwards

CAD-DS [V. Sahula] Complex Data Path & Control Design 33

FP Numbers • 6‐bit FP Number – 3 bit Exponent (E), 3 bit Mantissa (M) – E and M are Sign‐magnitude integers – (‐1)S M  BE,B=2 – 1 2‐3; 3 23

CAD-DS [V. Sahula] Complex Data Path & Control Design 34

17 FP Exceptional Conditions

Not a number Infinity Normalized number Denormalized number Zero

CAD-DS [V. Sahula] Complex Data Path & Control Design 35

Algorithm for FP Addition

CAD-DS [V. Sahula] Complex Data Path & Control Design 36

18 FP Addition Illustration

CAD-DS [V. Sahula] Complex Data Path & Control Design 37

FP Adder Datapath

CAD-DS [V. Sahula] Complex Data Path & Control Design 38

19 Pipelined FP Adder

• At inter‐ Stage-1 section of nets with Stage-2 pipeline RED cut Stage-3 – A register is Stage-4 implied

CAD-DS [V. Sahula] Complex Data Path & Control Design 39

4‐stage Pipelined FP Adder Operation

CAD-DS [V. Sahula] Complex Data Path & Control Design 40

20 Pipelined FP Adder with Feed‐back

CAD-DS [V. Sahula] Complex Data Path & Control Design 41

COMPLEX DATAPATH DESIGN: TRANSCENDENTAL FUNCTIONS

CAD-DS [V. Sahula] Complex Data Path & Control Design 42

21 Complex Datapath

• Complex data path • log • sin cos sin cos • FFT

CAD-DS [V. Sahula] Complex Data Path & Control Design 43

Control Unit Design

CAD-DS [V. Sahula] Complex Data Path & Control Design 44

22 Control Design

• Sequential logic ckts (FSM, ASM) – Hardwired control • Control memory based – Microprogram control unit

CAD-DS [V. Sahula] Complex Data Path & Control Design 45

Example Designs

• Data Path (data processing) unit • RTL symbols & ASM implementation • Control unit – Hardwired • GCD Computer • Shift‐Add multiplier – Microprogrammed • GCD Computer • Shift‐Add multiplier

CAD-DS [V. Sahula] Complex Data Path & Control Design 46

23 Control Unit Structures‐ An Implementation of FSM Microprogrammed control

Status Address Control Hardwired control signals Logic memory

Status Sequential Control signals Logic signals Microinstruction register signals Control

Decoder Instruction Instruction register register

CAD-DS [V. Sahula] Complex Data Path & Control Design 47

Microprogrammed Control

• Sequence of Control signals in response to instruction execution • Control signals stored in Microprogram memory – In a program like format akin to State‐table • Designing is more systematic – Organizing control signals into formatted words (micro‐instructions)

CAD-DS [V. Sahula] Complex Data Path & Control Design 48

24 Hardwired Control

• Sequence of Control Signals in response to clock • Optimizes – Minimize # of components used – Maximize speed • Only way to modify – Redesign entire unit

CAD-DS [V. Sahula] Complex Data Path & Control Design 49

Hardwired Control (contd.)

• Suited for – Application specific controllers – RISC computers • Design methods – FSM based method

• Uses log2 P FFs only for P‐states • Usually based on Moore machine state table – One‐ hot encoding method • One FF per state (P FFs for P states) • Moore machine state table based

CAD-DS [V. Sahula] Complex Data Path & Control Design 50

25 State Table for FSMs

Mealy Type

Inputs State I1 I2 Ik Im S1 S1,1,O1,1 S1,2,O1,2  S1,m,O1,m S2 S2,1,O2.1 S2,2,O2,2  S2,m,O2,m

Sn Sn,1,On,1 Sn,2,On,2  Sn,m,On,m

Inputs State I1 I2 Ik Im Outputs S1 S1,1 S1,2  S1,m O1 S2 S2,1 S2,2  S2,mm O2

Sn Sn,1 Sn,22  Sn,m On

Moore Type

CAD-DS [V. Sahula] Complex Data Path & Control Design 51

HARDWIRED CONTROL

CAD-DS [V. Sahula] Complex Data Path & Control Design 52

26 FSM Implementation • Assumption – Considering those machines whose past histories can affect their future behavior in only a finite number of ways • There is no bound on duration input may affect the future behavior of the system

• Notations Inputs, l – I: Input alphabet, Outputs, m – O: output alphabet,

– S: set of all states Input forming Output forming Combinational Combinational Logic Logic

Excitation, E I  l Memory 2 m devices O  2 State variables, k S  k CAD-DS [V. Sahula] Complex Data Path & Control Design2 53

GCD Computer: RTL Description

CAD-DS [V. Sahula] Complex Data Path & Control Design 54

27 Data Path‐ GCD Computer Z X Y Reset

Control Unit

Subtract Multiplexers MUX Swap Select XY

Load XR Register YR Register XR Load YR

Subtractor Comparators

(XR  YR) (XR > 0) Datapath Unit

CAD-DS [V. Sahula] Complex Data Path & Control Design 55

GCD Computer: RTL Description gcd (IN: X, Y; OUT:Z) REGISTER XR, YR, TEMPR; XR:=X; (Start & Input) YR:=Y; WHILE (XR>0) DO BEGIN IF (XR  YR) THEN BEGIN (Swap) TEMPR:=YR; YR:=XR; XR:=TEMPR; END (Sutract) XR:=XR-YR; END (Output & End) Z:=YR; END gcd; CAD-DS [V. Sahula] Complex Data Path & Control Design 56

28 Flow Chart‐ GCD Computer Begin

LXR, LYR X:=XR S 0 Y:=YR

Is XR>0 No

Yes LZ Is XR

SUB, LXR XR:=XR-YR S2

CAD-DS [V. Sahula] Complex Data Path & Control Design 57

State Table‐ GCD Computer

Inputs Outputs State (XR > 0) (XR  YR) 0- 10 11 Subtract Swap Select XY Load XR Load YR S0 (Begin) S3 S1 S2 0 0 1 1 1 S1 (Swap) S2 S2 S2 0 1 0 1 1 S2 S3 S1 S2 1 0 0 1 0 (Subtract) S3 (End) S3 S3 S3 0 0 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 58

29 Excitation Table

Inputs Present Next state Outputs state + + (XR > 0) (XR  YR) D1 D2 D 1 D2 Subtract Swap Select XY Load XR Load YR 0 d 0 0 1 1 0 0 1 1 1 0 d 0 1 1 0 0 1 0 1 1 0 d 1 0 1 1 1 0 0 1 0 0 d 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 59

Combinational Logic of GCD Control Unit‐ Classical FSM

 D1  (XR  0)  (XR  YR)  D0  D0  D1  D0  (XR  YR) D0  (XR  0) D0

Subtract  D1  D0

Swap  D1  D0

SelectXR  D1  D0

SelectYR  D1  D0

LoadYR  D1

CAD-DS [V. Sahula] Complex Data Path & Control Design 60

30 Combinational Logic of GCD Control Unit‐ FSM with 1‐Hot Assignment

 D0  0  D1  D0 (XR  0)(XR  YR)  D2 (XR  0)(XR  YR)  D2  D0 (XR  0)(XR  YR)  D1  D2 (XR  0)(XR  YR)  D3  D0 (XR  0)  D2 (XR  0)  D3

Subtract  D2

Swap  D1

SelectXR  D0

SelectYR  D0  D1  D2

LoadYR  D0  D1

CAD-DS [V. Sahula] Complex Data Path & Control Design 61

Flow Chart‐ Shift‐Add Multiplier

Begin S0 RA, LD, RC 8-bit numbers A=0 8 steps S1 Count=0 D=INBUS LR S R=INBUS Yes 2 No COUNT7==1 L No S Is R[0]==1 OUTBUS=S S5 Yes LA

S3 A=A+M

ShftA, LR, INCC End S0

S4 A[6:0].R=A.R[7:1] Count=Count+1

CAD-DS [V. Sahula] Complex Data Path & Control Design 62

31 Multiplier Control Unit

ShftAddMultplier (IN: INBUS; OUT:OUTBUS) REGISTER A[7:0]; R[7:0], D[7:0]; COUNT[2:0]; BUS INBUS[7:0]; OUTBUS[7:0];

BEGIN A:=0, COUNT:=0, LD RA RC INPUT D:=INBUS;

R:=INBUS LR ADD A [7:0]:= A[7:0]+D[7:0]*R[0] LA RSHIFT A[6:0].R:=A.R[7:1], A[7]=0, COUNT:=COUNT+1; ShftA INCC TEST IF COUNT  7 THEN GOTO ADD; OUTPUT OUTBUS:=R; LS OUTBUS:=A END ShftAddMultplier;

CAD-DS [V. Sahula] Complex Data Path & Control Design 63

Shift Add Multiplier

8 INBUS D/R 8

ShiftA LoadD MultiplicanD LoadA Accumulator MultiplieR ResetA LoadR 8

8 8 8

Adder/Subtracter 8-bit

Reset Shift n A LoadS Load OutputS R A 0 Load Start Controller R 16 bit Load Clock D ResetA OUTBUS Load S S CAD-DS [V. Sahula] Complex Data Path & Control Design 64

32 8‐Bit Shift‐Add Multiplier Status Signals

n Number of bits in mulitplier Reset External Reset signal

R0 LSB Bit of register MultiplierR Start External start signal Clock Clock signal provided externally

CAD-DS [V. Sahula] Complex Data Path & Control Design 65

8‐Bit Shift‐Add Multiplier Control Signals

ShiftA Right Shift register pair A.R

LoadA Transfer adder output to Accumulator LoadR Transfer INBUS contents into register MultiplierR LoadD Transfer INBUS contents into register MultiplierD ResetAReset contents of register Accumulator ResetCReset count INCC Increment Count LoadS Transfer final product into Output register OutputS

CAD-DS [V. Sahula] Complex Data Path & Control Design 66

33 State Table‐ ShiftAdd Mulitplier

Inputs: Begin R[0] Count7 Outputs State 000 001 010 011 100 101 110 111 ResetA ShiftA LoadA LoadR LoadD LoadS, End INCCount S0 S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 1 S1 S2 S2 S2 S2 S2 S2 S2 S2 1 0 0 0 1 0 0 S2 S4 S4 S3 S3 S4 S4 S3 S3 0 0 0 1 0 0 0 S3 S4 S4 S4 S4 S4 S4 S4 S4 0 0 1 0 0 0 0 S4 S4 S5 S3 S5 S4 S5 S3 S5 0 1 0 0 0 0 0 S5 S0 S0 S0 S0 S0 S0 S0 S0 0 0 0 0 0 1 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 67

Excitation Table‐ ShiftAdd Mulitplier

Inputs Present Next state Outputs state + + + Begin R[0] Count7 D0 D1 D2 D 0 D1 D 1 ResetA ShiftA LoadA LoadR LoadD LoadS, End INCCount 0 0 0 0 0 0 0 0 1

                               

1 1 1 1 0 1 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 68

34 Excitation Table‐ ShiftAdd Mulitplier Inputs Present Next state state + + + Begin R[0] Count7 D0 D1 D2 D 0 D1 D 1

0 0 0 0 0 0 0 0 1

                 

1 1 1 1 0 1 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 69

Output Table‐ ShiftAdd Mulitplier

Inputs Present Outputs state Begin R[0] Count7 D0 D1 D2 ResetA ShiftA LoadA LoadR LoadD LoadS, End INCCount 0 0 0 0 0 0

                         

1 1 1 1 0 1

CAD-DS [V. Sahula] Complex Data Path & Control Design 70

35 Combinational Logic of ShiftAdd Mulitplier Control Unit‐ Classical FSM

 D2  f (R[0] 1),(Count7 1), D0 , D1, D2  D1  f (R[0] 1),(Count7 1), D0 , D1, D2  D0  f (R[0] 1),(Count7 1), D0 , D1, D2

Re setA  f D2 , D1, D0

Load A  f D2 , D1, D0

Load R  f D2 , D1, D0

Load D  f D2 , D1, D0

LoadS  f D2 , D1, D0

Shift A  f D2 , D1, D0

CAD-DS [V. Sahula] Complex Data Path & Control Design 71

Combinational Logic of ShiftAdd Mulitplier Control Unit‐ FSM with 1‐Hot Encoding + D4 = f (R[0] ==1),(Count7 ==1),D0 ,D1 ,D2 ,D3 ,D4 + D3 = f (R[0] ==1),(Count7 ==1),D0 ,D1 ,D2 ,D3 ,D4 + D2 = f (R[0] ==1),(Count7 ==1),D0 ,D1 ,D2 ,D3 ,D4 + D1 = f (R[0] ==1),(Count7 ==1),D0 ,D1 ,D2 ,D3 ,D4 + D0 = f (R[0] ==1),(Count7 ==1),D0 ,D1 ,D2 ,D3 ,D4

ResetA = f D4 ,D3 ,D2 ,D1 ,D0

LoadA = f D4 ,D3 ,D2 ,D1 ,D0

LoadR = f D4 ,D3 ,D2 ,D1 ,D0

LoadD = f D4 ,D3 ,D2 ,D1 ,D0

LoadS = f D4 ,D3 ,D2 ,D1 ,D0

ShiftA = f D4 ,D3 ,D2 ,D1 ,D0 CAD-DS [V. Sahula] Complex Data Path & Control Design 72

36 Flow Chart‐ Shift‐Add Multiplier

Begin S R , 0 A R , L , A A=0 D L , Count=0 R Is R[0]==1 D C R D=INBUS S1 C

LR R=INBUS Yes No COUNT7==1 L No S Is R[0]==1 OUTBUS=S S2 Yes LA COUNT7==1 A=A+M S3 R , A End L , A[6:0].R=A.R[7:1] D Count=Count+1 RC

S CAD-DS [V. Sahula] Complex Data Path & Control Design4 73

CAD-DS [V. Sahula] Complex Data Path & Control Design 74

37 Algorithmic State Machine Implementation

ASM chart transformation rules with one flip-flop per state

CAD-DS [V. Sahula] Complex Data Path & Control Design 75

Flow Chart‐ Shift‐Add Multiplier

Begin S R , 0 A R , L , A A=0 D L , Count=0 R Is R[0]==1 D C R D=INBUS S1 C

LR R=INBUS Yes No COUNT7==1 L No S Is R[0]==1 OUTBUS=S S2 Yes LA COUNT7==1 A=A+M S3 R , A End L , A[6:0].R=A.R[7:1] D Count=Count+1 RC

S CAD-DS [V. Sahula] Complex Data Path & Control Design4 76

38 MICROPROGRAMMED CONTROL

CAD-DS [V. Sahula] Complex Data Path & Control Design 77

Microprogrammed Control

• Microinstructions – Group of control signals, sequencing signals • Control memory (ROM) – Control signal selection – Sequencing • Examples – GCD Computer – Multiplier

CAD-DS [V. Sahula] Complex Data Path & Control Design 78

39 Control Unit Organization

External address

External signals Branch address Mux … Load PC control Increment

Control memory Control fields

 Instruction register Condition select Decoders Branch address … CAD-DS [V. Sahula] Complex Data Path & Control Design 79

Micro‐program Control (CISC)

nI: no. of micro-instructions BEGIN nC: no. of control signals Branch address 0 Mux Condition_1 Load Condition_2 PC control 1 Increment log2nI

Control 2 log2nI Memory

nI[2+log2nI+nC]

[2+ log2nI+nC] Control fields  Instruction register Condition select ? Multiple Decoding Branch address … nC CAD-DS [V. Sahula] Complex Data Path & Control Design 80

40 Flow Chart‐ GCD Computer Begin

LXR, LYR X:=XR S 0 Y:=YR

Is XR>0 No

Yes LZ Is XR

SUB, LXR XR:=XR-YR S2

CAD-DS [V. Sahula] Complex Data Path & Control Design 81

State Table‐ GCD Computer

CAD-DS [V. Sahula] Complex Data Path & Control Design 82

41 GCD Computer Binary Micro‐program

Memory Condition Branch LXR LYR SUB LZ OUTRDY address Select Address 000 001 100 1 1 0 0 0 001 010 011 0 0 0 0 0 010 000 011 1 1 1 0 0 011 011 001 1 0 1 0 0 100 000 101 0 0 0 1 1 101 111 101 0 0 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 83

GCD Computer Micro‐program Control BEGIN Branch address 0 (X  0) Mux R Load (X R  YR ) (X  0) PC control R Increment 1  4

Control 3 3 Memory 614 bits Control fields

14  Instruction register Condition select 9 Decoders Branch address … CAD-DS [V. Sahula] Complex Data Path & Control Design 84

42 State Table‐ ShiftAdd Mulitplier

CAD-DS [V. Sahula] Complex Data Path & Control Design 85

Binary Micro‐program

Address Condition Branch Control signals in CM select address LD LR RA RC SA LA INCC LS END 000 00 000 1 0 1 1 0 0 0 0 0 001 00 000 0 1 0 0 0 0 0 0 0 010 01 100 0 0 0 0 0 1 0 0 0 011 00 000 1 0 0 1 1 0 1 0 0 100 00 000 0 0 0 0 0 0 0 1 0 101 11 101 0 0 0 0 0 0 0 0 1

CAD-DS [V. Sahula] Complex Data Path & Control Design 86

43 Multiplier Micro‐program Control

BEGIN Branch address 0 R[0] Load

COUNT Mux PC control Increment 1 4

Control 2 3 Memory 617 bits Control fields

14  Instruction register Condition select 9 Decoders Branch address … CAD-DS [V. Sahula] Complex Data Path & Control Design 87

Processor Instruction Set Design

CAD-DS [V. Sahula] Complex Data Path & Control Design 88

44 Processor Model

• Von Neumann model – Combined data & program memory • Harvard model – Separate program & data memory

Data/ Program CPU Data Memory Memory

CAD-DS [V. Sahula] Complex Data Path & Control Design 89

Processor Evolution • A first generation computer

CAD-DS [V. Sahula] Complex Data Path & Control Design 90

45 Processor Evolution

1st ‐generation’s Princeton Univ. IAS computer

CAD-DS [V. Sahula] Complex Data Path & Control Design 91

Processor Evolution

• 3rd‐generation IBM/360

CAD-DS [V. Sahula] Complex Data Path & Control Design 92

46 32 Bit Processor

• IBM, Motorola & Apple’s PowerPC

CAD-DS [V. Sahula] Complex Data Path & Control Design 93

Performance & Speed‐up (a) Non‐pipelined (b) Pipelined

CAD-DS [V. Sahula] Complex Data Path & Control Design 94

47 Micro‐program Control (CISC)

BEGIN Branch address 0 Condition_1 Load Condition_2 Mux PC control 1 Increment log2nC

Control 2 Memory

log2nC [nC+log2nC+2] Control fields  Instruction register Condition select Decoder Branch address … CAD-DS [V. Sahula] Complex Data Path & Control Design 95

Processor Model

• Von Neumann Model

Instructions

Main CPU Memory

Data

CAD-DS [V. Sahula] Complex Data Path & Control Design 96

48 CPU Behavior

Begin

Are No there instructions waiting?

Yes

Fetch the next instruction

Execute the instruction

Are Yes there interrupts Main waiting? Memory

CAD-DS [V. Sahula] Complex Data Path & Control Design 97

Instructions RISC Style Simple instructions • Most instructions

X1:=fi (X1,X2) X1, X2 are CPU registers, AC, DR, PC • Operand in Memory I=op.adr IR.AR:=M(PC) IR:=op; AR:=adr • Load AC:= M(adr) • Store M(adr):=AC

CAD-DS [V. Sahula] Complex Data Path & Control Design 98

49 ADD Two Operands‐ RISC Style

Z:=X+Y

HDL/RTL Assembly format language format AC:=M(X) LD X DR:=AC MOV DR,AC AC:=M(Y) LD Y AC:=AC+DR ADD M(Z):=AC ST Z

CAD-DS [V. Sahula] Complex Data Path & Control Design 99

Instructions CISC Style More complex instructions • Most instructions

X1:=fi (X1,X2) X1, X2 are CPU registers, AC, DR, PC or M(adr)

Viz. AC:= fi (AC, M(adr)) • Operand in Memory I=op.adr IR.AR:=M(PC) IR:=op; AR:=adr • Load AC:= M(adr) • Store M(adr):=AC

CAD-DS [V. Sahula] Complex Data Path & Control Design 100

50 ADD Two Operands‐ RISC Style

Z:=X+Y

HDL/RTL Assembly format language format AC:=M(X) LD X AC:=AC+M(Y) ADD Y M(Z):=AC ST Z

CAD-DS [V. Sahula] Complex Data Path & Control Design 101

Instruction‐set for Accumulator Based Processor

Type Instruction HDL/RTL format Assembly language format Data transfer Load AC:= M(X) LD X Store M(X):= AC ST X Move register DR:= AC MOV DR,AC Move register AC:= DR MOV AC,DR Data processing Add AC:= AC+DR ADD Subtract AC:= AC-DR SUB And AC:= AC and DR AND Not AC:= not AC NOT Program control Branch PC:= M(adr) BRA adr Branch zero if AC=0 then BZ adr PC:= M(adr)

CAD-DS [V. Sahula] Complex Data Path & Control Design 102

51 CPU Control Unit

• CPU • A multifunction unit • Accumulator based • Control lines • Function select • Storage select • Data storage

CAD-DS [V. Sahula] Complex Data Path & Control Design 103

Instruction Set • 10 Single address instructions • 32 bit data

CAD-DS [V. Sahula] Complex Data Path & Control Design 104

52 Instruction Execution Sequence

• Fetching instruction, I – Content‐transfer from PC to AR of memory – Memory read, contents comes into DR • I’s opcode into IR • PC++ • Decode & Execute, I – IR contents transferred to PC – IR gets contents from ‐Control Memory (CM)

CAD-DS [V. Sahula] Complex Data Path & Control Design 105

Instruction, I

• Made of several micro‐instructions • Each instruction is multi‐cycle – CISC

– Each micro‐instruction takes one‐clock, TC

• Each instruction takes one clock, TC – RISC – Each micro‐instruction takes small part of large clock

period, TC

– Multi‐phase clock, TC

CAD-DS [V. Sahula] Complex Data Path & Control Design 106

53 Flow‐Chart [ASM] • Moore machine • Mealy machine – States s :s 0 12 – States s1:s6

CAD-DS [V. Sahula] Complex Data Path & Control Design 107

Control Unit‐ HW/microprogramed • Opcode in IR – Decoded in 10 signals, one per instruction type • Inputs – 10 signals from IR‐decoder BEGIN … 12

(AC  0) Control- :c – BEGIN 0 Unit c

– Status of AC, AC=0 • Outputs … 10 LZ ST … BZ – 13 Control signals, c0:c12 4 IR

CAD-DS [V. Sahula] Complex Data Path & Control Design 108

54 Control Signals • CPU datapath with control signals

CAD-DS [V. Sahula] Complex Data Path & Control Design 109

CAD-DS [V. Sahula] Complex Data Path & Control Design 110

55 Hardwired Control

• Mealy FSM – Merge execution

states, S5 S6 S8 S12 * – Into just 1 state S4

* S4  S5 S6 S8 S12 * S5  S2 S6 * S6  S5 S7

CAD-DS [V. Sahula] Complex Data Path & Control Design 111

Combinational Logic of CPU Control Unit‐ FSM with 1‐Hot Assignment

 D1  D1  BEGIN  D4 (MOV1 MOV 2  ADD  SUB  AND  NOT  BRA  BZ)  D6  D2  D1  BEGIN  D3  D2  D4  D3  D5  D4 (LD  ST )  D6  D5

c0  D1

c1  D2  D5  LD

c2  c4  D3

c3  D4 (BRA  BZ (AC  0))

c5  D4 (LD  ST )

CAD-DS [V. Sahula] Complex Data Path & Control Design 112

56 Hardwired Control Implementation

CAD-DS [V. Sahula] Complex Data Path & Control Design 113

Microprogrammed Control

CAD-DS [V. Sahula] Complex Data Path & Control Design 114

57 Control Memory (CM) Implementation

CAD-DS [V. Sahula] Complex Data Path & Control Design 115

Mealy FSM

• Control outputs to be derived from control fields, using 12 inputs • Each state has 2 branches at most

CAD-DS [V. Sahula] Complex Data Path & Control Design 116

58 CPU Microprogram‐ Control‐Memory contents

Memory Condition Branch C0 C1 C2 C’3 C4 C’5 C’6 C’7 C8 C’9 C’10 C’1 C’12 address Select Address 1 000 01 000 1 0 0 0 0 0 0 0 0 0 0 0 0 001 00 010 0 1 0 0 0 0 0 0 0 0 0 0 0 010 00 011 0 0 1 0 1 0 0 0 0 0 0 0 0 011 10 000 0 0 0 1 0 1 1 1 0 1 1 1 1 100 00 101 0 1 0 0 0 0 1 0 0 0 0 0 0 101 00 000 0 0 0 0 0 0 0 1 1 0 0 0 0

CAD-DS [V. Sahula] Complex Data Path & Control Design 117

Micro‐program Control (CISC)

nI: no. of micro-instructions BEGIN nC: no. of control signals Branch address 0 Condition_1 Load Condition_2 Mux PC control 1 Increment log2nI

Control 2 log2nI Memory

nI[2+log2nI+nC]

[2+ log2nI+nC] Control fields  Instruction register Condition select ? Multiple Decoding Branch address … nC CAD-DS [V. Sahula] Complex Data Path & Control Design 118

59 Control Design‐ Control Field Encoding

Micro‐Program Example

• Shift‐Add multiplier control • Identifying signals active simultaneously

CAD-DS [V. Sahula] Complex Data Path & Control Design 120

60 Identical Pattern Control Signals

• Group signals which are activated simultaneously – Redundant control field removal

LD LR RA SA LA LS END RC INCC 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

CAD-DS [V. Sahula] Complex Data Path & Control Design 121

Compatibility Class

• Group of signals – When no two signals are ever active simultaneously

LD LR RA SA LA LS END RC INCC 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1

C1={LD, LR, LA, LS, END}

C2={LR, RA, SA, LA, LS, END}

CAD-DS [V. Sahula] Complex Data Path & Control Design 122

61 Graph Theory‐ Max Clique Finding • Clique – A completely connected L subgraph D LR

LA LS

LD LR

RA END LA LS

CAD-DS [V. Sahula] Complex Data Path & Control Design 123

Optimization Algorithm

• To minimize total number of control fields

• Find a collection of compatibility classes {Ci}, such that

– Every control signal is contained in at least one {Ci} – The following function is minimum,

• is number of signals in {Ci} Ci

W   log2 Ci 1 i

CAD-DS [V. Sahula] Complex Data Path & Control Design 124

62 Graph Theory‐ Clique Partitioning

• Clique‐partitioning – Partitioning a

given graph into LD LR sub‐graphs such LA that each of them LS is a clique RA END

CAD-DS [V. Sahula] Complex Data Path & Control Design 125

Optimizing W

• C1={LD, LR, LA}

• C2={RA, SA, LS, END}

• W=log2(3+1)+log2(4+1) =2+3=5

• Control word of width 5 is sufficient

CAD-DS [V. Sahula] Complex Data Path & Control Design 126

63 Control Field Encoding a) Uncoded‐ 13 control fields b) Partially coded‐ 3 control fields c) Fully coded‐ single control field

CAD-DS [V. Sahula] Complex Data Path & Control Design 127

Encoded Micro‐instruction • Vertical micro‐instruction format – Max parrallelism – Min control‐field width

CAD-DS [V. Sahula] Complex Data Path & Control Design 128

64 Encoding by Function

• ADDER • SHIFT • COUNT • INBUS • OUTBUS

CAD-DS [V. Sahula] Complex Data Path & Control Design 129