High Performance Energy Efficient Near Threshold Circuits: Challenges and Opportunities

2012 MICRO Near Threshold Computing Workshop Keynote December 2012 Ram K. Krishnamurthy Senior Principal Engineer Circuits Research Lab, Circuits & Systems Research, Intel Labs Intel Corporation, Hillsboro, OR 97124, USA [email protected] Acknowledgements: Intel Circuits Research Lab, Vivek De, Rick Forand, Wen-Hann Wang, Shekhar Borkar, Greg Taylor, IPR Bangalore Design Lab, Stefan Rusu, Jim Held Era of Tera-scale Computing Teraflops of performance operating on Terabytes of data

Entertainment, learning and virtual travel Model-based Apps Recognition TIPS Financial Analytics Mining Synthesis Models GIPS Personal Media Creation and 3D & Management Video Mult- Terascale Performance MIPS Media Multi-core Text KIPS Single-core Health Kilobytes Megabytes Gigabytes Terabytes Dataset Size

2 Tera-scale Platform Vision

Special Integrated IO Cache Cache Cache Purpose Engines devices

Scalable On-die Interconnect Fabric

Last Level Last Level Last Level Integrated Off Die Cache Cache Cache Memory Controllers interconnect

Socket High Bandwidth IO Inter- Memory Connect

3 Silicon Process Technology Innovation

65nm 45nm 32nm 22nm 14nm 10nm 7nm 2005 2007 2009 2011 2013 * 2015 * 2017 * 2019+ MANUFACTURING DEVELOPMENT RESEARCH

Hi-K Tri-Gate *projected Process innovation leads to energy efficient performance and predictable 2-year technology cycles

4 22nm Performance and Energy Scaling

5 M. Bohr, Intel Developer Forum 2012 Silicon Integration Providing Greater End-User Value

• More transistors/area: enables substantial system-on-chip integration opportunities Extreme Scale (Exa-Scale) Computing Research 2W – 100 GigaFLOPS 20MW - ExaFLOPS

10 year goal: ~300X Improvement in energy efficiency Equal to 20 pJ/FLOP at the system level

J. Rattner, ISCA 2012 Keynote Ultra Low Power Graphics/Video & Security Circuits

10-100X higher performance/watt vs. GP cores Dedicated HW Intel ISSCC, VLSI 2008-2012 More flexible… 100x

More efficient… DSPs GOPS/W

Microprocessors 10x

Source: ISSCC Flexibility vs. energy-efficiency vs. Flexibility P4 x86 PPC PPC MUD Alpha Alpha Sparc Sparc2 Sparc1 MPEG2 MPEG2 Itanium 802.11a PPC770 PPC970 Encrypt SA-DSP Fuj-DSP Fuj-DSP Cell-SPE Fuj-Multi Video ME Video NEC-DSP PPC2-SOI PPC1-SOI KAIST-DSP Hitachi-DSP SIMD Vector SIMD AES Encryption AES SIMD Permutation SIMD DSP functions highly throughput-oriented: Amenable for parallelism/pipelining ⇒ Better power-performance optimization ⇒ Optimal partitioning of tasks between GP processor and dedicated engines 8 Specialized HW Accelerators for ExaExa----ScaleScale

General purpose cores, special-purpose accelerators, interconnect fabric Efficient, adaptive, reconfigurable, resilient

LowLowLow-Low ---powerpower generalgeneral----purposepurpose core SP HW accelerators

Fixed function vs. limited programmability Operation over wide supply voltage range (near-threshold to nominal)

9 NTV Operation & Energy Efficiency

4 2 10 10 65nm CMOS, 50°C 1 65nm CMOS, 50°C 450 10 375 10 3 10 1 300 1 10 2 1 225 9.6X (mW) 150 10 -1 10 1 10 -1 (GOPS/Watt) Total Power (mW) Power Total Energy-Efficiency Energy-Efficiency 75 Subthreshold 320mV

-2 Power Leakage Active 1 10 -2 0 10 Maximum (MHz) Frequency 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Supply Voltage (V) Supply Voltage (V) H. Kaul, R. Krishnamurthy et al, ISSCC 2008 Frequency reduces almost Energy efficiency improves by linearly first, then exponentially one order of magnitude at NTV Total power reduces by three to Energy efficiency reduces in four orders of magnitude subthreshold operation Leakage power reduces by two

to three orders of magnitude 10 NTV Across Technology Generations

H. Kaul, et. al., ISSCC 2009 3 S. K. Hsu, et. al., ISSCC 2012 3 9 10 10 45nm CMOS 8 22nm CMOS, 50°C 50 °C 7 32b Multiply

2 ) 6 10 5 16b SIMD W

Multiply 8X 9x m 4 (

3 2 r 10 10 e

2 w 1 o 300mV P

72b Add 1.1V 0 1 e g

Normalized Normalized Energy Efficiency 0.15 0.40 0.65 0.90 1.15 1.40 Vhi 9x 0.15 0.37 0.59 0.74 0.87 0.98 Vlo a k Region Supply Voltage (V) -1 a 10 10 e L A. Agarwal, et. al., ISSCC 2010 Sub-threshold 3.0 10 Reconfigurable Fabric, 32nm CMOS, 50 °C -2 2.5 10

1 (GOPS/W)EfficiencyEnergy 2.0 Register File 0.8mW Permute Crossbar -3 1.5 5.7x 10 -1 1 10 0.2 0.4 0.6 0.8 1.0 1.2 1.0 Supply Voltage (V) 10 -2 0.5 Sub-threshold Region Sub-threshold 340mV NTV operation improves energy -3

Energy Efficiency (TOPS/W) Efficiency Energy 0 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Leakage (mW) Active Power efficiency across 45nm-22nm Supply Voltage (V) CMOS 11 NTV Opportunities for Wide Dynamic Range

T. Thakkar, Intel Developer Forum 2012 ATOM™ 32nm SOC V/F Islands

SoC integration of many unrelated functions in their own power ‘islands’.

DDR GPIO • On-die voltage regulation leading to power ‘islands’ that can have different voltage levels. south • Power management that shuts functional units off. audio • Voltage-Frequency pairs; CPU’s can be run in several operating points where its power supply is adjusted to DDR complex reduce power while keeping various functional blocks at constant voltage: – lowest frequency: 100 - 600MHz – medium frequency: 700 - 1500MHz

security CPU – burst frequency: 1600 – 2500MHz

EMMC • OFF chip drivers have to support various voltage levels NC whereas the controller logic is powered by a lower 2D/3D PLLs clocks voltage : graphics – LPDDR: 1.25V video – MIPI-display: 1.25V

DDR– HDMI-display DDR 3.3V Image Signal – SD cards: 2.85V

GPIO Processor display – GPIO: 1.25V, 1.80V HDMI DDR GPIO MIPI DDR

T. Thakkar, Medfield, Intel Developer Forum 2012 NTV Opportunities for Converged Core

14 T. Piazza, Intel Developer Forum 2012 Impact of Variation on NTV

6 1.0 60% +/- 5% Variation in Vdd or Vt 5 0.8 50% Spread 4 40% 0.6 30% 3 0.4 20% 2 Freq (Relative) Freq

0.2 10% Frequency 1

0.0 0% noise 5% to vulnerability Circuit 0.0 0.2 0.4 0.6 0.8 1.0 0 1.0 0.9 0.8 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Vdd (Relative) Vdd scaling towards threshold Threshold (V −V )α frequency ∝ dd t V dd 5% variation in Vt or Vdd results in up to 50%

variation in circuit performance 15 Variation Modeling & Measurements

4 65nm CMOS, 50 °C 10 65nm CMOS Typical Die Measurements 1

10 3 ±5% 1.2V

Frequency variation 2 across 0-110 °C Frequency variation 10 across fast – slow dies ±2X ±18% 10 1 Normalized Distribution Normalized

Maximum Frequency (MHz) Frequency Maximum 50 °C 320mV ±2X 320mV 0 1 0.5 1.0 1.5 2.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Normalized Frequency Supply Voltage (V) H. Kaul, R. Krishnamurthy et al, ISSCC 2008 Monte-Carlo Simulations 18% nominal frequency spread 65nm CMOS measurements 2X spread at NTV 5% nominal spread due to temperature 16 2X spread at NTV Using Vdd to Compensate for Variation

56 56 65nm CMOS, 65nm CMOS, 320mV Typical Die 320mV, 50C 42 42

28 28

14 14 Frequency (MHz) Frequency Frequency (MHz) Frequency 23MHz 23MHz 0 0 0 50 110 Slow Typical Fast Temperature (C) Process Skew

• Adaptive Voltage Compensation for variation tolerance • Adjust supply voltage to maintain constant performance • ±50mV adjustment about 320mV: Nominal 23MHz performance sustained across 0-110°C and Intel Confidential fast-slow skews 17 Subthreshold Leakage at NTV

60%

50% 40% Vdd 40% Increasing Variations 30% 50% Vdd 75% Vdd 20% 100% Vdd SD Leakage Leakage Power SD 10%

0% 45nm 32nm 22nm 14nm 10nm 7nm 5nm

NTV operation reduces total power, improves energy efficiency Subthreshold leakage power is substantial portion of the total 18 Low Voltage SRAM and Register File 6T SRAM suffers stability and yield at NTV 6T SRAM cell with larger transistors 8T/10T SRAM for improved stability and yield

Variation tolerant register file for NTV wrbl# rdbl wrbl wrbl# rdbl Conventional dual-ended (DE) write cell Dual-ended transmission gatewrbl (Write failure due to strong P and weak N) (DETG) write cell S. Hsu, R. Krishnamurthy et al, ISSCC 2012 19 Low Voltage Latches and Flip-flops Designing flip-flops for NTV Averaging with vector flip-flops Upsized

Ck Ck Ck Ck Shared Ck Ck min-sized clock drivers D “0” “1”

Ck Ck Q

Non-minimum Channel Length

Vmin improves by 175 mV Hold time margin by 7 to 30%

20 Low Voltage Logic: Multiplexers & Gates

Designing multiplexers for NTV Transmission gates, logic gates Issue: Large off-current paths “1” Weak on-current paths “1” “1” Body effect “1” “0” “0”

“0” “0” “0”

“0” “0” One-hot 4:1 Encoded 4:1

Up to 3X reduction in worst case Avoid series connected static droop transmission gates

Logic fan in limited to 3 stack 21 Low Voltage Level Converters

CVSL Level Converter Low Voltage Significant energy High Voltage Circuit Block consumed in contention Circuit Block currents

Two-stage cascaded split-output level Ultra-low voltage split-output shifter level shifter

VCC MID VCC HIGH VCC HIGH CVSL CVSL Stage Stage 0

VCC LOW OUT VCC LOW MID VCC MID 0 IN

H. Kaul, R. Krishnamurthy et al, ISSCC 2009 CVSL split into two stages to reduce contention current Decoupled output from CVSL Decoupled output for smaller CVSL Interrupts contention devices 20% energy reduction Vmin improved by 125 mV 22 Soft Errors and Reliability 10 65nm 1 90nm Assuming 2X bit/latch 130nm count increase per 0.8 180nm generation 250nm Latch 0.6 0.4 Memory 0.2 Relative 130nm to Relative n-SER/cell (sea-level) n-SER/cell 0 1 0.5 1 1.5 2 180 130 90 65 45 32 Voltage (V) Technology (nm) Soft error/bit reduces each generation Soft error at the system level will Impact of NTV on soft error rate continue to increase Positive impact of NTV on reliability Low V lower E fields, low power lower temperature Device aging effects mitigated Lower electro-migration related defects

23 NTV SIMD Permutation Engine 256b Permutation Engine 22nm CMOS Chip Organization Micrograph

RdAdd0x RdAdd0y Register File RdData0x RdData0y Register File RdAdd1x RdData1x Permute RdData1y RdAdd1y RdAdd2x RdData2x Crossbar RdData2y RdAdd2y WrAdd0x 32x8b 32x8b WrAdd0y PermOut 3R1W 3R1W WrData0y WrData0x x16 x16 x16

32x128b 3R1W Register File Bank 256b Permute Crossbar (32 x 32:1) Vertical Shuffle Horizontal Shuffle RdData0x WrData0x RdData0x RdData0y 32 entries x32 8b

d3 128 e4 b1 d3 h7 d3 5:32 Decoder Bank15 RdData0x x32 Process 22nm CMOS c2 8b g6 d3 c2 g6 c2 128 Bank14 5:32 Decoder Nominal RdData1x 0.9V X16 x16 x16 x16 x16 Vcc x32 128 8b b1 f5 f5 b1 a0 b1 Permute 256b byte-wise any-to- 5:32 Decoder RdData2x x32 Xbar any a0 8b a0 c2 h7 e4 128 a0

Bank0 Bank1 Register 5:32 Decoder 32x256b 3R/1W File 2:1 2:1 2:1 2:1 5 5 2 RdData1y Die Area 0.048mm 16x5 256 mode mode WrAdd0x PAdd0y PAdd0x 16x5 RdAdd2x 16x5 16x5 RdAdd0x RdAdd1x Pad Count 30 •SIMD permutation operations are key for maximizing vector datapath utilization in multimedia, graphics, and signal processing workloads •SIMD vector permutation engine with 2-dimensional shuffle consists of register file for vertical shuffle and permutation crossbar for horizontal shuffle Logic and Memory V MIN Circuit Optimizations 32x256b 3R/1W Register 256b Permute Crossbar File Circuits Circuits RdLBL PLBL sel# RdLBL Q D FF C LS x128 Vccx 32:1 MUX 32:1 Vccx Vssx x128 pout Q D Q D FF C FF C Vssx WrBl# WrBl

•Register file and logic V MIN circuit optimizations enable NTV operation

•Register file V MIN techniques: (i) clock-less static CMOS reads, (ii) dual-ended transmission gate (DETG) writes with shared P/N

•Logic V MIN techniques: (i) vector flip-flops, (ii) stacked min-delay buffers, (iii) shared gates to average min-sized transistor variation, (iv) ultra low voltage split-output level shifters 22nm Simulations/Measurements Maximum Frequency and Energy Efficiency and Active Register File V MIN Total Power Simulations Leakage Measurements vs. Measurements vs. Supply Supply Voltage Voltage 3 10 4 10 4 10 3 10 22nm CMOS, 50°C 22nm CMOS, 50°C 585GOPS/W 10 3 154GOPS/W 10 2 10 3 9x

10 2 10 2 10 10 2 Sub-thresholdRegion

Permutation Engine V MIN 10 1 Simulations 9x 10 -1

1 Total Power (mW) 10 10 Leakage Power (mW) Sub-threshold Region Sub-threshold Maximum Frequency (MHz) 1 EfficiencyEnergy (GOPS/W) 10 -1 10 -2

Register File Register File Permute Crossbar Permute Crossbar -3 10 -1 10 -2 1 10 0.2 0.4 0.6 0.8 1.0 1.2 0.2 0.4 0.6 0.8 1.0 1.2 22nm V MIN simulations performed at Supply Voltage (V) 0°C -85 °C, Supply Voltage (V) 3σ systematic, 6σ random variation • VMIN improvement: register file V MIN by 250mV and logic V MIN by 150mV • Nominal: 1.8GHz, 0.9V, 50 °C down to sub-threshold: 16.8MHz, 280mV • Wide voltage supply scalability across 280mV - 1.1V increasing energy efficiency by 9x: Industry’s first Tri-Gate NTV Logic + Memory circuits S. Hsu, R. Krishnamurthy et al, ISSCC 2012 & JSSC January 2013 NTV Variable Precision FPU

H. Kaul, R. Krishnamurthy et al, ISSCC 2012

27 Experimental NTV Processor

1.1 mm Scan IA-32 Core Logic 951 Pin FCBGA Package

1.8 mm 1.8 Custom Interposer Level Shifters + clk spine

L1$-I L1$-D ROM

Technology 32nm High-K Metal Gate Interconnect 1 Poly, 9 Metal (Cu) Transistors 6 Million (Core) Core Area 2mm 2

Legacy Socket-7 Motherboard 28 S. Jain, et al, “A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS”, ISSCC 2012 NTV Design Methodology Normalized Delay Slowdown Due to Random Variations (6 σ)

Nominal Versus High Vt Devices Minimum/Small Sized Devices 7 12 Nominal Vt High Vt 0.5V 6 10

5 76% 8 130% 4 6

3 4

2 2

1 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1X 2X 3X 4X 5X Logic Vcc (V) Device Width 29 leakage Memory 1000 62% Frequency (MHz) 100 10 utrsodNTV Subthreshold 1 ...... 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.55 0.55 0.55 0.55 0.55 0.6 1% 32nm25 CMOS, 3MHz 2mW 4%

Subthreshold & PerformancePower 33% o C 17mW 100MHz Logic Logic Vcc / 53% 0.7 0.8 0.9 0.9 1 0.8 0.7 Memory VccMemory 5% 174mW 500MHz 27% 15% leakage Logic (V) 81% Super-threshold 1.1 1.1 1.2 Logicdynamic 915MHz 737mW 11% 100 200 300 400 500 600 700 800 0 3%

5% Total Power (mW) Power Total 30 Wide Dynamic Range

HIGH Subthreshold NTV Normal operating range

~5x Demonstrated ENERGY ENERGY EFFICENCY

LOW

ZEROVOLTAGE MAX Ultra-low Power Energy Efficient High Performance 280 mV 0.45 V 1.2 V 3 MHz 60 MHz 915 MHz 2 mW 10 mW 737 mW

1500 Mips/W 5830 Mips/W 1240 Mips/W 31 NTV Parallelism: On-chip Interconnect Global Compute 1.2 Compute Energy Interconnect 1 Interconnect Energy 0.8 0.6 1.6X Energy Relative 0.4 0.2 6X 0 45 32 22 14 10 7 Technology (nm) Supply Voltage

Compute energy reduces faster than global interconnect energy For constant throughput, NTV demands more parallelism Increases data movement at the system level System level optimization is required to determine NTV operating point 32 Circuit-Switched On-Chip Interconnects

M. Anders, R. Krishnamurthy et al, ISSCC 2010

33 Fine-grain Reconfigurable Fabrics RFA RFA Core0 Core0

Memory Memory

Core1 Core1 RFA

Reconfigurable Fabric Array (RFA)

RFA

Core Memory

Core

Reconfigurable fabric tightly Reconfigurable fabric directly coupled to processor pipeline interfaced with memory X1 Y0 X0 32nm Hybrid CLB Design 4 4 4 A. Agarwal, R. Krishnamurthy et al, ISSCC 2010 4 4 Y1 OutX 2 4 Hybrid 4 Y2 Y0[0] 3 LUT4 X2 OutY C 4 & 5 Input 4 CLB 4 4 1 LUT Merge 1 Y2 OutZ LUT5 3 2:1 x4 3 X0 4 4 C OutC Y0 4 Y0[3] Y0[2] Y0[1] 3 1 1 1 Cin0 Cin1 Cin2 OutC 4 Z 4 4 4 4 X0 Y0 Y1 Y2 4 Sum0 Sum1 OutZ t LUT3 4 u 4 4 O 4 4 OutY 4b Adder X2 4b Adder 4b Adder 4b Sum2 4 4 4 Output MUX 4

3-Input LUT 3-Input X0 X1 X2 OutX XY Cout0 Cout1 Cout2 ● Optimized for arithmetic with support for random logic ● Four 3-input Look-Up Tables (LUTs) ● Three 4b adders ● 27 inputs, 15 outputs, 43 configuration bits 35 32nm High-K/Metal-Gate CMOS Die Micrograph

Reconfigurable Control I/O I/O Fabric Clock

32nm High-K Process Metal-Gate CMOS Nominal Supply 1.0V Interconnect 9 metal Cu Number of CLBs 6 Register File Array 64-entry x 32b Die Area 0.076mm 2 Number of Transistors 110K Pad Count 30 36 255mV (Sub-threshold) operation in 32nm CMOS technology Industry’s first ultra-low-voltage reconfigurable accelerator A. Agarwal, R. Krishnamurthy et al, ISSCC 2010 1.5mm 3 Intraocular Pressure Monitor ● Continuous IOP monitoring ● Wireless communication ● Energy-autonomy ● Device components ● Solar cell ● Wireless transceiver ● Cap to digital converter ● Processor and memory ● Power delivery ● Thin-film Li battery ● MEMS capacitive sensor

● Biocompatible housing Courtesy: Gregory Chen, U. Michigan 38 Summary • Moore’s Law has fueled the worldwide technology revolution for over 40 years and will continue for at least another decade – 0.7x transistor dimension scaling every two years – Hi-K MG & Tri-Gate devices: significant energy-efficiency benefits • Key challenges for Sub-22nm 1-100TOPS/Watt SOC platforms – Special-purpose accelerators for graphics/video/media DSP – Ultra-low-voltage/NTV operation with wide dynamic voltage range – On-die reconfigurable logic fabrics/accelerators for flexible SOCs • Energy-efficient SOC graphics/media processing: – Reconfigurable SIMD vector permutation processor in 22nm – NTV processor with wide dynamic range in 32nm CMOS – Fine-grain reconfigurable logic array fabric in 32nm CMOS • Ultra-low voltage (NTV) circuit design challenges & opportunities – 5-10X higher energy efficiency (GOPS/W) vs. nominal supply operation 39 Legal Disclaimer This presentation contains the general insights and opinions of intel corporation (Intel). • This presentation is provided for informational purposes only and is not to be relied upon for any other purpose. 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