Data Path & Control Design‐ (i) Simple arithmetic computations (ii) Complex Datapath, Transcendental Functions Vineet Sahula [email protected] Dept. of ECE, MNIT Jaipur Text Marking 1.!!! 2.1 Design‐ representation 2.2.1 RTL components 2.2.3 Register level design 3.2 Data representation‐ Fixed & Floating point 4.1 Fixed point arithmetic, + ‐ × 4.2 ALU 4.3.1 Floating point arithmetic [4.3.2 Pipelining] 5.1 Control design basics‐ HW 5.2 Control basics‐ Microprogrammed CAD-DS [V. Sahula] Complex Data Path & Control Design 2 1 Arithmetic Digital Design • RTL symbols & Algorithm State Machine • Control Unit Design • Hard‐wired control • Micro‐programmed control • Example data path • GCD Computer • Shift Add multiplier • Processor‐ RISC/CISC • Complex data path • log • sin cos sin cos • FFT • Processor instruction design • Control field encoding CAD-DS [V. Sahula] Complex Data Path & Control Design 3 Register Transfer Symbols CAD-DS [V. Sahula] Complex Data Path & Control Design 4 2 Data Path Design CAD-DS [V. Sahula] Complex Data Path & Control Design 5 Data Path Components • Shifters Counters • Adders/Subtracters/Multipliers/Dividers • Multiplexers – 2P input m‐output MUX • Selectors Decoders • Magnitude comparator • Registers – PIPO, SISO CAD-DS [V. Sahula] Complex Data Path & Control Design 6 3 Arithmetic Data Path • Serial adder • 4‐bit parallel adder – Ripple carry (RCA) – Carry Look Ahead (CLA) – Carry save • Multiplication – Shift‐add – Booth’s coded • Division – Repeated subtraction – Repeated multiplication • Others – GCD computer CAD-DS [V. Sahula] Complex Data Path & Control Design 7 Ripple Carry Adder B An-1 n-1 An-2Bn-2 A0 B0 C Cn+1 n C 1-bit 1-bit 1-bit 1 C adder adder adder 0 S Sn-1 Sn-2 0 Si Ai Bi Ci1 Ci1 Ai Bi Ci (Ai Bi ) CAD-DS [V. Sahula] Complex Data Path & Control Design 8 4 Carry Look Ahead Adder‐ Truth Table Looking ahead “Carry” Table Ai Bi Ci Ci+1 pi gi 0 0 0 0 0 0 gi Ai Bi 0 1 0 0 0 0 p A B 1 0 0 0 0 0 i i i 1 1 0 1 0 1 0 0 1 0 0 0 Ci1 gi piCi 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 CAD-DS [V. Sahula] Complex Data Path & Control Design 9 CLA‐ 1‐Bit HA‐ implementation Ai Bi Ai Bi Ai Bi Ai Bi Si S i S i gi Ai Bi gi pi pi Ai Bi CAD-DS [V. Sahula] Complex Data Path & Control Design 10 5 Carry Look Ahead Adder An-1Bn-1 An-2Bn-2 A0 B0 C 1-bit Cn-1 1-bit Cn-2 1-bit 0 HA- HA- HA- Sn-1 Sn-2 S0 p gn-2 pn-1gn-1 n-2 p0 g0 C n Carry-Look Ahead generator CAD-DS [V. Sahula] Complex Data Path & Control Design 11 Carry Save Adder‐ Principle W,X,Y,Z n‐bit numbers to be added 1. Add X,Y,Z using CSA (Ouput is C,S ) Wallace Tree 2. Add W,C,S using CSA (Ouput is C’,S’ ) 3. Add C’ and S’ Using RCA X YZ 1101 + 0111 CSA 1001 ---------- W CS S 00011 Saved carry C 11010 CSA W 01010 C’ S’ ------- Cout 0--- RCA Saved carry S’ 100110 --------- C’ 01010 Merged - Sum carry CAD-DS [V. Sahula] Complex Data Path & Control Design 12 SUM 100111 6 Carry Save Adder‐ Implementation Z3 Z2 Z1 Z0 X Y 3 3 X2Y2 X1Y1 X0Y0 1-bit 1-bit 1-bit 1-bit adder adder adder adder W3 W2 W1 W0 1-bit 1-bit 1-bit 1-bit adder adder adder adder C’3 C’2 C’1 C’0 S’3 S’2 S’1 S’0 CAD-DS [V. Sahula] Complex Data Path & Control Design 13 Multiplication Principle j Pi1 Pi rj 2 D Forming Partial products Pi’s 3 j S rj 2 D 0100 D3D2D1D0 j0 P 0 R3R2R1R0 0011 P3 ---------- -------------------- 0100 P03P02P01P00 0100 P13P12P11P10 j Pi1 2 Pi rj D 0000 P23P22P21P20 P3 n3 P33P32P31P30 j3 0000 S rj 2 D ---------- --------------------- j0 0001100 S7 S6 S5 S4 S3 S2 S1 S0 P3 CAD-DS [V. Sahula] Complex Data Path & Control Design 14 7 Modified Booth Coding 0100 1111 Booth Recoding Table ---------- f f f f Ri+1 Ri fi RRi fi+1 3 2 1 0 0 0 0 0 0 0100 001 1 1 1 0 1 0 1 0 0100 1 0 0 0 0 0100 Booth coded 1 1 0 ī 1 0 0 1 1 0 0100 1000î 0 1 1 0 1 ---------- 1 addition 1 0 1 ī 1 01 1 1 100 1 subtraction 1 1 1 0 1 ---------- 4 additions CAD-DS [V. Sahula] Complex Data Path & Control Design 15 Alternate Methods for Pi • P1 = P0 + p1 – Recursively compute, Pi = Pi‐1 + pi – requires ONLY one ADDER – For n‐bit numbers, requires n steps • SUM all Pi s together – needs n/2 adders – Need n/4 adders further for summing n/2 such outputs – … – … till, n/2m=1 – m=log2 n is depth of Adder‐tree, total ADDERS=n‐1 – ONE step process CAD-DS [V. Sahula] Complex Data Path & Control Design 16 8 Sum All Pistogether … • Adder Tree with depth m for n numbers + + + + + + + + + + A ONE step process Wallace Tree Multiplier + CAD-DS [V. Sahula] Complex Data Path & Control Design 17 Fixed Point Array Multiplier‐ AND Array CAD-DS [V. Sahula] Complex Data Path & Control Design 18 9 Fixed Point Array Multiplier‐ Adder Array CAD-DS [V. Sahula] Complex Data Path & Control Design 19 Fixed Point Array Multiplier‐ Array Cell CAD-DS [V. Sahula] Complex Data Path & Control Design 20 10 Shift Add Multiplier 8 INBUS D/R 8 R0 ShiftA LoadD MultiplicanD LoadA Accumulator MultiplieR ResetA LoadR 8 8 8 8 Adder/Subtracter 8-bit Reset Shift n LoadS Load Output S R A 0 Load Start Controller R 16 bit Load Clock D ResetA OUTBUS Load S S CAD-DS [V. Sahula] Complex Data Path & Control Design 21 GCD Computer: RTL Description gcd (IN: X, Y; OUT:Z) REGISTER XR, YR, TEMPR; XR:=X; (Start & Input) YR:=Y; WHILE (XR>0) DO BEGIN IF (XR YR) THEN BEGIN TEMPR:=YR; (Swap) YR:=XR; XR:=TEMPR; END XR:=XR-YR; (Sutract) END Z:=YR; (Output & End) END gcd; CAD-DS [V. Sahula] Complex Data Path & Control Design 22 11 Example Check of GCD algorithm Conditions Actions XR := 20; YR :=12 XR > 0 XR > YR XR := XR-YR := 8; XR > 0 XR YR YR := 8; XR := 12; XR := XR-YR = 4; XR >0 XR YR YR := 4; XR := 8; XR := XR-YR = 4; XR > 0 XR YR YR := 4; XR := 4; XR := XR-YR = 0; XR 0 Z := 4; CAD-DS [V. Sahula] Complex Data Path & Control Design 23 Data Path‐ GCD Computer Z X Y Reset Control Unit Subtract Multiplexers MUX Swap Select XY Load XR Register YR Register XR Load YR Subtractor Comparators (XR YR) (XR > 0) Datapath Unit CAD-DS [V. Sahula] Complex Data Path & Control Design 24 12 Division Principles‐ Repeated Subtraction 8-bit numbers _______ 8 steps R0=D 101 ) 100 1 1 0 R R q 2iV 000 i1 i i -------------- 0 R 2iV i 100 1 q 1 0 1 i i 1 Ri 2 V -------------- 10 0 1 1 0 1 -------------- Ri1 2Ri qiV 1 0 00 0 2R V 1 01 2R0=D i -------------- qi 0 1 1 1 2Ri V CAD-DS [V. Sahula] Complex Data Path & Control Design 25 Division: (2)Repeated Multiplication D (16bit) Q V (8bit) 0.4 0.4 0.4(1 0.3) 0.7 (1 0.3) (1 0.3)(1 0.3) 0.4(1 0.3) 0.4(1 0.3)(1 0.32 ) (1 0.32 ) (1 0.32 )(1 0.32 ) 0.4(1 0.3)(1 0.32 ) 0.4(1 0.3)(1 0.32 )(1 0.34 ) (1 0.34 ) (1 0.34 )(1 0.34 ) n 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 ) (1 0.3n ) 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3n ) (1 0.3n )(1 0.3n ) n 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 )(1 0.3n ) (1 0.32n ) n 0.4(1 0.3)(1 0.32 )(1 0.34 )...(1 0.3 2 )(1 0.3n ) When 0.32n 1 CAD-DS [V. Sahula] Complex Data Path & Control Design 26 13 Repeated Multiplication‐ Algorithm 1. Load D 2. Load R 3. X=(1‐R) 4. Y=(1+X) 5. D=D*Y 6. R=R*Y 7. If R is sufficiently close to 1.0 GOTO Step 8. Else GOTO Step 3. 8. Output D 9. Stop CAD-DS [V. Sahula] Complex Data Path & Control Design 27 FLOATING POINT ARITHMETIC CAD-DS [V. Sahula] Complex Data Path & Control Design 28 14 Data Format Classification • Instructions [Control] • Data CAD-DS [V. Sahula] Complex Data Path & Control Design 29 Fixed Point Numbers Signed binary numbers CAD-DS [V. Sahula] Complex Data Path & Control Design 30 15 Exceptional Conditions • Overflow/Underflow Z=X+Y zi=xi yici‐1 ci=xi yi+ xici‐1 +yici‐1 • v indicates overflow v=x’n‐1 y’n‐1cn‐2 + xn‐1 yn‐1c’n‐2 CAD-DS [V. Sahula] Complex Data Path & Control Design 31 Floating Point Numbers • Format (‐1)S (1.M) BE (‐1)S 2E‐127 (1.M) Binary FP no.