NVAX Plus CPU Chip Functional Specification The NVAX Plus CPU Chip is a high-performance, single-chip implementation of the VAX Architecture for use in low-end and mid-range systems. Revision/Update Information: This is Revision 0.1 of this specification, the initial external release DIGITAL RESTRICTED DISTRIBUTION This information shall not be disclosed to persons other than DIGITAL employees or generally distributed within DIGITAL. Distribution is restricted to persons authorized and designated by the originating organization. This document shall not be transmitted electronically, copied unless authorized by the originating organization, or left unattended. When not in use, this document shall be stored in a locked storage area. These restrictions are enforced until this document is reclassified by the originating organization. Semiconductor Engineering Group Digital Equipment Corporation, Hudson, Massachusetts This is copy number February 1991 The drawings and specifications in this document are the property of Digital Equipment Corporation and shall not be reproduced or copied or used in whole or in part as the basis for the manufacture or sale of items without written permission. The information in this document may be changed without notice and is not a commitment by Digital Equipment Corporation. Digital Equipment Corporation is not responsible for any errors in this document. This specification does not describe any program or product that is currently available from Digital Equipment Corporation, nor is Digital Equipment Corporation committed to implement this specification in any program or product. Digital Equipment Corporation makes no commitment that this document accurately describes any product it might ever make. Copyright ©1991 by Digital Equipment Corporation All Rights Reserved Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: DEC ULTRIX VAXstation DECnet ULTRIX–32 VMS DECUS UNIBUS VT MicroVAX VAX MicroVMS VAXBI TM PDP VAXcluster d i g i t a l Contents CHAPTER 1 INTRODUCTION 1–1 1.1 SCOPE AND ORGANIZATION OF THIS SPECIFICATION 1–1 1.2 RELATED DOCUMENTS 1–1 1.3 TERMINOLOGY AND CONVENTIONS 1–2 1.3.1 Numbering 1–2 1.3.2 UNPREDICTABLE and UNDEFINED 1–2 1.3.3 Ranges and Extents 1–2 1.3.4 Must be Zero (MBZ) 1–2 1.3.5 Should be Zero (SBZ) 1–2 1.3.6 Register Format Notation 1–3 1.3.7 Timing Diagram Notation 1–5 1.4 REVISION HISTORY 1–6 CHAPTER 2 ARCHITECTURAL SUMMARY 2–1 2.1 OVERVIEW 2–1 2.2 VISIBLE STATE 2–1 2.2.1 Virtual Address Space 2–1 2.2.2 Physical Address Space 2–2 2.2.2.1 Physical Address Control Registers • 2–4 2.2.3 Registers 2–4 2.3 DATA TYPES 2–6 2.4 INSTRUCTION FORMATS AND ADDRESSING MODES 2–8 2.4.1 Opcode Formats 2–8 2.4.2 Addressing Modes 2–8 2.4.3 Branch Displacements 2–11 2.5 INSTRUCTION SET 2–11 2.6 MEMORY MANAGEMENT 2–25 2.6.1 Memory Management Control Registers 2–25 2.6.2 System Space Address Translation 2–26 2.6.3 Process Space Address Translation 2–27 2.6.3.1 P0 Region Address Translation • 2–27 2.6.3.2 P1 Region Address Translation • 2–28 2.6.4 Page Table Entry 2–30 2.6.5 Translation Buffer 2–31 2.7 EXCEPTIONS AND INTERRUPTS 2–32 2.7.1 Interrupts 2–32 2.7.1.1 Interrupt Control Registers • 2–33 DIGITAL RESTRICTED DISTRIBUTION iii Contents 2.7.2 Exceptions 2–34 2.7.2.1 Arithmetic Exceptions • 2–35 2.7.2.2 Memory Management Exceptions • 2–36 2.7.2.3 Emulated Instruction Exceptions • 2–37 2.7.2.4 Machine Check Exceptions • 2–39 2.7.2.5 Console Halts • 2–39 2.8 SYSTEM CONTROL BLOCK 2–40 2.8.1 System Control Block Vectors 2–40 2.8.2 System Control Block Layout 2–41 2.9 CPU IDENTIFICATION 2–43 2.10 SYSTEM IDENTIFICATION 2–43 2.11 PROCESS STRUCTURE 2–45 2.12 MAILBOX STRUCTURE 2–47 2.12.1 Mailbox Operation 2–49 2.13 PROCESSOR REGISTERS 2–51 2.14 REVISION HISTORY 2–62 CHAPTER 3 EXTERNAL INTERFACE 3–1 3.1 OVERVIEW 3–1 3.2 SIGNALS 3–1 3.2.1 Clocks 3–3 3.2.2 DC_OK and Reset 3–4 3.2.3 Initialization and Diagnostic Interface 3–5 3.2.4 Address Bus 3–5 3.2.5 Data Bus 3–6 3.2.6 External Cache Control 3–7 3.2.6.1 The TagAdr RAM • 3–7 3.2.6.2 The TagCtl RAM • 3–8 3.2.6.3 The Data RAM • 3–8 3.2.6.4 Backmaps • 3–9 3.2.6.5 External Cache Access • 3–9 3.2.6.5.1 HoldReq and HoldAck • 3–9 3.2.6.5.2 TagOk • 3–10 3.2.7 External Cycle Control 3–11 3.2.8 Primary Cache Invalidate 3–13 3.2.9 Interrupts 3–14 3.2.10 Electrical Level Configuration 3–14 3.2.11 Testing 3–14 3.3 64-BIT MODE 3–14 3.4 TRANSACTIONS 3–14 3.4.1 Reset 3–14 3.4.2 Fast External Cache Read Hit 3–15 3.4.3 Fast External Cache Write Hit 3–16 3.4.4 Fast External Cache Byte/Word Write Hit 3–16 3.4.5 Transfer to SysClk for External tranactions 3–17 iv DIGITAL RESTRICTED DISTRIBUTION Contents 3.4.6 READ_BLOCK Transaction 3–17 3.4.7 Write Block 3–18 3.4.8 LDxL Transaction 3–19 3.4.9 STxC Transaction 3–20 3.4.10 BARRIER Transaction 3–21 3.4.11 FETCH Transaction 3–21 3.4.12 FETCHM Transaction 3–21 3.5 SUMMARY OF NVAX PLUS OPTIONS 3–21 3.6 REVISION HISTORY 3–22 CHAPTER 4 CHIP OVERVIEW 4–1 4.1 NVAX PLUS CPU CHIP BOX AND SECTION OVERVIEW 4–1 4.1.1 The Ibox 4–2 4.1.2 The Ebox and Microsequencer 4–3 4.1.3 The Fbox 4–3 4.1.4 The Mbox 4–4 4.1.5 The Cbox 4–4 4.1.6 Major Internal Buses 4–4 4.2 REVISION HISTORY 4–5 CHAPTER 5 MACROINSTRUCTION AND MICROINSTRUCTION PIPELINES 5–1 5.1 INTRODUCTION 5–1 5.2 PIPELINE FUNDAMENTALS 5–1 5.2.1 The Concept of a Pipeline 5–1 5.2.2 Pipeline Flow 5–3 5.2.3 Stalls and Exceptions in an Instruction Pipeline 5–5 5.3 NVAX PLUS CPU PIPELINE OVERVIEW 5–6 5.3.1 Normal Macroinstruction Execution 5–8 5.3.1.1 The Ibox • 5–8 5.3.1.2 The Microsequencer • 5–9 5.3.1.3 The Ebox • 5–9 5.3.1.4 The Fbox • 5–10 5.3.1.5 The Mbox • 5–10 5.3.1.6 The Cbox • 5–11 5.3.2 Stalls in the Pipeline 5–11 5.3.2.1 S0 Stalls • 5–12 5.3.2.2 S1 Stalls • 5–12 5.3.2.3 S2 Stalls • 5–13 5.3.2.4 S3 Stalls • 5–14 5.3.2.5 S4 Stalls • 5–15 5.3.3 Exception Handling 5–16 5.3.3.1 Interrupts • 5–17 5.3.3.2 Integer Arithmetic Exceptions • 5–17 5.3.3.3 Floating Point Arithmetic Exceptions • 5–17 5.3.3.4 Memory Management Exceptions • 5–18 5.3.3.5 Translation Buffer Miss • 5–19 5.3.3.6 Reserved Addressing Mode Faults • 5–19 5.3.3.7 Reserved Operand Faults • 5–20 DIGITAL RESTRICTED DISTRIBUTION v Contents 5.3.3.8 Exceptions Occurring as the Consequence of an Instruction • 5–20 5.3.3.9 Trace Fault • 5–20 5.3.3.10 Conditional Branch Mispredict • 5–20 5.3.3.11 First Part Done Handling • 5–21 5.3.3.12 Cache and Memory Hardware Errors • 5–21 5.4 REVISION HISTORY 5–22 CHAPTER 6 MICROINSTRUCTION FORMATS 6–1 6.1 EBOX MICROCODE 6–1 6.1.1 Data Path Control 6–1 6.1.2 Microsequencer Control 6–3 6.2 IBOX CSU MICROCODE 6–4 6.3 REVISION HISTORY 6–5 CHAPTER 7 THE IBOX 7–1 7.1 OVERVIEW 7–1 7.1.1 Introduction 7–1 7.1.2 Functional Overview 7–2 7.2 VIC CONTROL AND ERROR REGISTERS 7–4 7.3 VIC PERFORMANCE MONITORING HARDWARE 7–6 7.4 IBOX IPR TRANSACTIONS 7–7 7.4.1 IPR Reads 7–7 7.4.2 IPR Writes 7–7 7.5 BRANCH PREDICTION IPR REGISTER 7–8 7.6 TESTABILITY 7–9 7.6.1 Overview 7–9 7.6.2 Internal Scan Register and Data Reducer 7–9 7.6.3 Parallel Port 7–10 7.6.4 Architectural Features 7–10 7.6.5 Metal 3 Nodes 7–10 7.6.6 Issues 7–10 7.7 PERFORMANCE MONITORING HARDWARE 7–10 7.7.1 Signals 7–10 7.8 REVISION HISTORY 7–11 CHAPTER 8 THE EBOX 8–1 8.1 CHAPTER OVERVIEW 8–1 8.2 INTRODUCTION 8–1 8.3 EBOX OVERVIEW 8–4 8.3.1 Microword Fields 8–4 8.3.1.1 Microsequencer Control Fields • 8–6 8.3.2 The Register File 8–6 vi DIGITAL RESTRICTED DISTRIBUTION Contents 8.3.3 ALU and Shifter 8–6 8.3.3.1 Sources of ALU and Shifter Operands • 8–6 8.3.3.2 ALU Functions • 8–6 8.3.3.3 Shifter Functions • 8–6 8.3.3.4 Destinations of ALU and Shifter Results • 8–7 8.3.4 Ibox-Ebox Interface 8–7 8.3.5 Other Registers and States 8–8 8.3.6 Ebox Memory Access 8–9 8.3.7 CPU Control Functions 8–9 8.3.8 Ebox Pipeline 8–9 8.3.9 Pipeline Stalls 8–10 8.3.10 Microtraps, Exceptions, and Interrupts 8–11 8.3.11 Ebox IPRs 8–12 8.3.11.1 IPR 124, Patchable Control Store Control Register • 8–12 8.3.11.2 IPR 125, Ebox Control Register • 8–13 8.3.12 Initialization 8–14 8.3.13 Testability 8–14 8.3.13.1 Parallel Port Test Features • 8–14 8.3.13.2 Observe Scan • 8–15 8.3.13.3 E%WBUS<31:0> LFSR • 8–15 8.3.14 Revision History 8–15 CHAPTER 9 THE MICROSEQUENCER 9–1 9.1 OVERVIEW 9–1 9.2 FUNCTIONAL DESCRIPTION 9–1 9.2.1 Introduction 9–2 9.2.2 Control Store 9–2 9.2.2.1 Patchable Control Store • 9–2 9.2.2.2 Microsequencer Control Field of Microcode • 9–2 9.2.2.3 MIB Latches • 9–4 9.2.3 Next Address Logic 9–5 9.2.3.1 CAL and CAL INPUT BUS • 9–5 9.2.3.1.1 Microtest Bus • 9–5 9.2.3.2 Microtrap Logic • 9–7 9.2.3.3 Last Cycle Logic • 9–7 9.2.3.4 Microstack • 9–8 9.2.4 Stall Logic 9–8 9.3 INITIALIZATION 9–8 9.4 MICROCODE RESTRICTIONS 9–8 9.5 TESTABILITY 9–9 9.5.1 Test Address 9–9 9.5.2 MIB Scan Chain 9–10 9.6 REVISION HISTORY 9–10 DIGITAL RESTRICTED DISTRIBUTION vii Contents CHAPTER 10 THE INTERRUPT SECTION 10–1 10.1 OVERVIEW 10–1 10.2 INTERRUPT SUMMARY 10–1 10.2.1 External Interrupt Requests Received by Level-Sensitive Logic 10–2 10.2.2 Internal Interrupt Requests 10–2 10.2.3 Special Considerations for Interval Timer Interrupts 10–3 10.2.4 Priority of Interrupt Requests 10–3 10.3 INTERRUPT SECTION STRUCTURE 10–5 10.3.1 Synchronization Logic 10–5 10.3.2 Interrupt State Register 10–6 10.3.3 Interrupt Generation Logic 10–7 10.4 EBOX MICROCODE INTERFACE 10–8 10.5 PROCESSOR REGISTER INTERFACE 10–10 10.6 INTERRUPT SECTION INTERFACES 10–11 10.6.1 Ebox Interface 10–11 10.6.1.1 Signals From Ebox • 10–11 10.6.1.2 Signals To Ebox • 10–11 10.6.2 Microsequencer Interface 10–11 10.6.2.1 Signals from Microsequencer • 10–11 10.6.2.2 Signals To Microsequencer • 10–11 10.6.3